xref: /aosp_15_r20/external/mesa3d/src/panfrost/compiler/valhall/test/assembler-cases.txt (revision 6104692788411f58d303aa86923a9ff6ecaded22) 
102 00 00 00 00 c1 91 00    MOV.i32 r1, r2
28a 00 00 00 00 c1 91 00    MOV.i32 r1, u10
3e3 00 00 00 00 c1 91 02    MOV.i32 r1, thread_local_pointer.w1
4e6 00 00 00 00 c1 91 02    MOV.i32 r1, workgroup_local_pointer.w0
5e2 00 00 00 00 c1 91 06    MOV.i32 r1, lane_id.w0
6e6 00 00 00 00 c1 91 06    MOV.i32 r1, core_id.w0
701 02 00 00 00 c0 a4 00    FADD.f32 r0, r1, r2
801 02 00 00 20 c0 a4 00    FADD.f32 r0, r1, r2.abs
901 02 00 00 10 c0 a4 00    FADD.f32 r0, r1, r2.neg
1001 02 00 00 30 c0 a4 00    FADD.f32 r0, r1, r2.neg.abs
1101 02 00 00 32 c0 a4 00    FADD.f32.clamp_m1_1 r0, r1, r2.neg.abs
1241 03 00 00 00 c0 1f 50    BRANCHZ.reconverge ^r1, offset:3
1301 d0 00 00 00 c0 a4 00    FADD.f32 r0, r1, 0x3F800000
1401 d0 00 00 10 c0 a4 00    FADD.f32 r0, r1, 0x3F800000.neg
1501 c0 00 00 00 c0 a4 00    FADD.f32 r0, r1, 0x0
1601 c0 00 00 10 c0 a4 00    FADD.f32 r0, r1, 0x0.neg
1701 c9 00 00 00 c0 a0 00    IADD.u32 r0, r1, 0x7060504
1801 00 00 08 00 c0 a4 00    FADD.f32 r0, r1, r0.h1
1901 00 00 04 00 c0 a4 00    FADD.f32 r0, r1, r0.h0
2001 00 00 0c 00 c0 a5 00    FADD.v2f16 r0, r1.h00, r0.h11
2101 00 00 28 00 c0 a5 00    FADD.v2f16 r0, r1, r0
2201 00 00 24 00 c0 a5 00    FADD.v2f16 r0, r1, r0.h10
2301 02 00 08 00 c0 a0 00    IADD.u32 r0, r1, r2.h0
2401 02 00 0c 00 c0 a0 00    IADD.u32 r0, r1, r2.h1
2501 02 00 0c 70 c0 a0 00    IADD.u32 r0, r1.b3, r2.h1
2601 c9 00 18 00 c0 a0 00    IADD.u32 r0, r1, 0x7060504.b2
2701 02 00 08 20 c0 a1 00    IADD.v2u16 r0, r1, r2
2882 3c 27 20 00 c0 a3 01    SHADDX.u64 r0, u2, r60.w0, shift:0x2
2940 00 00 18 82 80 60 08    LOAD.i32.unsigned.slot0.wait0 @r0, ^r0, offset:0
3080 7c 47 20 00 c0 a3 01    SHADDX.u64 r0, u0, ^r60.w0, shift:0x4
3140 00 00 38 08 44 61 78    STORE.i128.slot0.end @r4:r5:r6:r7, ^r0, offset:0
3200 00 00 00 00 c0 00 78    NOP.end
3340 c4 c0 9c 01 c1 f0 00    ICMP_OR.u32.gt.m1 r1, ^r0, 0x1000000.b3, 0x0
3442 00 00 18 02 40 61 50    STORE.i32.slot0.reconverge @r0, ^r2, offset:0
3500 c9 8f 12 30 c0 a0 00    CLPER.i32.f1 r0, r0, 0x7060504.b0
3600 00 00 30 00 c7 90 00    S8_TO_S32 r7, r0.b3
3700 00 00 20 00 c6 90 00    S8_TO_S32 r6, r0.b2
3800 00 00 00 00 c4 90 00    S8_TO_S32 r4, r0.b0
3940 00 00 10 00 c5 90 00    S8_TO_S32 r5, ^r0.b1
4000 00 01 30 00 c7 90 00    S8_TO_F32 r7, r0.b3
4100 00 0f a0 00 40 90 00    FROUND.v2f16.rtn r0.h0, r0
4201 00 0f 90 00 40 90 00    FROUND.v2f16.rtn r0.h0, r1.h10
4301 00 0f a0 00 41 90 00    FROUND.v2f16.rtn r1.h0, r1
4400 00 0f 90 00 40 90 00    FROUND.v2f16.rtn r0.h0, r0.h10
4500 00 0b 00 00 c2 90 00    F16_TO_F32 r2, r0.h0
4640 00 0b 10 00 c3 90 00    F16_TO_F32 r3, ^r0.h1
4700 00 00 00 00 c0 00 40    NOP.wait0126
4842 43 04 00 00 c0 a5 00    V2F32_TO_V2F16 r0, ^r2, ^r3
4940 c0 00 28 90 c0 a5 48    FADD.v2f16.wait r0, ^r0.abs, 0x0.neg
50c0 00 00 00 00 f6 10 01    IADD_IMM.i32 r54, 0x0, #0x0
513c d0 ea 00 02 bc 7d 68    ATEST.discard @r60, r60, 0x3F800000, atest_datum.w0
5240 db 05 04 00 c1 a1 00    MKVEC.v2i16 r1, ^r0.h00, 0x3C000000.h10
53f0 00 3c 33 04 40 7f 78    BLEND.slot0.v4.f16.end @r0:r1, blend_descriptor_0.w0, r60, target:0x0
547b 0d 00 40 04 84 5e 08    LEA_BUF_IMM.slot1.wait0 @r4:r5, ^r59, table:0xD, index:0x0
5500 dd c0 08 14 c2 b2 00    FMA.f32 r2, r0, 0x44000000.neg.h1, 0x0.neg
5641 88 c0 00 04 c1 b2 00    FMA.f32 r1, ^r1, u8, 0x0.neg
5740 88 c0 00 04 c0 b2 10    FMA.f32.wait1 r0, ^r0, u8, 0x0.neg
5844 00 00 32 06 40 61 78    STORE.i96.estream.slot0.end @r0:r1:r2, ^r4, offset:0
5944 00 00 39 08 48 61 78    STORE.i128.istream.slot0.end @r8:r9:r10:r11, ^r4, offset:0
6000 00 00 c0 01 c0 45 48    BARRIER.slot7.wait
6180 00 00 00 82 82 60 00    LOAD.i8.unsigned.slot0 @r2, u0, offset:0
6280 00 00 08 82 82 60 00    LOAD.i16.unsigned.slot0 @r2, u0, offset:0
6380 00 00 10 82 82 60 00    LOAD.i24.unsigned.slot0 @r2, u0, offset:0
6480 00 00 18 82 82 60 00    LOAD.i32.unsigned.slot0 @r2, u0, offset:0
6580 00 00 20 c4 82 60 00    LOAD.i48.unsigned.slot0 @r2:r3, u0, offset:0
6680 00 00 28 f4 82 60 00    LOAD.i64.unsigned.slot0 @r2:r3, u0, offset:0
6780 00 00 30 e6 82 60 00    LOAD.i96.unsigned.slot0 @r2:r3:r4, u0, offset:0
6880 00 00 38 f8 84 60 00    LOAD.i128.unsigned.slot0 @r4:r5:r6:r7, u0, offset:0
6980 00 00 18 94 82 60 00    LOAD.i32.d0.unsigned.slot0 @r2:r3, u0, offset:0
7080 00 00 18 14 82 60 00    LOAD.i32.d0.slot0 @r2:r3, u0, offset:0
7180 00 00 08 34 82 60 00    LOAD.i16.d0.slot0 @r2:r3, u0, offset:0
7280 00 00 00 74 82 60 00    LOAD.i8.d0.slot0 @r2:r3, u0, offset:0
7380 00 00 00 f4 82 60 00    LOAD.i8.d0.unsigned.slot0 @r2:r3, u0, offset:0
7480 00 00 08 22 82 60 00    LOAD.i16.w0.slot0 @r2, u0, offset:0
7580 00 00 00 62 82 60 00    LOAD.i8.w0.slot0 @r2, u0, offset:0
7680 00 00 00 c2 82 60 00    LOAD.i8.h0.unsigned.slot0 @r2, u0, offset:0
7780 14 00 08 92 82 60 00    LOAD.i16.h1.unsigned.slot0 @r2, u0, offset:20
7880 00 00 08 82 82 60 00    LOAD.i16.unsigned.slot0 @r2, u0, offset:0
7942 00 0d 80 40 c2 90 00    FROUND.f32.rtn r2, ^r2.neg
8042 00 0b 00 40 c2 90 00    F16_TO_F32 r2, ^r2.neg.h0
8142 00 0c c0 40 c2 90 00    F32_TO_S32.rtz r2, ^r2.neg
8242 00 0e e0 40 c2 90 00    V2F16_TO_V2S16.rtz r2, ^r2.neg
8302 00 0a c0 40 c4 90 00    F16_TO_S32.rtz r4, r2.neg.h00
8442 00 0a d0 40 c5 90 00    F16_TO_S32.rtz r5, ^r2.neg.h10
8542 c0 c6 47 48 c2 14 01    FADD_IMM.f32 r2, ^r2, #0x4847C6C0
8642 84 67 ac 70 c2 15 01    FADD_IMM.v2f16 r2, ^r2, #0x70AC6784
8742 14 13 12 ad c2 12 01    IADD_IMM.v4i8 r2, ^r2, #0xAD121314
8842 14 00 13 00 c2 11 01    IADD_IMM.v2i16 r2, ^r2, #0x130014
8942 ab 4b 00 00 c2 10 01    IADD_IMM.i32 r2, ^r2, #0x4BAB
9043 42 c0 84 11 c2 f9 00    ICMP_OR.v2s16.gt.m1 r2, ^r3.h10, ^r2.h10, 0x0
9143 42 c0 90 01 c2 f5 00    FCMP_OR.v2f16.gt.m1 r2, ^r3.h10, ^r2.h00, 0x0
9242 00 07 00 20 c2 90 00    V2S16_TO_V2F16 r2, ^r2
9300 c0 c0 00 43 c1 f2 00    ICMP_OR.v4u8.ne.i1 r1, r0.b0000, 0x0, 0x0
9441 03 00 00 00 c0 1f 50    BRANCHZ.reconverge ^r1, offset:3
9500 03 00 00 20 c0 1f 50    BRANCHZ.reconverge r0.h0, offset:3
9600 03 00 00 40 c0 1f 50    BRANCHZ.reconverge r0.h1, offset:3
9700 03 00 00 00 c0 1f 50    BRANCHZ.reconverge r0, offset:3
98c0 00 00 00 00 c0 10 01    IADD_IMM.i32 r0, 0x0, #0x0
99c0 01 00 00 00 c4 10 51    IADD_IMM.i32.reconverge r4, 0x0, #0x1
10080 00 27 20 00 c2 a3 01    SHADDX.u64 r2, u0, r0.w0, shift:0x2
10140 c9 00 10 00 c0 a0 00    IADD.u32 r0, ^r0, 0x7060504.b0
10200 82 c0 80 03 c1 f0 00    ICMP_OR.u32.ne.m1 r1, r0, u2, 0x0
10304 00 00 00 00 c5 91 00    MOV.i32 r5, r4
10404 00 00 00 00 c6 91 00    MOV.i32 r6, r4
10504 00 00 00 00 c7 91 08    MOV.i32.wait0 r7, r4
10642 00 00 38 08 44 61 00    STORE.i128.slot0 @r4:r5:r6:r7, ^r2, offset:0
10741 f8 ff ff 07 c0 1f 50    BRANCHZ.reconverge ^r1, offset:-8
1087d c0 00 08 10 bc a1 00    IADD.v2u16 r60.h1, ^r61.h10, 0x0
10944 00 46 32 28 40 71 78    ST_CVT.slot0.istream.v4.f32.end @r0:r1:r2:r3, ^r4, ^r6, offset:0x0
11044 00 46 34 28 40 71 78    ST_CVT.slot0.istream.v4.s32.end @r0:r1:r2:r3, ^r4, ^r6, offset:0x0
11144 00 46 36 28 40 71 78    ST_CVT.slot0.istream.v4.u32.end @r0:r1:r2:r3, ^r4, ^r6, offset:0x0
1127c c0 12 00 26 84 67 00    LEA_TEX_IMM.slot0 @r4:r5:r6, ^r60, 0x0, table:0x2, index:0x1
1137c c0 02 00 26 84 67 00    LEA_TEX_IMM.slot0 @r4:r5:r6, ^r60, 0x0, table:0x2, index:0x0
11482 81 00 28 f4 82 6a 00    LD_BUFFER.i64.unsigned.slot0 @r2:r3, u2, u1
11580 81 00 68 f4 80 6a 00    LD_BUFFER.i64.unsigned.slot1 @r0:r1, u0, u1
11684 81 00 a8 f4 a6 6a 00    LD_BUFFER.i64.unsigned.slot2 @r38:r39, u4, u1
11783 81 00 a8 f4 a4 6a 00    LD_BUFFER.i64.unsigned.slot2 @r36:r37, u3, u1
11883 84 00 28 f4 82 6a 00    LD_BUFFER.i64.unsigned.slot0 @r2:r3, u3, u4
11941 82 00 30 e6 82 6a 00    LD_BUFFER.i96.unsigned.slot0 @r2:r3:r4, ^r1, u2
12040 83 00 30 e6 86 6a 08    LD_BUFFER.i96.unsigned.slot0.wait0 @r6:r7:r8, ^r0, u3
12140 00 00 00 c0 c0 9c 40    FRCP.f32.wait0126 r0, ^r0.neg.abs
12240 44 80 00 00 c0 b8 00    MUX.i32.neg r0, ^r0, ^r4, u0
12340 44 80 00 01 c0 b8 00    MUX.i32 r0, ^r0, ^r4, u0
12440 44 80 00 02 c0 b8 00    MUX.i32.fp_zero r0, ^r0, ^r4, u0
12540 44 80 00 03 c0 b8 00    MUX.i32.bit r0, ^r0, ^r4, u0
12600 00 00 01 00 c1 99 68    FREXPM.f32.sqrt.discard r1, r0
12701 00 02 00 00 c2 9c 00    FRSQ.f32 r2, r1
12840 00 02 01 00 c0 99 00    FREXPE.f32.sqrt r0, ^r0
12941 42 c0 40 04 c0 62 41    FMA_RSCALE_LEFT.f32.wait0126 r0, ^r1, ^r2, 0x0.neg, ^r0
13042 43 84 85 00 c1 50 01    CSEL.u32.eq r1, ^r2, ^r3, u4, u5
13142 43 84 85 04 c1 50 01    CSEL.u32.lt r1, ^r2, ^r3, u4, u5
13242 43 84 85 04 c1 58 01    CSEL.s32.lt r1, ^r2, ^r3, u4, u5
1333d 00 00 12 b4 82 56 08    LD_VAR_SPECIAL.v2.f32.sample.clobber.slot0.wait0 @r2:r3, r61, index:0x0
1343d 00 00 33 14 82 5d 08    LD_VAR_BUF_IMM.f16.slot0.v4.src_f16.center.retrieve.wait0 @r2:r3, r61, index:0x0
1353d 00 00 33 84 80 5d 08    LD_VAR_BUF_IMM.f16.slot0.v4.src_f16.sample.store.wait0 @r0:r1, r61, index:0x0
1363d 00 08 33 44 80 5d 08    LD_VAR_BUF_IMM.f16.slot0.v4.src_f16.centroid.store.wait0 @r0:r1, r61, index:0x8
1377c 7d 11 33 04 80 66 00    LD_ATTR_IMM.v4.f16.slot0 @r0:r1, ^r60, ^r61, index:0x1, table:0x1
13840 3c 03 23 04 84 78 00    LD_TILE.v3.f16.slot0 @r4:r5, ^r0, r60, r3
13900 c9 00 20 10 81 a1 00    IADD.v2u16 r1.h1, r0.h10, 0x7060504.b11
14040 c0 00 08 10 41 a1 00    IADD.v2u16 r1.h0, ^r0.h10, 0x0
14102 02 00 04 20 42 a1 00    IADD.v2u16 r2.h0, r2, r2.h10
14242 c0 05 00 00 c2 a1 00    MKVEC.v2i16 r2, ^r2.h00, 0x0.h00
14377 c0 05 00 00 c2 a1 00    MKVEC.v2i16 r2, ^r55.h00, 0x0.h00
14477 c0 05 10 00 c2 a1 00    MKVEC.v2i16 r2, ^r55.h10, 0x0.h00
145c0 77 05 00 00 c2 a1 00    MKVEC.v2i16 r2, 0x0.h00, ^r55.h00
146c0 77 05 04 00 c2 a1 00    MKVEC.v2i16 r2, 0x0.h00, ^r55.h10
14777 00 14 00 00 c2 90 00    U16_TO_U32 r2, ^r55.h00
14877 00 14 10 00 c2 90 00    U16_TO_U32 r2, ^r55.h10
14977 00 15 00 00 c2 90 00    U16_TO_F32 r2, ^r55.h00
15077 00 15 10 00 c2 90 00    U16_TO_F32 r2, ^r55.h10
15177 00 04 00 00 c2 90 00    S16_TO_S32 r2, ^r55.h00
15277 00 04 10 00 c2 90 00    S16_TO_S32 r2, ^r55.h10
153c0 77 01 08 00 c2 a8 00    ISUB.s32 r2, 0x0, ^r55.h0
154c0 77 01 0c 00 c2 a8 00    ISUB.s32 r2, 0x0, ^r55.h1
15500 c0 c0 00 c0 c7 bd 00    MKVEC.v2i8 r7, r0.b3, 0x0.b0, 0x0
15600 c0 c0 00 80 c6 bd 00    MKVEC.v2i8 r6, r0.b2, 0x0.b0, 0x0
15700 c0 c0 00 00 c4 bd 00    MKVEC.v2i8 r4, r0.b0, 0x0.b0, 0x0
15840 c0 c0 00 40 c5 bd 00    MKVEC.v2i8 r5, ^r0.b1, 0x0.b0, 0x0
15900 00 11 30 00 c7 90 00    U8_TO_F32 r7, r0.b3
16000 00 11 20 00 c6 90 00    U8_TO_F32 r6, r0.b2
16100 00 11 00 00 c4 90 00    U8_TO_F32 r4, r0.b0
16240 00 11 10 00 c5 90 00    U8_TO_F32 r5, ^r0.b1
16300 00 01 30 00 c7 90 00    S8_TO_F32 r7, r0.b3
16400 00 01 20 00 c6 90 00    S8_TO_F32 r6, r0.b2
16500 00 01 00 00 c4 90 00    S8_TO_F32 r4, r0.b0
16640 00 01 10 00 c5 90 00    S8_TO_F32 r5, ^r0.b1
16742 00 07 00 20 c2 90 00    V2S16_TO_V2F16 r2, ^r2
16842 00 07 00 10 c2 90 00    V2S16_TO_V2F16 r2, ^r2.h10
16942 00 07 00 00 c2 90 00    V2S16_TO_V2F16 r2, ^r2.h00
1707d 00 07 00 00 c2 90 00    V2S16_TO_V2F16 r2, ^r61.h00
17177 00 07 00 00 c2 90 00    V2S16_TO_V2F16 r2, ^r55.h00
17277 00 07 00 30 c2 90 00    V2S16_TO_V2F16 r2, ^r55.h11
17377 00 07 00 20 c2 90 00    V2S16_TO_V2F16 r2, ^r55
17477 00 07 00 10 c2 90 00    V2S16_TO_V2F16 r2, ^r55.h10
17542 00 07 00 c0 c2 90 00    V2S16_TO_V2F16 r2, ^r2.b01
17642 00 03 00 40 c2 90 00    V2S8_TO_V2F16 r2, ^r2.b01
17742 00 03 00 00 c2 90 00    V2S8_TO_V2F16 r2, ^r2.b00
17800 00 03 00 40 c2 90 00    V2S8_TO_V2F16 r2, r0.b01
17940 00 03 00 e0 c3 90 00    V2S8_TO_V2F16 r3, ^r0.b23
18000 00 03 00 20 c1 90 00    V2S8_TO_V2F16 r1, r0.b20
18140 00 03 00 60 c0 90 00    V2S8_TO_V2F16 r0, ^r0.b21
182
1833d 00 00 b2 88 80 5c 68    LD_VAR_BUF_IMM.f32.slot2.v4.src_f32.sample.store.discard @r0:r1:r2:r3, r61, index:0x0
1843d 00 10 72 18 84 5c 00    LD_VAR_BUF_IMM.f32.slot1.v4.src_f32.center.retrieve @r4:r5:r6:r7, r61, index:0x10
185c0 00 00 00 00 c8 10 01    IADD_IMM.i32 r8, 0x0, #0x0
186c0 00 00 00 00 c9 10 01    IADD_IMM.i32 r9, 0x0, #0x0
1873d 00 14 00 00 ca 90 00    U16_TO_U32 r10, r61.h00
1883d 09 00 00 30 c0 1f 50    BRANCHZ.eq.reconverge r61.h0, offset:9
1890a 00 00 00 00 cb 91 50    MOV.i32.reconverge r11, r10
19000 00 00 00 00 c0 00 48    NOP.wait
19181 0b 80 33 04 8e 78 00    LD_TILE.v4.f16.slot0 @r14:r15, u1, r11, u0
1920b 00 04 00 00 cc 91 00    CLZ.u32 r12, r11
19382 4c c0 52 00 cc b4 00    RSHIFT_XOR.i32.not_result r12, u2, ^r12.b00, 0x0
1944b c0 4c 10 01 cb b4 08    LSHIFT_AND.i32.wait0 r11, ^r11, 0x0.b00, ^r12
1954f 49 00 28 00 c9 a5 00    FADD.v2f16 r9, ^r15, ^r9
1964e 48 00 28 00 c8 a5 00    FADD.v2f16 r8, ^r14, ^r8
1970b f8 ff ff 07 c0 1f 50    BRANCHZ.reconverge r11, offset:-8
1984a 00 0c 00 00 fe 91 00    POPCOUNT.i32 r62, ^r10
1997e 00 19 00 00 fe 90 00    U32_TO_F32 r62, ^r62
2007e 7e 04 00 00 fe a5 00    V2F32_TO_V2F16 r62, ^r62, ^r62
2017e 00 01 00 00 fe 9c 00    FRCP.f16 r62, ^r62.h00
20249 3e c0 22 04 c9 b3 30    FMA.v2f16.wait12 r9, ^r9, r62.h00, 0x0.neg
20347 43 00 00 00 c3 a4 00    FADD.f32 r3, ^r7, ^r3
20443 09 00 08 00 c3 a4 40    FADD.f32.wait0126 r3, ^r3, r9.h1
2053c 03 ea 00 02 bc 7d 68    ATEST.discard @r60, r60, r3, atest_datum.w0
20646 42 00 00 00 c2 a4 00    FADD.f32 r2, ^r6, ^r2
20744 40 00 00 00 c0 a4 00    FADD.f32 r0, ^r4, ^r0
20848 7e c0 22 04 ff b3 00    FMA.v2f16 r63, ^r8, ^r62.h00, 0x0.neg
20945 41 00 00 00 c1 a4 00    FADD.f32 r1, ^r5, ^r1
21041 3f 00 08 00 c1 a4 00    FADD.f32 r1, ^r1, r63.h1
21140 7f 00 04 00 c0 a4 00    FADD.f32 r0, ^r0, ^r63.h0
21242 49 00 04 00 c2 a4 48    FADD.f32.wait r2, ^r2, ^r9.h0
213f0 00 3c 32 08 40 7f 78    BLEND.slot0.v4.f32.end @r0:r1:r2:r3, blend_descriptor_0.w0, r60, target:0x0
214c0 00 00 00 00 f6 10 01    IADD_IMM.i32 r54, 0x0, #0x0
215c0 f1 00 00 10 c1 2f 08    BRANCHZI.eq.absolute.wait0 0x0, blend_descriptor_0.w1
21680 00 c0 17 34 7c 25 01    TEX_FETCH.slot0.f.32.2d @r0:r1:r2:r3, @r60:r61, u0
21780 00 00 00 00 c1 91 02    MOV.i32 r1, u64
21881 00 00 00 00 c1 91 02    MOV.i32 r1, u65
21930 00 f7 1b 02 cc 20 09    ATOM_RETURN.i32.slot0.axchg.wait0 @r55, @r12, r48, offset:0x0
22032 00 80 18 02 4c 68 08    ATOM.i32.slot0.aadd.wait0 @r12, r50, offset:0x0
22132 00 00 18 02 8c 69 08    ATOM1_RETURN.i32.slot0.ainc.wait0 @r12, r50, offset:0x0
22232 00 00 18 00 80 69 08    ATOM1_RETURN.i32.slot0.ainc.wait0 @, r50, offset:0x0
22382 00 80 15 b4 80 38 49    VAR_TEX_SINGLE.slot0.skip.sample_store.f.32.2d.zero.wait @r0:r1:r2:r3, u2, u0
22482 20 80 15 b4 80 38 09    VAR_TEX_SINGLE.slot0.skip.sample_store.f.32.2d.computed.wait0 @r0:r1:r2:r3, u2, u0
22582 20 80 1d 84 80 38 41    VAR_TEX_SINGLE.slot0.skip.sample_store.s.32.2d.computed.wait0126 @r0, u2, u0
22640 c0 c0 80 03 c0 f0 10    ICMP_OR.u32.ne.m1.wait1 r0, ^r0, 0x0, 0x0
22742 43 40 01 01 c0 f8 00    ICMP_AND.s32.gt.i1 r0, ^r2, ^r3, ^r0
22842 c0 c0 c2 03 c0 f0 10    ICMP_MULTI.u32.ne.u1.wait1 r0, ^r2, 0x0, 0x0
22944 46 c0 c2 01 c2 f0 00    ICMP_MULTI.u32.gt.u1 r2, ^r4, ^r6, 0x0
23045 47 42 82 01 c2 f0 00    ICMP_MULTI.u32.gt.m1 r2, ^r5, ^r7, ^r2
23143 c0 40 82 03 c0 f0 00    ICMP_MULTI.u32.ne.m1 r0, ^r3, 0x0, ^r0
23240 42 c0 c2 01 c0 f0 00    ICMP_MULTI.u32.gt.u1 r0, ^r0, ^r2, 0x0
23341 43 40 82 01 c4 f8 00    ICMP_MULTI.s32.gt.m1 r4, ^r1, ^r3, ^r0
23440 c0 c0 a8 03 c0 f5 10    FCMP_OR.v2f16.ne.m1.wait1 r0, ^r0, 0x0, 0x0
23541 41 40 ad 01 c0 f5 00    FCMP_AND.v2f16.gt.m1 r0, ^r1, ^r1.h11, ^r0
23640 c0 c0 a8 03 c0 f5 10    FCMP_OR.v2f16.ne.m1.wait1 r0, ^r0, 0x0, 0x0
23741 41 40 ad 01 c0 f5 00    FCMP_AND.v2f16.gt.m1 r0, ^r1, ^r1.h11, ^r0
238c4 c0 40 10 71 c0 b6 00    LSHIFT_AND.v4i8 r0, 0x1000000.b3333, 0x0.b00, ^r0
23940 00 13 00 80 c0 90 00    V2U8_TO_V2F16 r0, ^r0.b02
24041 40 00 40 00 c0 aa 00    IADD.v4s8.saturate r0, ^r1, ^r0
24141 40 01 40 00 c0 aa 00    ISUB.v4s8.saturate r0, ^r1, ^r0
24241 40 0b 40 00 c0 aa 00    HADD.v4s8.rhadd r0, ^r1, ^r0
24301 00 c0 80 01 c2 fa 00    ICMP_OR.v4s8.gt.m1 r2, r1, r0, 0x0
24440 41 42 00 01 c0 ba 00    MUX.v4i8 r0, ^r0, ^r1, ^r2
245c0 c0 00 00 04 82 6b 00    LEA_BUFFER.slot0 @r2:r3, 0x0, 0x0
246