1<!-- 2 Copyright (C) 2024 Collabora Ltd. 3 4 Permission is hereby granted, free of charge, to any person obtaining a 5 copy of this software and associated documentation files (the "Software"), 6 to deal in the Software without restriction, including without limitation 7 the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 and/or sell copies of the Software, and to permit persons to whom the 9 Software is furnished to do so, subject to the following conditions: 10 11 The above copyright notice and this permission notice (including the next 12 paragraph) shall be included in all copies or substantial portions of the 13 Software. 14 15 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 SOFTWARE. 22--> 23 24<bifrost> 25 26 <!-- Pseudo instruction representing dual texturing on Bifrost. Lowered to 27 TEXC after register allocation, when the second destination register can 28 be combined with the texture operation descriptor. --> 29 <ins name="TEXC_DUAL" staging="rw=sr_count" pseudo="true" message="tex" dests="2" unit="add"> 30 <src start="0"/> 31 <src start="3"/> 32 <src start="6" mask="0xf7"/> 33 <mod name="skip" start="9" size="1" opt="skip"/> 34 <immediate name="sr_count" size="4" pseudo="true"/> 35 <immediate name="sr_count_2" size="4" pseudo="true"/> 36 <mod name="lod_mode" start="13" size="1" default="zero_lod" pseudo="true"> 37 <opt>computed_lod</opt> 38 <opt>zero_lod</opt> 39 </mod> 40 </ins> 41 42 <!--- Lowered to *SEG_ADD/+SEG_ADD --> 43 <ins name="SEG_ADD.i64" pseudo="true" unit="add"> 44 <src start="0"/> 45 <src start="3"/> 46 <mod name="seg" size="3"> 47 <reserved/> 48 <reserved/> 49 <opt>wls</opt> 50 <reserved/> 51 <reserved/> 52 <reserved/> 53 <reserved/> 54 <opt>tl</opt> 55 </mod> 56 <mod name="preserve_null" size="1" opt="preserve_null"/> 57 </ins> 58 59 <!-- Scheduler lowered to *ATOM_C.i32/+ATOM_CX. Real Valhall instructions. --> 60 <ins name="ATOM_RETURN.i32" pseudo="true" staging="rw=sr_count" message="atomic" unit="add"> 61 <src start="0"/> 62 <src start="3"/> 63 <mod name="atom_opc" start="9" size="5"> 64 <reserved/> 65 <reserved/> 66 <opt>aadd</opt> 67 <reserved/> 68 <reserved/> 69 <reserved/> 70 <reserved/> 71 <reserved/> 72 <opt>asmin</opt> 73 <opt>asmax</opt> 74 <opt>aumin</opt> 75 <opt>aumax</opt> 76 <opt>aand</opt> 77 <opt>aor</opt> 78 <opt>axor</opt> 79 <opt>axchg</opt> <!-- For Valhall --> 80 <opt>acmpxchg</opt> <!-- For Valhall --> 81 </mod> 82 <!-- not actually encoded, but used for IR --> 83 <immediate name="sr_count" size="4" pseudo="true"/> 84 </ins> 85 86 <ins name="ATOM1_RETURN.i32" pseudo="true" staging="w=sr_count" message="atomic" unit="add"> 87 <src start="0"/> 88 <src start="3"/> 89 <mod name="atom_opc" start="6" size="3"> 90 <opt>ainc</opt> 91 <opt>adec</opt> 92 <opt>aumax1</opt> 93 <opt>asmax1</opt> 94 <opt>aor1</opt> 95 </mod> 96 <!-- not actually encoded, but used for IR --> 97 <immediate name="sr_count" size="4" pseudo="true"/> 98 </ins> 99 100 <ins name="ATOM.i32" pseudo="true" staging="r=sr_count" message="atomic" unit="add"> 101 <src start="0"/> 102 <src start="3"/> 103 <mod name="atom_opc" start="9" size="4"> 104 <reserved/> 105 <reserved/> 106 <opt>aadd</opt> 107 <reserved/> 108 <reserved/> 109 <reserved/> 110 <reserved/> 111 <reserved/> 112 <opt>asmin</opt> 113 <opt>asmax</opt> 114 <opt>aumin</opt> 115 <opt>aumax</opt> 116 <opt>aand</opt> 117 <opt>aor</opt> 118 <opt>axor</opt> 119 </mod> 120 <!-- not actually encoded, but used for IR --> 121 <immediate name="sr_count" size="4" pseudo="true"/> 122 </ins> 123 124 <!-- *CUBEFACE1/+CUBEFACE2 pair, two destinations, scheduler lowered --> 125 <ins name="CUBEFACE" pseudo="true" dests="2" unit="add"> 126 <src start="0"/> 127 <src start="3"/> 128 <src start="6"/> 129 <mod name="neg0" size="1" opt="neg"/> 130 <mod name="neg1" size="1" opt="neg"/> 131 <mod name="neg2" size="1" opt="neg"/> 132 </ins> 133 134 <ins name="FABSNEG.f32" pseudo="true" unit="fma"> 135 <src start="0" mask="0xfb"/> 136 <mod name="neg0" start="7" size="1" opt="neg"/> 137 <mod name="abs0" start="12" size="1" opt="abs"/> 138 <mod name="widen0" size="2"> 139 <opt>none</opt> 140 <opt>h0</opt> 141 <opt>h1</opt> 142 </mod> 143 </ins> 144 145 <ins name="FABSNEG.v2f16" pseudo="true" unit="fma"> 146 <src start="0" mask="0xfb"/> 147 <mod name="abs0" size="1" opt="abs"/> 148 <mod name="neg0" start="7" size="1" opt="neg"/> 149 <mod name="swz0" start="9" size="2" default="h01"> 150 <opt>h00</opt> 151 <opt>h10</opt> 152 <opt>h01</opt> 153 <opt>h11</opt> 154 </mod> 155 </ins> 156 157 <ins name="FCLAMP.f32" pseudo="true" unit="fma"> 158 <src start="0" mask="0xfb"/> 159 <mod name="clamp" start="15" size="2"> 160 <opt>none</opt> 161 <opt>clamp_0_inf</opt> 162 <opt>clamp_m1_1</opt> 163 <opt>clamp_0_1</opt> 164 </mod> 165 </ins> 166 167 <ins name="FCLAMP.v2f16" pseudo="true" unit="fma"> 168 <src start="0" mask="0xfb"/> 169 <mod name="clamp" start="15" size="2"> 170 <opt>none</opt> 171 <opt>clamp_0_inf</opt> 172 <opt>clamp_m1_1</opt> 173 <opt>clamp_0_1</opt> 174 </mod> 175 </ins> 176 177 <ins name="DISCARD.b32" pseudo="true" dests="0" unit="add"> 178 <src start="0"/> 179 <mod name="widen0" size="2"> 180 <opt>none</opt> 181 <opt>h0</opt> 182 <opt>h1</opt> 183 </mod> 184 </ins> 185 186 <ins name="PHI" pseudo="true" variable_srcs="true" unit="add"/> 187 188 <ins name="COLLECT.i32" pseudo="true" variable_srcs="true" unit="add"/> 189 190 <ins name="SPLIT.i32" pseudo="true" variable_dests="true" unit="add"> 191 <src start="0"/> 192 </ins> 193 194 195</bifrost> 196