1 /*
2 * Copyright © 2022 Collabora Ltd. and Red Hat Inc.
3 * SPDX-License-Identifier: MIT
4 */
5 #include "nvk_cmd_buffer.h"
6
7 #include "nvk_buffer.h"
8 #include "nvk_device.h"
9 #include "nvk_device_memory.h"
10 #include "nvk_entrypoints.h"
11 #include "nvk_format.h"
12 #include "nvk_image.h"
13 #include "nvk_image_view.h"
14 #include "nvk_physical_device.h"
15
16 #include "vk_format.h"
17
18 #include "nvtypes.h"
19 #include "nv_push_cl902d.h"
20 #include "nv_push_cl90b5.h"
21 #include "nv_push_clc1b5.h"
22
23 static inline uint16_t
nvk_cmd_buffer_copy_cls(struct nvk_cmd_buffer * cmd)24 nvk_cmd_buffer_copy_cls(struct nvk_cmd_buffer *cmd)
25 {
26 struct nvk_device *dev = nvk_cmd_buffer_device(cmd);
27 struct nvk_physical_device *pdev = nvk_device_physical(dev);
28 return pdev->info.cls_copy;
29 }
30
31 struct nouveau_copy_buffer {
32 uint64_t base_addr;
33 VkImageType image_type;
34 struct nil_Offset4D_Elements offset_el;
35 struct nil_Extent4D_Elements extent_el;
36 uint32_t bpp;
37 uint32_t row_stride;
38 uint32_t array_stride;
39 struct nil_tiling tiling;
40 };
41
42 struct nouveau_copy {
43 struct nouveau_copy_buffer src;
44 struct nouveau_copy_buffer dst;
45 struct nouveau_copy_remap {
46 uint8_t comp_size;
47 uint8_t dst[4];
48 } remap;
49 struct nil_Extent4D_Elements extent_el;
50 };
51
52 static struct nouveau_copy_buffer
nouveau_copy_rect_buffer(struct nvk_buffer * buf,VkDeviceSize offset,struct vk_image_buffer_layout buffer_layout)53 nouveau_copy_rect_buffer(struct nvk_buffer *buf,
54 VkDeviceSize offset,
55 struct vk_image_buffer_layout buffer_layout)
56 {
57 return (struct nouveau_copy_buffer) {
58 .base_addr = nvk_buffer_address(buf, offset),
59 .image_type = VK_IMAGE_TYPE_2D,
60 .bpp = buffer_layout.element_size_B,
61 .row_stride = buffer_layout.row_stride_B,
62 .array_stride = buffer_layout.image_stride_B,
63 };
64 }
65
66 static struct nil_Offset4D_Pixels
vk_to_nil_offset(VkOffset3D offset,uint32_t base_array_layer)67 vk_to_nil_offset(VkOffset3D offset, uint32_t base_array_layer)
68 {
69 return (struct nil_Offset4D_Pixels) {
70 .x = offset.x,
71 .y = offset.y,
72 .z = offset.z,
73 .a = base_array_layer
74 };
75 }
76
77 static struct nil_Extent4D_Pixels
vk_to_nil_extent(VkExtent3D extent,uint32_t array_layers)78 vk_to_nil_extent(VkExtent3D extent, uint32_t array_layers)
79 {
80 return (struct nil_Extent4D_Pixels) {
81 .width = extent.width,
82 .height = extent.height,
83 .depth = extent.depth,
84 .array_len = array_layers,
85 };
86 }
87
88 static struct nouveau_copy_buffer
nouveau_copy_rect_image(const struct nvk_image * img,const struct nvk_image_plane * plane,VkOffset3D offset_px,const VkImageSubresourceLayers * sub_res)89 nouveau_copy_rect_image(const struct nvk_image *img,
90 const struct nvk_image_plane *plane,
91 VkOffset3D offset_px,
92 const VkImageSubresourceLayers *sub_res)
93 {
94 const struct nil_Extent4D_Pixels lvl_extent4d_px =
95 nil_image_level_extent_px(&plane->nil, sub_res->mipLevel);
96
97 offset_px = vk_image_sanitize_offset(&img->vk, offset_px);
98 const struct nil_Offset4D_Pixels offset4d_px =
99 vk_to_nil_offset(offset_px, sub_res->baseArrayLayer);
100
101 struct nouveau_copy_buffer buf = {
102 .base_addr = nvk_image_plane_base_address(plane) +
103 plane->nil.levels[sub_res->mipLevel].offset_B,
104 .image_type = img->vk.image_type,
105 .offset_el = nil_offset4d_px_to_el(offset4d_px, plane->nil.format,
106 plane->nil.sample_layout),
107 .extent_el = nil_extent4d_px_to_el(lvl_extent4d_px, plane->nil.format,
108 plane->nil.sample_layout),
109 .bpp = util_format_get_blocksize(plane->nil.format.p_format),
110 .row_stride = plane->nil.levels[sub_res->mipLevel].row_stride_B,
111 .array_stride = plane->nil.array_stride_B,
112 .tiling = plane->nil.levels[sub_res->mipLevel].tiling,
113 };
114
115 return buf;
116 }
117
118 static struct nouveau_copy_remap
nouveau_copy_remap_format(VkFormat format)119 nouveau_copy_remap_format(VkFormat format)
120 {
121 /* Pick an arbitrary component size. It doesn't matter what size we
122 * pick since we're just doing a copy, as long as it's no more than 4B
123 * and divides the format size.
124 */
125 unsigned comp_size = vk_format_get_blocksize(format);
126 if (comp_size % 3 == 0) {
127 comp_size /= 3;
128 assert(util_is_power_of_two_nonzero(comp_size) && comp_size <= 4);
129 } else {
130 assert(util_is_power_of_two_nonzero(comp_size) && comp_size <= 16);
131 comp_size = MIN2(comp_size, 4);
132 }
133
134 return (struct nouveau_copy_remap) {
135 .comp_size = comp_size,
136 .dst = { 0, 1, 2, 3 },
137 };
138 }
139
140 static uint32_t
to_90b5_remap_comp_size(uint8_t comp_size)141 to_90b5_remap_comp_size(uint8_t comp_size)
142 {
143 static const uint8_t to_90b5[] = {
144 [1] = NV90B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_ONE,
145 [2] = NV90B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_TWO,
146 [3] = NV90B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_THREE,
147 [4] = NV90B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_FOUR,
148 };
149 assert(comp_size > 0 && comp_size < ARRAY_SIZE(to_90b5));
150
151 uint32_t size_90b5 = comp_size - 1;
152 assert(size_90b5 == to_90b5[comp_size]);
153 return size_90b5;
154 }
155
156 static uint32_t
to_90b5_remap_num_comps(uint8_t num_comps)157 to_90b5_remap_num_comps(uint8_t num_comps)
158 {
159 static const uint8_t to_90b5[] = {
160 [1] = NV90B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_ONE,
161 [2] = NV90B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_TWO,
162 [3] = NV90B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_THREE,
163 [4] = NV90B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_FOUR,
164 };
165 assert(num_comps > 0 && num_comps < ARRAY_SIZE(to_90b5));
166
167 uint32_t num_comps_90b5 = num_comps - 1;
168 assert(num_comps_90b5 == to_90b5[num_comps]);
169 return num_comps_90b5;
170 }
171
172 static void
nouveau_copy_rect(struct nvk_cmd_buffer * cmd,struct nouveau_copy * copy)173 nouveau_copy_rect(struct nvk_cmd_buffer *cmd, struct nouveau_copy *copy)
174 {
175 uint32_t src_bw, dst_bw;
176 if (copy->remap.comp_size > 0) {
177 struct nv_push *p = nvk_cmd_buffer_push(cmd, 2);
178
179 assert(copy->src.bpp % copy->remap.comp_size == 0);
180 assert(copy->dst.bpp % copy->remap.comp_size == 0);
181 uint32_t num_src_comps = copy->src.bpp / copy->remap.comp_size;
182 uint32_t num_dst_comps = copy->dst.bpp / copy->remap.comp_size;
183
184 /* When running with component remapping enabled, most X/Y dimensions
185 * are in units of blocks.
186 */
187 src_bw = dst_bw = 1;
188
189 P_IMMD(p, NV90B5, SET_REMAP_COMPONENTS, {
190 .dst_x = copy->remap.dst[0],
191 .dst_y = copy->remap.dst[1],
192 .dst_z = copy->remap.dst[2],
193 .dst_w = copy->remap.dst[3],
194 .component_size = to_90b5_remap_comp_size(copy->remap.comp_size),
195 .num_src_components = to_90b5_remap_comp_size(num_src_comps),
196 .num_dst_components = to_90b5_remap_comp_size(num_dst_comps),
197 });
198 } else {
199 /* When component remapping is disabled, dimensions are in units of
200 * bytes (an implicit block widht of 1B).
201 */
202 assert(copy->src.bpp == copy->dst.bpp);
203 src_bw = copy->src.bpp;
204 dst_bw = copy->dst.bpp;
205 }
206
207 assert(copy->extent_el.depth == 1 || copy->extent_el.array_len == 1);
208 uint32_t layers = MAX2(copy->extent_el.depth, copy->extent_el.array_len);
209 for (unsigned z = 0; z < layers; z++) {
210 VkDeviceSize src_addr = copy->src.base_addr;
211 VkDeviceSize dst_addr = copy->dst.base_addr;
212
213 if (copy->src.image_type != VK_IMAGE_TYPE_3D)
214 src_addr += (z + copy->src.offset_el.a) * copy->src.array_stride;
215
216 if (copy->dst.image_type != VK_IMAGE_TYPE_3D)
217 dst_addr += (z + copy->dst.offset_el.a) * copy->dst.array_stride;
218
219 if (!copy->src.tiling.is_tiled) {
220 src_addr += copy->src.offset_el.x * copy->src.bpp +
221 copy->src.offset_el.y * copy->src.row_stride;
222 }
223
224 if (!copy->dst.tiling.is_tiled) {
225 dst_addr += copy->dst.offset_el.x * copy->dst.bpp +
226 copy->dst.offset_el.y * copy->dst.row_stride;
227 }
228
229 struct nv_push *p = nvk_cmd_buffer_push(cmd, 31);
230
231 P_MTHD(p, NV90B5, OFFSET_IN_UPPER);
232 P_NV90B5_OFFSET_IN_UPPER(p, src_addr >> 32);
233 P_NV90B5_OFFSET_IN_LOWER(p, src_addr & 0xffffffff);
234 P_NV90B5_OFFSET_OUT_UPPER(p, dst_addr >> 32);
235 P_NV90B5_OFFSET_OUT_LOWER(p, dst_addr & 0xffffffff);
236 P_NV90B5_PITCH_IN(p, copy->src.row_stride);
237 P_NV90B5_PITCH_OUT(p, copy->dst.row_stride);
238 P_NV90B5_LINE_LENGTH_IN(p, copy->extent_el.width * src_bw);
239 P_NV90B5_LINE_COUNT(p, copy->extent_el.height);
240
241 uint32_t src_layout = 0, dst_layout = 0;
242 if (copy->src.tiling.is_tiled) {
243 P_MTHD(p, NV90B5, SET_SRC_BLOCK_SIZE);
244 P_NV90B5_SET_SRC_BLOCK_SIZE(p, {
245 .width = 0, /* Tiles are always 1 GOB wide */
246 .height = copy->src.tiling.y_log2,
247 .depth = copy->src.tiling.z_log2,
248 .gob_height = copy->src.tiling.gob_height_is_8 ?
249 GOB_HEIGHT_GOB_HEIGHT_FERMI_8 :
250 GOB_HEIGHT_GOB_HEIGHT_TESLA_4,
251 });
252 /* We use the stride for copies because the copy hardware has no
253 * concept of a tile width. Instead, we just set the width to the
254 * stride divided by bpp.
255 */
256 uint32_t src_stride_el = copy->src.row_stride / copy->src.bpp;
257 P_NV90B5_SET_SRC_WIDTH(p, src_stride_el * src_bw);
258 P_NV90B5_SET_SRC_HEIGHT(p, copy->src.extent_el.height);
259 P_NV90B5_SET_SRC_DEPTH(p, copy->src.extent_el.depth);
260 if (copy->src.image_type == VK_IMAGE_TYPE_3D)
261 P_NV90B5_SET_SRC_LAYER(p, z + copy->src.offset_el.z);
262 else
263 P_NV90B5_SET_SRC_LAYER(p, 0);
264
265 if (nvk_cmd_buffer_copy_cls(cmd) >= PASCAL_DMA_COPY_B) {
266 P_MTHD(p, NVC1B5, SRC_ORIGIN_X);
267 P_NVC1B5_SRC_ORIGIN_X(p, copy->src.offset_el.x * src_bw);
268 P_NVC1B5_SRC_ORIGIN_Y(p, copy->src.offset_el.y);
269 } else {
270 P_MTHD(p, NV90B5, SET_SRC_ORIGIN);
271 P_NV90B5_SET_SRC_ORIGIN(p, {
272 .x = copy->src.offset_el.x * src_bw,
273 .y = copy->src.offset_el.y
274 });
275 }
276
277 src_layout = NV90B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT_BLOCKLINEAR;
278 } else {
279 src_addr += copy->src.array_stride;
280 src_layout = NV90B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT_PITCH;
281 }
282
283 if (copy->dst.tiling.is_tiled) {
284 P_MTHD(p, NV90B5, SET_DST_BLOCK_SIZE);
285 P_NV90B5_SET_DST_BLOCK_SIZE(p, {
286 .width = 0, /* Tiles are always 1 GOB wide */
287 .height = copy->dst.tiling.y_log2,
288 .depth = copy->dst.tiling.z_log2,
289 .gob_height = copy->dst.tiling.gob_height_is_8 ?
290 GOB_HEIGHT_GOB_HEIGHT_FERMI_8 :
291 GOB_HEIGHT_GOB_HEIGHT_TESLA_4,
292 });
293 /* We use the stride for copies because the copy hardware has no
294 * concept of a tile width. Instead, we just set the width to the
295 * stride divided by bpp.
296 */
297 uint32_t dst_stride_el = copy->dst.row_stride / copy->dst.bpp;
298 P_NV90B5_SET_DST_WIDTH(p, dst_stride_el * dst_bw);
299 P_NV90B5_SET_DST_HEIGHT(p, copy->dst.extent_el.height);
300 P_NV90B5_SET_DST_DEPTH(p, copy->dst.extent_el.depth);
301 if (copy->dst.image_type == VK_IMAGE_TYPE_3D)
302 P_NV90B5_SET_DST_LAYER(p, z + copy->dst.offset_el.z);
303 else
304 P_NV90B5_SET_DST_LAYER(p, 0);
305
306 if (nvk_cmd_buffer_copy_cls(cmd) >= PASCAL_DMA_COPY_B) {
307 P_MTHD(p, NVC1B5, DST_ORIGIN_X);
308 P_NVC1B5_DST_ORIGIN_X(p, copy->dst.offset_el.x * dst_bw);
309 P_NVC1B5_DST_ORIGIN_Y(p, copy->dst.offset_el.y);
310 } else {
311 P_MTHD(p, NV90B5, SET_DST_ORIGIN);
312 P_NV90B5_SET_DST_ORIGIN(p, {
313 .x = copy->dst.offset_el.x * dst_bw,
314 .y = copy->dst.offset_el.y
315 });
316 }
317
318 dst_layout = NV90B5_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR;
319 } else {
320 dst_addr += copy->dst.array_stride;
321 dst_layout = NV90B5_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH;
322 }
323
324 P_IMMD(p, NV90B5, LAUNCH_DMA, {
325 .data_transfer_type = DATA_TRANSFER_TYPE_NON_PIPELINED,
326 .multi_line_enable = MULTI_LINE_ENABLE_TRUE,
327 .flush_enable = FLUSH_ENABLE_TRUE,
328 .src_memory_layout = src_layout,
329 .dst_memory_layout = dst_layout,
330 .remap_enable = copy->remap.comp_size > 0,
331 });
332 }
333 }
334
335 VKAPI_ATTR void VKAPI_CALL
nvk_CmdCopyBuffer2(VkCommandBuffer commandBuffer,const VkCopyBufferInfo2 * pCopyBufferInfo)336 nvk_CmdCopyBuffer2(VkCommandBuffer commandBuffer,
337 const VkCopyBufferInfo2 *pCopyBufferInfo)
338 {
339 VK_FROM_HANDLE(nvk_cmd_buffer, cmd, commandBuffer);
340 VK_FROM_HANDLE(nvk_buffer, src, pCopyBufferInfo->srcBuffer);
341 VK_FROM_HANDLE(nvk_buffer, dst, pCopyBufferInfo->dstBuffer);
342
343 for (unsigned r = 0; r < pCopyBufferInfo->regionCount; r++) {
344 const VkBufferCopy2 *region = &pCopyBufferInfo->pRegions[r];
345
346 uint64_t src_addr = nvk_buffer_address(src, region->srcOffset);
347 uint64_t dst_addr = nvk_buffer_address(dst, region->dstOffset);
348 uint64_t size = region->size;
349
350 while (size) {
351 struct nv_push *p = nvk_cmd_buffer_push(cmd, 10);
352
353 P_MTHD(p, NV90B5, OFFSET_IN_UPPER);
354 P_NV90B5_OFFSET_IN_UPPER(p, src_addr >> 32);
355 P_NV90B5_OFFSET_IN_LOWER(p, src_addr & 0xffffffff);
356 P_NV90B5_OFFSET_OUT_UPPER(p, dst_addr >> 32);
357 P_NV90B5_OFFSET_OUT_LOWER(p, dst_addr & 0xffffffff);
358
359 unsigned bytes = MIN2(size, 1 << 17);
360
361 P_MTHD(p, NV90B5, LINE_LENGTH_IN);
362 P_NV90B5_LINE_LENGTH_IN(p, bytes);
363 P_NV90B5_LINE_COUNT(p, 1);
364
365 P_IMMD(p, NV90B5, LAUNCH_DMA, {
366 .data_transfer_type = DATA_TRANSFER_TYPE_NON_PIPELINED,
367 .multi_line_enable = MULTI_LINE_ENABLE_TRUE,
368 .flush_enable = FLUSH_ENABLE_TRUE,
369 .src_memory_layout = SRC_MEMORY_LAYOUT_PITCH,
370 .dst_memory_layout = DST_MEMORY_LAYOUT_PITCH,
371 });
372
373 src_addr += bytes;
374 dst_addr += bytes;
375 size -= bytes;
376 }
377 }
378 }
379
380 VKAPI_ATTR void VKAPI_CALL
nvk_CmdCopyBufferToImage2(VkCommandBuffer commandBuffer,const VkCopyBufferToImageInfo2 * pCopyBufferToImageInfo)381 nvk_CmdCopyBufferToImage2(VkCommandBuffer commandBuffer,
382 const VkCopyBufferToImageInfo2 *pCopyBufferToImageInfo)
383 {
384 VK_FROM_HANDLE(nvk_cmd_buffer, cmd, commandBuffer);
385 VK_FROM_HANDLE(nvk_buffer, src, pCopyBufferToImageInfo->srcBuffer);
386 VK_FROM_HANDLE(nvk_image, dst, pCopyBufferToImageInfo->dstImage);
387
388 for (unsigned r = 0; r < pCopyBufferToImageInfo->regionCount; r++) {
389 const VkBufferImageCopy2 *region = &pCopyBufferToImageInfo->pRegions[r];
390 struct vk_image_buffer_layout buffer_layout =
391 vk_image_buffer_copy_layout(&dst->vk, region);
392
393 const VkExtent3D extent_px =
394 vk_image_sanitize_extent(&dst->vk, region->imageExtent);
395 const uint32_t layer_count =
396 vk_image_subresource_layer_count(&dst->vk, ®ion->imageSubresource);
397 const struct nil_Extent4D_Pixels extent4d_px =
398 vk_to_nil_extent(extent_px, layer_count);
399
400 const VkImageAspectFlagBits aspects = region->imageSubresource.aspectMask;
401 uint8_t plane = nvk_image_aspects_to_plane(dst, aspects);
402
403 struct nouveau_copy copy = {
404 .src = nouveau_copy_rect_buffer(src, region->bufferOffset,
405 buffer_layout),
406 .dst = nouveau_copy_rect_image(dst, &dst->planes[plane],
407 region->imageOffset,
408 ®ion->imageSubresource),
409 .extent_el = nil_extent4d_px_to_el(extent4d_px, dst->planes[plane].nil.format,
410 dst->planes[plane].nil.sample_layout),
411 };
412 struct nouveau_copy copy2 = { 0 };
413
414 switch (dst->vk.format) {
415 case VK_FORMAT_D32_SFLOAT_S8_UINT:
416 if (aspects == VK_IMAGE_ASPECT_DEPTH_BIT) {
417 copy.remap.comp_size = 4;
418 copy.remap.dst[0] = NV90B5_SET_REMAP_COMPONENTS_DST_X_SRC_X;
419 copy.remap.dst[1] = NV90B5_SET_REMAP_COMPONENTS_DST_Y_NO_WRITE;
420 copy.remap.dst[2] = NV90B5_SET_REMAP_COMPONENTS_DST_Z_NO_WRITE;
421 copy.remap.dst[3] = NV90B5_SET_REMAP_COMPONENTS_DST_W_NO_WRITE;
422 } else {
423 assert(aspects == VK_IMAGE_ASPECT_STENCIL_BIT);
424 copy2.dst = copy.dst;
425 copy2.extent_el = copy.extent_el;
426 copy.dst = copy2.src =
427 nouveau_copy_rect_image(dst, &dst->stencil_copy_temp,
428 region->imageOffset,
429 ®ion->imageSubresource);
430
431 copy.remap.comp_size = 1;
432 copy.remap.dst[0] = NV90B5_SET_REMAP_COMPONENTS_DST_X_SRC_X;
433 copy.remap.dst[1] = NV90B5_SET_REMAP_COMPONENTS_DST_Y_NO_WRITE;
434 copy.remap.dst[2] = NV90B5_SET_REMAP_COMPONENTS_DST_Z_NO_WRITE;
435 copy.remap.dst[3] = NV90B5_SET_REMAP_COMPONENTS_DST_W_NO_WRITE;
436
437 copy2.remap.comp_size = 2;
438 copy2.remap.dst[0] = NV90B5_SET_REMAP_COMPONENTS_DST_X_NO_WRITE;
439 copy2.remap.dst[1] = NV90B5_SET_REMAP_COMPONENTS_DST_Y_NO_WRITE;
440 copy2.remap.dst[2] = NV90B5_SET_REMAP_COMPONENTS_DST_Z_SRC_X;
441 copy2.remap.dst[3] = NV90B5_SET_REMAP_COMPONENTS_DST_W_NO_WRITE;
442 }
443 break;
444 case VK_FORMAT_D24_UNORM_S8_UINT:
445 if (aspects == VK_IMAGE_ASPECT_DEPTH_BIT) {
446 copy.remap.comp_size = 1;
447 copy.remap.dst[0] = NV90B5_SET_REMAP_COMPONENTS_DST_X_SRC_X;
448 copy.remap.dst[1] = NV90B5_SET_REMAP_COMPONENTS_DST_Y_SRC_Y;
449 copy.remap.dst[2] = NV90B5_SET_REMAP_COMPONENTS_DST_Z_SRC_Z;
450 copy.remap.dst[3] = NV90B5_SET_REMAP_COMPONENTS_DST_W_NO_WRITE;
451 } else {
452 assert(aspects == VK_IMAGE_ASPECT_STENCIL_BIT);
453 copy.remap.comp_size = 1;
454 copy.remap.dst[0] = NV90B5_SET_REMAP_COMPONENTS_DST_X_NO_WRITE;
455 copy.remap.dst[1] = NV90B5_SET_REMAP_COMPONENTS_DST_Y_NO_WRITE;
456 copy.remap.dst[2] = NV90B5_SET_REMAP_COMPONENTS_DST_Z_NO_WRITE;
457 copy.remap.dst[3] = NV90B5_SET_REMAP_COMPONENTS_DST_W_SRC_X;
458 }
459 break;
460 default:
461 copy.remap = nouveau_copy_remap_format(dst->vk.format);
462 break;
463 }
464
465 nouveau_copy_rect(cmd, ©);
466 if (copy2.extent_el.width > 0)
467 nouveau_copy_rect(cmd, ©2);
468
469 vk_foreach_struct_const(ext, region->pNext) {
470 switch (ext->sType) {
471 default:
472 vk_debug_ignored_stype(ext->sType);
473 break;
474 }
475 }
476 }
477
478 vk_foreach_struct_const(ext, pCopyBufferToImageInfo->pNext) {
479 switch (ext->sType) {
480 default:
481 vk_debug_ignored_stype(ext->sType);
482 break;
483 }
484 }
485 }
486
487 VKAPI_ATTR void VKAPI_CALL
nvk_CmdCopyImageToBuffer2(VkCommandBuffer commandBuffer,const VkCopyImageToBufferInfo2 * pCopyImageToBufferInfo)488 nvk_CmdCopyImageToBuffer2(VkCommandBuffer commandBuffer,
489 const VkCopyImageToBufferInfo2 *pCopyImageToBufferInfo)
490 {
491 VK_FROM_HANDLE(nvk_cmd_buffer, cmd, commandBuffer);
492 VK_FROM_HANDLE(nvk_image, src, pCopyImageToBufferInfo->srcImage);
493 VK_FROM_HANDLE(nvk_buffer, dst, pCopyImageToBufferInfo->dstBuffer);
494
495 for (unsigned r = 0; r < pCopyImageToBufferInfo->regionCount; r++) {
496 const VkBufferImageCopy2 *region = &pCopyImageToBufferInfo->pRegions[r];
497 struct vk_image_buffer_layout buffer_layout =
498 vk_image_buffer_copy_layout(&src->vk, region);
499
500 const VkExtent3D extent_px =
501 vk_image_sanitize_extent(&src->vk, region->imageExtent);
502 const uint32_t layer_count =
503 vk_image_subresource_layer_count(&src->vk, ®ion->imageSubresource);
504 const struct nil_Extent4D_Pixels extent4d_px =
505 vk_to_nil_extent(extent_px, layer_count);
506
507 const VkImageAspectFlagBits aspects = region->imageSubresource.aspectMask;
508 uint8_t plane = nvk_image_aspects_to_plane(src, aspects);
509
510 struct nouveau_copy copy = {
511 .src = nouveau_copy_rect_image(src, &src->planes[plane],
512 region->imageOffset,
513 ®ion->imageSubresource),
514 .dst = nouveau_copy_rect_buffer(dst, region->bufferOffset,
515 buffer_layout),
516 .extent_el = nil_extent4d_px_to_el(extent4d_px, src->planes[plane].nil.format,
517 src->planes[plane].nil.sample_layout),
518 };
519 struct nouveau_copy copy2 = { 0 };
520
521 switch (src->vk.format) {
522 case VK_FORMAT_D32_SFLOAT_S8_UINT:
523 if (aspects == VK_IMAGE_ASPECT_DEPTH_BIT) {
524 copy.remap.comp_size = 4;
525 copy.remap.dst[0] = NV90B5_SET_REMAP_COMPONENTS_DST_X_SRC_X;
526 copy.remap.dst[1] = NV90B5_SET_REMAP_COMPONENTS_DST_Y_NO_WRITE;
527 copy.remap.dst[2] = NV90B5_SET_REMAP_COMPONENTS_DST_Z_NO_WRITE;
528 copy.remap.dst[3] = NV90B5_SET_REMAP_COMPONENTS_DST_W_NO_WRITE;
529 } else {
530 assert(aspects == VK_IMAGE_ASPECT_STENCIL_BIT);
531 copy2.dst = copy.dst;
532 copy2.extent_el = copy.extent_el;
533 copy.dst = copy2.src =
534 nouveau_copy_rect_image(src, &src->stencil_copy_temp,
535 region->imageOffset,
536 ®ion->imageSubresource);
537
538 copy.remap.comp_size = 2;
539 copy.remap.dst[0] = NV90B5_SET_REMAP_COMPONENTS_DST_X_SRC_Z;
540 copy.remap.dst[1] = NV90B5_SET_REMAP_COMPONENTS_DST_Y_NO_WRITE;
541 copy.remap.dst[2] = NV90B5_SET_REMAP_COMPONENTS_DST_Z_NO_WRITE;
542 copy.remap.dst[3] = NV90B5_SET_REMAP_COMPONENTS_DST_W_NO_WRITE;
543
544 copy2.remap.comp_size = 1;
545 copy2.remap.dst[0] = NV90B5_SET_REMAP_COMPONENTS_DST_X_SRC_X;
546 copy2.remap.dst[1] = NV90B5_SET_REMAP_COMPONENTS_DST_Y_NO_WRITE;
547 copy2.remap.dst[2] = NV90B5_SET_REMAP_COMPONENTS_DST_Z_NO_WRITE;
548 copy2.remap.dst[3] = NV90B5_SET_REMAP_COMPONENTS_DST_W_NO_WRITE;
549 }
550 break;
551 case VK_FORMAT_D24_UNORM_S8_UINT:
552 if (aspects == VK_IMAGE_ASPECT_DEPTH_BIT) {
553 copy.remap.comp_size = 1;
554 copy.remap.dst[0] = NV90B5_SET_REMAP_COMPONENTS_DST_X_SRC_X;
555 copy.remap.dst[1] = NV90B5_SET_REMAP_COMPONENTS_DST_Y_SRC_Y;
556 copy.remap.dst[2] = NV90B5_SET_REMAP_COMPONENTS_DST_Z_SRC_Z;
557 copy.remap.dst[3] = NV90B5_SET_REMAP_COMPONENTS_DST_W_NO_WRITE;
558 } else {
559 assert(aspects == VK_IMAGE_ASPECT_STENCIL_BIT);
560 copy.remap.comp_size = 1;
561 copy.remap.dst[0] = NV90B5_SET_REMAP_COMPONENTS_DST_X_SRC_W;
562 copy.remap.dst[1] = NV90B5_SET_REMAP_COMPONENTS_DST_Y_NO_WRITE;
563 copy.remap.dst[2] = NV90B5_SET_REMAP_COMPONENTS_DST_Z_NO_WRITE;
564 copy.remap.dst[3] = NV90B5_SET_REMAP_COMPONENTS_DST_W_NO_WRITE;
565 }
566 break;
567 default:
568 copy.remap = nouveau_copy_remap_format(src->vk.format);
569 break;
570 }
571
572 nouveau_copy_rect(cmd, ©);
573 if (copy2.extent_el.width > 0)
574 nouveau_copy_rect(cmd, ©2);
575
576 vk_foreach_struct_const(ext, region->pNext) {
577 switch (ext->sType) {
578 default:
579 vk_debug_ignored_stype(ext->sType);
580 break;
581 }
582 }
583 }
584
585 vk_foreach_struct_const(ext, pCopyImageToBufferInfo->pNext) {
586 switch (ext->sType) {
587 default:
588 vk_debug_ignored_stype(ext->sType);
589 break;
590 }
591 }
592 }
593
594 void
nvk_linear_render_copy(struct nvk_cmd_buffer * cmd,const struct nvk_image_view * iview,VkRect2D copy_rect,bool copy_to_tiled_shadow)595 nvk_linear_render_copy(struct nvk_cmd_buffer *cmd,
596 const struct nvk_image_view *iview,
597 VkRect2D copy_rect,
598 bool copy_to_tiled_shadow)
599 {
600 const struct nvk_image *image = (struct nvk_image *)iview->vk.image;
601
602 const uint8_t ip = iview->planes[0].image_plane;
603 const struct nvk_image_plane *src_plane = NULL, *dst_plane = NULL;
604 if (copy_to_tiled_shadow) {
605 src_plane = &image->planes[ip];
606 dst_plane = &image->linear_tiled_shadow;
607 } else {
608 src_plane = &image->linear_tiled_shadow;
609 dst_plane = &image->planes[ip];
610 }
611
612 const struct VkImageSubresourceLayers subres = {
613 .aspectMask = iview->vk.aspects,
614 .baseArrayLayer = iview->vk.base_array_layer,
615 .layerCount = iview->vk.layer_count,
616 .mipLevel = iview->vk.base_mip_level,
617 };
618
619 const VkOffset3D offset_px = {
620 .x = copy_rect.offset.x,
621 .y = copy_rect.offset.y,
622 .z = 0,
623 };
624 const struct nil_Extent4D_Pixels extent4d_px = {
625 .width = copy_rect.extent.width,
626 .height = copy_rect.extent.height,
627 .depth = 1,
628 .array_len = 1,
629 };
630
631 struct nouveau_copy copy = {
632 .src = nouveau_copy_rect_image(image, src_plane, offset_px, &subres),
633 .dst = nouveau_copy_rect_image(image, dst_plane, offset_px, &subres),
634 .extent_el = nil_extent4d_px_to_el(extent4d_px, src_plane->nil.format,
635 src_plane->nil.sample_layout),
636 };
637
638 copy.remap = nouveau_copy_remap_format(image->vk.format);
639 nouveau_copy_rect(cmd, ©);
640 }
641
642 VKAPI_ATTR void VKAPI_CALL
nvk_CmdCopyImage2(VkCommandBuffer commandBuffer,const VkCopyImageInfo2 * pCopyImageInfo)643 nvk_CmdCopyImage2(VkCommandBuffer commandBuffer,
644 const VkCopyImageInfo2 *pCopyImageInfo)
645 {
646 VK_FROM_HANDLE(nvk_cmd_buffer, cmd, commandBuffer);
647 VK_FROM_HANDLE(nvk_image, src, pCopyImageInfo->srcImage);
648 VK_FROM_HANDLE(nvk_image, dst, pCopyImageInfo->dstImage);
649
650 for (unsigned r = 0; r < pCopyImageInfo->regionCount; r++) {
651 const VkImageCopy2 *region = &pCopyImageInfo->pRegions[r];
652
653 /* From the Vulkan 1.3.217 spec:
654 *
655 * "When copying between compressed and uncompressed formats the
656 * extent members represent the texel dimensions of the source image
657 * and not the destination."
658 */
659 const VkExtent3D extent_px =
660 vk_image_sanitize_extent(&src->vk, region->extent);
661 const uint32_t layer_count =
662 vk_image_subresource_layer_count(&src->vk, ®ion->srcSubresource);
663 const struct nil_Extent4D_Pixels extent4d_px =
664 vk_to_nil_extent(extent_px, layer_count);
665
666 const VkImageAspectFlagBits src_aspects =
667 region->srcSubresource.aspectMask;
668 uint8_t src_plane = nvk_image_aspects_to_plane(src, src_aspects);
669
670 const VkImageAspectFlagBits dst_aspects =
671 region->dstSubresource.aspectMask;
672 uint8_t dst_plane = nvk_image_aspects_to_plane(dst, dst_aspects);
673
674 struct nouveau_copy copy = {
675 .src = nouveau_copy_rect_image(src, &src->planes[src_plane],
676 region->srcOffset,
677 ®ion->srcSubresource),
678 .dst = nouveau_copy_rect_image(dst, &dst->planes[dst_plane],
679 region->dstOffset,
680 ®ion->dstSubresource),
681 .extent_el = nil_extent4d_px_to_el(extent4d_px, src->planes[src_plane].nil.format,
682 src->planes[src_plane].nil.sample_layout),
683 };
684
685 assert(src_aspects == region->srcSubresource.aspectMask);
686 switch (src->vk.format) {
687 case VK_FORMAT_D24_UNORM_S8_UINT:
688 if (src_aspects == VK_IMAGE_ASPECT_DEPTH_BIT) {
689 copy.remap.comp_size = 1;
690 copy.remap.dst[0] = NV90B5_SET_REMAP_COMPONENTS_DST_W_SRC_X;
691 copy.remap.dst[1] = NV90B5_SET_REMAP_COMPONENTS_DST_Y_SRC_Y;
692 copy.remap.dst[2] = NV90B5_SET_REMAP_COMPONENTS_DST_Z_SRC_Z;
693 copy.remap.dst[3] = NV90B5_SET_REMAP_COMPONENTS_DST_W_NO_WRITE;
694 } else if (src_aspects == VK_IMAGE_ASPECT_STENCIL_BIT) {
695 copy.remap.comp_size = 1;
696 copy.remap.dst[0] = NV90B5_SET_REMAP_COMPONENTS_DST_X_NO_WRITE;
697 copy.remap.dst[1] = NV90B5_SET_REMAP_COMPONENTS_DST_Y_NO_WRITE;
698 copy.remap.dst[2] = NV90B5_SET_REMAP_COMPONENTS_DST_Z_NO_WRITE;
699 copy.remap.dst[3] = NV90B5_SET_REMAP_COMPONENTS_DST_W_SRC_W;
700 } else {
701 /* If we're copying both, there's nothing special to do */
702 assert(src_aspects == (VK_IMAGE_ASPECT_DEPTH_BIT |
703 VK_IMAGE_ASPECT_STENCIL_BIT));
704 }
705 break;
706 default:
707 copy.remap = nouveau_copy_remap_format(src->vk.format);
708 break;
709 }
710
711 nouveau_copy_rect(cmd, ©);
712 }
713 }
714
715 VKAPI_ATTR void VKAPI_CALL
nvk_CmdFillBuffer(VkCommandBuffer commandBuffer,VkBuffer dstBuffer,VkDeviceSize dstOffset,VkDeviceSize size,uint32_t data)716 nvk_CmdFillBuffer(VkCommandBuffer commandBuffer,
717 VkBuffer dstBuffer,
718 VkDeviceSize dstOffset,
719 VkDeviceSize size,
720 uint32_t data)
721 {
722 VK_FROM_HANDLE(nvk_cmd_buffer, cmd, commandBuffer);
723 VK_FROM_HANDLE(nvk_buffer, dst_buffer, dstBuffer);
724
725 uint64_t dst_addr = nvk_buffer_address(dst_buffer, dstOffset);
726 size = vk_buffer_range(&dst_buffer->vk, dstOffset, size);
727
728 uint32_t max_dim = 1 << 15;
729
730 struct nv_push *p = nvk_cmd_buffer_push(cmd, 7);
731
732 P_IMMD(p, NV90B5, SET_REMAP_CONST_A, data);
733 P_IMMD(p, NV90B5, SET_REMAP_COMPONENTS, {
734 .dst_x = DST_X_CONST_A,
735 .dst_y = DST_Y_CONST_A,
736 .dst_z = DST_Z_CONST_A,
737 .dst_w = DST_W_CONST_A,
738 .component_size = COMPONENT_SIZE_FOUR,
739 .num_src_components = NUM_SRC_COMPONENTS_ONE,
740 .num_dst_components = NUM_DST_COMPONENTS_ONE,
741 });
742
743 P_MTHD(p, NV90B5, PITCH_IN);
744 P_NV90B5_PITCH_IN(p, max_dim * 4);
745 P_NV90B5_PITCH_OUT(p, max_dim * 4);
746
747 while (size >= 4) {
748 struct nv_push *p = nvk_cmd_buffer_push(cmd, 8);
749
750 P_MTHD(p, NV90B5, OFFSET_OUT_UPPER);
751 P_NV90B5_OFFSET_OUT_UPPER(p, dst_addr >> 32);
752 P_NV90B5_OFFSET_OUT_LOWER(p, dst_addr & 0xffffffff);
753
754 uint64_t width, height;
755 if (size >= (uint64_t)max_dim * (uint64_t)max_dim * 4) {
756 width = height = max_dim;
757 } else if (size >= max_dim * 4) {
758 width = max_dim;
759 height = size / (max_dim * 4);
760 } else {
761 width = size / 4;
762 height = 1;
763 }
764
765 uint64_t dma_size = (uint64_t)width * (uint64_t)height * 4;
766 assert(dma_size <= size);
767
768 P_MTHD(p, NV90B5, LINE_LENGTH_IN);
769 P_NV90B5_LINE_LENGTH_IN(p, width);
770 P_NV90B5_LINE_COUNT(p, height);
771
772 P_IMMD(p, NV90B5, LAUNCH_DMA, {
773 .data_transfer_type = DATA_TRANSFER_TYPE_NON_PIPELINED,
774 .multi_line_enable = height > 1,
775 .flush_enable = FLUSH_ENABLE_TRUE,
776 .src_memory_layout = SRC_MEMORY_LAYOUT_PITCH,
777 .dst_memory_layout = DST_MEMORY_LAYOUT_PITCH,
778 .remap_enable = REMAP_ENABLE_TRUE,
779 });
780
781 dst_addr += dma_size;
782 size -= dma_size;
783 }
784 }
785
786 VKAPI_ATTR void VKAPI_CALL
nvk_CmdUpdateBuffer(VkCommandBuffer commandBuffer,VkBuffer dstBuffer,VkDeviceSize dstOffset,VkDeviceSize dataSize,const void * pData)787 nvk_CmdUpdateBuffer(VkCommandBuffer commandBuffer,
788 VkBuffer dstBuffer,
789 VkDeviceSize dstOffset,
790 VkDeviceSize dataSize,
791 const void *pData)
792 {
793 VK_FROM_HANDLE(nvk_cmd_buffer, cmd, commandBuffer);
794 VK_FROM_HANDLE(nvk_buffer, dst, dstBuffer);
795
796 uint64_t dst_addr = nvk_buffer_address(dst, dstOffset);
797
798 uint64_t data_addr;
799 nvk_cmd_buffer_upload_data(cmd, pData, dataSize, 64, &data_addr);
800
801 struct nv_push *p = nvk_cmd_buffer_push(cmd, 10);
802
803 P_MTHD(p, NV90B5, OFFSET_IN_UPPER);
804 P_NV90B5_OFFSET_IN_UPPER(p, data_addr >> 32);
805 P_NV90B5_OFFSET_IN_LOWER(p, data_addr & 0xffffffff);
806 P_NV90B5_OFFSET_OUT_UPPER(p, dst_addr >> 32);
807 P_NV90B5_OFFSET_OUT_LOWER(p, dst_addr & 0xffffffff);
808
809 P_MTHD(p, NV90B5, LINE_LENGTH_IN);
810 P_NV90B5_LINE_LENGTH_IN(p, dataSize);
811 P_NV90B5_LINE_COUNT(p, 1);
812
813 P_IMMD(p, NV90B5, LAUNCH_DMA, {
814 .data_transfer_type = DATA_TRANSFER_TYPE_NON_PIPELINED,
815 .multi_line_enable = MULTI_LINE_ENABLE_TRUE,
816 .flush_enable = FLUSH_ENABLE_TRUE,
817 .src_memory_layout = SRC_MEMORY_LAYOUT_PITCH,
818 .dst_memory_layout = DST_MEMORY_LAYOUT_PITCH,
819 });
820 }
821