1 /*
2 * Copyright © 2022 Mary Guillemard
3 * SPDX-License-Identifier: MIT
4 */
5 #include "mme_sim.h"
6
7 #include "mme_fermi.h"
8 #include "mme_fermi_sim.h"
9 #include "mme_tu104.h"
10 #include "mme_tu104_sim.h"
11
12 #define MME_CLS_FERMI 0x9000
13 #define MME_CLS_TURING 0xc500
14
15 void
mme_sim_core(const struct nv_device_info * devinfo,size_t macro_size,const void * macro,const struct mme_sim_state_ops * state_ops,void * state_handler)16 mme_sim_core(const struct nv_device_info *devinfo,
17 size_t macro_size, const void *macro,
18 const struct mme_sim_state_ops *state_ops,
19 void *state_handler)
20 {
21 if (devinfo->cls_eng3d >= MME_CLS_TURING) {
22 assert(macro_size % 12 == 0);
23 uint32_t inst_count = macro_size / 12;
24 struct mme_tu104_inst *insts =
25 malloc(inst_count * sizeof(struct mme_tu104_inst));
26 mme_tu104_decode(insts, macro, inst_count);
27 mme_tu104_sim_core(inst_count, insts, state_ops, state_handler);
28 free(insts);
29 } else if (devinfo->cls_eng3d >= MME_CLS_FERMI) {
30 assert(macro_size % 4 == 0);
31 uint32_t inst_count = macro_size / 4;
32 struct mme_fermi_inst *insts =
33 malloc(inst_count * sizeof(struct mme_fermi_inst));
34 mme_fermi_decode(insts, macro, inst_count);
35 mme_fermi_sim_core(inst_count, insts, state_ops, state_handler);
36 free(insts);
37 } else {
38 unreachable("Unsupported GPU class");
39 }
40 }
41