1 /*
2 * Copyright © 2021 Ilia Mirkin
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 */
23
24 #include <limits.h>
25 #include <stdio.h>
26 #include <stdint.h>
27 #include <stdlib.h>
28 #include <sys/ioctl.h>
29 #include "drm-uapi/nouveau_drm.h"
30 #include "nouveau/nvif/ioctl.h"
31 #include "nouveau/nvif/cl0080.h"
32 #include "drm-shim/drm_shim.h"
33 #include "util/u_math.h"
34
35 #include "../../gallium/drivers/nouveau/nv_object.xml.h"
36 bool drm_shim_driver_prefers_first_render_node = true;
37
38 struct nouveau_device {
39 uint64_t next_offset;
40 };
41
42 static struct nouveau_device nouveau = {
43 .next_offset = 0x1000,
44 };
45
46 struct nouveau_shim_bo {
47 struct shim_bo base;
48 uint64_t offset;
49 };
50
51 static struct nouveau_shim_bo *
nouveau_shim_bo(struct shim_bo * bo)52 nouveau_shim_bo(struct shim_bo *bo)
53 {
54 return (struct nouveau_shim_bo *)bo;
55 }
56
57 struct nouveau_device_info {
58 uint32_t chip_id;
59 };
60
61 static struct nouveau_device_info device_info;
62
63 static int
nouveau_ioctl_noop(int fd,unsigned long request,void * arg)64 nouveau_ioctl_noop(int fd, unsigned long request, void *arg)
65 {
66 return 0;
67 }
68
69 static int
nouveau_ioctl_gem_new(int fd,unsigned long request,void * arg)70 nouveau_ioctl_gem_new(int fd, unsigned long request, void *arg)
71 {
72 struct shim_fd *shim_fd = drm_shim_fd_lookup(fd);
73 struct drm_nouveau_gem_new *create = arg;
74 struct nouveau_shim_bo *bo = calloc(1, sizeof(*bo));
75
76 drm_shim_bo_init(&bo->base, create->info.size);
77
78 assert(ULONG_MAX - nouveau.next_offset > create->info.size);
79
80 create->info.handle = drm_shim_bo_get_handle(shim_fd, &bo->base);
81 create->info.map_handle = drm_shim_bo_get_mmap_offset(shim_fd, &bo->base);
82
83 if (create->align != 0)
84 nouveau.next_offset = align64(nouveau.next_offset, create->align);
85 create->info.offset = nouveau.next_offset;
86 nouveau.next_offset += create->info.size;
87
88 bo->offset = create->info.offset;
89
90 drm_shim_bo_put(&bo->base);
91
92 return 0;
93 }
94
95 static int
nouveau_ioctl_gem_info(int fd,unsigned long request,void * arg)96 nouveau_ioctl_gem_info(int fd, unsigned long request, void *arg)
97 {
98 struct shim_fd *shim_fd = drm_shim_fd_lookup(fd);
99 struct drm_nouveau_gem_info *info = arg;
100 struct nouveau_shim_bo *bo =
101 nouveau_shim_bo(drm_shim_bo_lookup(shim_fd, info->handle));
102 info->map_handle = drm_shim_bo_get_mmap_offset(shim_fd, &bo->base);
103 info->offset = bo->offset;
104 info->size = bo->base.size;
105
106 drm_shim_bo_put(&bo->base);
107
108 return 0;
109 }
110
111 static int
nouveau_ioctl_gem_pushbuf(int fd,unsigned long request,void * arg)112 nouveau_ioctl_gem_pushbuf(int fd, unsigned long request, void *arg)
113 {
114 struct drm_nouveau_gem_pushbuf *submit = arg;
115 submit->vram_available = 3ULL << 30;
116 submit->gart_available = 1ULL << 40;
117 return 0;
118 }
119
120 static int
nouveau_ioctl_channel_alloc(int fd,unsigned long request,void * arg)121 nouveau_ioctl_channel_alloc(int fd, unsigned long request, void *arg)
122 {
123 struct shim_fd *shim_fd = drm_shim_fd_lookup(fd);
124 struct drm_nouveau_channel_alloc *alloc = arg;
125 if (device_info.chip_id == 0x50 || device_info.chip_id >= 0x80)
126 alloc->pushbuf_domains = NOUVEAU_GEM_DOMAIN_VRAM | NOUVEAU_GEM_DOMAIN_GART;
127 else
128 alloc->pushbuf_domains = NOUVEAU_GEM_DOMAIN_GART;
129
130 /* NOTE: this will get leaked since we don't handle the channel
131 * free. However only one channel is created per screen, so impact should
132 * be limited. */
133 struct nouveau_shim_bo *notify = calloc(1, sizeof(*notify));
134 drm_shim_bo_init(¬ify->base, 0x1000);
135 notify->offset = nouveau.next_offset;
136 nouveau.next_offset += 0x1000;
137 alloc->notifier_handle = drm_shim_bo_get_handle(shim_fd, ¬ify->base);
138
139 drm_shim_bo_put(¬ify->base);
140
141 return 0;
142 }
143
144 static int
nouveau_ioctl_get_param(int fd,unsigned long request,void * arg)145 nouveau_ioctl_get_param(int fd, unsigned long request, void *arg)
146 {
147 struct drm_nouveau_getparam *gp = arg;
148
149 switch (gp->param) {
150 case NOUVEAU_GETPARAM_CHIPSET_ID:
151 gp->value = device_info.chip_id;
152 return 0;
153 case NOUVEAU_GETPARAM_PCI_VENDOR:
154 gp->value = 0x10de;
155 return 0;
156 case NOUVEAU_GETPARAM_PCI_DEVICE:
157 gp->value = 0x1004;
158 return 0;
159 case NOUVEAU_GETPARAM_BUS_TYPE:
160 gp->value = 2 /* NV_PCIE */;
161 return 0;
162 case NOUVEAU_GETPARAM_FB_SIZE:
163 gp->value = 3ULL << 30;
164 return 0;
165 case NOUVEAU_GETPARAM_AGP_SIZE:
166 gp->value = 1ULL << 40;
167 return 0;
168 case NOUVEAU_GETPARAM_PTIMER_TIME:
169 gp->value = 0;
170 return 0;
171 case NOUVEAU_GETPARAM_HAS_BO_USAGE:
172 gp->value = 1;
173 return 0;
174 case NOUVEAU_GETPARAM_GRAPH_UNITS:
175 gp->value = 0x01000101;
176 return 0;
177 default:
178 fprintf(stderr, "Unknown DRM_IOCTL_NOUVEAU_GETPARAM %llu\n",
179 (long long unsigned)gp->param);
180 return -1;
181 }
182 }
183
184 static int
nouveau_ioctl_nvif(int fd,unsigned long request,void * arg)185 nouveau_ioctl_nvif(int fd, unsigned long request, void *arg)
186 {
187 struct {
188 struct nvif_ioctl_v0 ioctl;
189 } *args = arg;
190
191 switch (args->ioctl.type) {
192 case NVIF_IOCTL_V0_MTHD: {
193 struct {
194 struct nvif_ioctl_v0 ioctl;
195 struct nvif_ioctl_mthd_v0 mthd;
196 } *mthd = (void *)args;
197 switch (mthd->mthd.method) {
198 case NV_DEVICE_V0_INFO: {
199 struct nv_device_info_v0 *info = (void *)&mthd->mthd.data;
200 info->chipset = device_info.chip_id;
201 info->platform = NV_DEVICE_INFO_V0_PCIE;
202
203 /* make something up */
204 info->ram_user = 3ULL << 30;
205 break;
206 }
207 default:
208 break;
209 }
210 break;
211 }
212 case NVIF_IOCTL_V0_SCLASS: {
213 struct {
214 struct nvif_ioctl_v0 ioctl;
215 struct nvif_ioctl_sclass_v0 sclass;
216 } *sclass = (void *)args;
217
218 if (sclass->sclass.count == 0) {
219 sclass->sclass.count = device_info.chip_id >= 0xe0 ? 4 : 3;
220 return 0;
221 }
222 int idx = 0;
223 /* m2mf */
224 switch (device_info.chip_id & ~0xf) {
225 case 0x170:
226 case 0x160:
227 case 0x140:
228 case 0x130:
229 case 0x120:
230 case 0x110:
231 case 0x100:
232 case 0xf0:
233 sclass->sclass.oclass[idx].oclass = NVF0_P2MF_CLASS;
234 break;
235 case 0xe0:
236 sclass->sclass.oclass[idx].oclass = NVE4_P2MF_CLASS;
237 break;
238 default:
239 sclass->sclass.oclass[idx].oclass = NVC0_M2MF_CLASS;
240 break;
241 }
242 sclass->sclass.oclass[idx].minver = -1;
243 sclass->sclass.oclass[idx].maxver = -1;
244 idx++;
245 if (device_info.chip_id >= 0xe0) {
246 switch (device_info.chip_id & ~0xf) {
247 case 0x170:
248 sclass->sclass.oclass[idx].oclass = AMPERE_DMA_COPY_A;
249 break;
250 case 0x160:
251 sclass->sclass.oclass[idx].oclass = TURING_DMA_COPY_A;
252 break;
253 case 0x140:
254 sclass->sclass.oclass[idx].oclass = VOLTA_DMA_COPY_A;
255 break;
256 case 0x130:
257 sclass->sclass.oclass[idx].oclass = PASCAL_DMA_COPY_A;
258 break;
259 case 0x120:
260 case 0x110:
261 sclass->sclass.oclass[idx].oclass = MAXWELL_DMA_COPY_A;
262 break;
263 case 0x100:
264 case 0xf0:
265 case 0xe0:
266 sclass->sclass.oclass[idx].oclass = KEPLER_DMA_COPY_A;
267 break;
268 }
269 sclass->sclass.oclass[idx].minver = -1;
270 sclass->sclass.oclass[idx].maxver = -1;
271 idx++;
272 }
273 /* 2d */
274 if (device_info.chip_id >= 0x50) {
275 if (device_info.chip_id <= 0xa0)
276 sclass->sclass.oclass[idx].oclass = NV50_2D_CLASS;
277 else
278 sclass->sclass.oclass[idx].oclass = NVC0_2D_CLASS;
279
280 sclass->sclass.oclass[idx].minver = -1;
281 sclass->sclass.oclass[idx].maxver = -1;
282 idx++;
283 }
284 /* 3d */
285 switch (device_info.chip_id & ~0xf) {
286 case 0x170:
287 sclass->sclass.oclass[idx].oclass = GA102_3D_CLASS;
288 break;
289 case 0x160:
290 sclass->sclass.oclass[idx].oclass = TU102_3D_CLASS;
291 break;
292 case 0x140:
293 sclass->sclass.oclass[idx].oclass = GV100_3D_CLASS;
294 break;
295 case 0x130:
296 switch (device_info.chip_id) {
297 case 0x130:
298 case 0x13b:
299 sclass->sclass.oclass[idx].oclass = GP100_3D_CLASS;
300 break;
301 default:
302 sclass->sclass.oclass[idx].oclass = GP102_3D_CLASS;
303 break;
304 }
305 break;
306 case 0x120:
307 sclass->sclass.oclass[idx].oclass = GM200_3D_CLASS;
308 break;
309 case 0x110:
310 sclass->sclass.oclass[idx].oclass = GM107_3D_CLASS;
311 break;
312 case 0x100:
313 case 0xf0:
314 sclass->sclass.oclass[idx].oclass = NVF0_3D_CLASS;
315 break;
316 case 0xe0:
317 switch (device_info.chip_id) {
318 case 0xea:
319 sclass->sclass.oclass[idx].oclass = NVEA_3D_CLASS;
320 break;
321 default:
322 sclass->sclass.oclass[idx].oclass = NVE4_3D_CLASS;
323 break;
324 }
325 break;
326 case 0xd0:
327 sclass->sclass.oclass[idx].oclass = NVC8_3D_CLASS;
328 break;
329 default:
330 case 0xc0:
331 switch (device_info.chip_id) {
332 case 0xc8:
333 sclass->sclass.oclass[idx].oclass = NVC8_3D_CLASS;
334 break;
335 case 0xc1:
336 sclass->sclass.oclass[idx].oclass = NVC1_3D_CLASS;
337 break;
338 default:
339 sclass->sclass.oclass[idx].oclass = NVC0_3D_CLASS;
340 break;
341 }
342 break;
343 }
344 sclass->sclass.oclass[idx].minver = -1;
345 sclass->sclass.oclass[idx].maxver = -1;
346 idx++;
347 switch (device_info.chip_id & ~0xf) {
348 case 0x170:
349 sclass->sclass.oclass[idx].oclass = GA102_COMPUTE_CLASS;
350 break;
351 case 0x160:
352 sclass->sclass.oclass[idx].oclass = TU102_COMPUTE_CLASS;
353 break;
354 case 0x140:
355 sclass->sclass.oclass[idx].oclass = GV100_COMPUTE_CLASS;
356 break;
357 case 0x130:
358 switch (device_info.chip_id) {
359 case 0x130:
360 case 0x13b:
361 sclass->sclass.oclass[idx].oclass = GP100_COMPUTE_CLASS;
362 break;
363 default:
364 sclass->sclass.oclass[idx].oclass = GP104_COMPUTE_CLASS;
365 break;
366 }
367 break;
368 case 0x120:
369 sclass->sclass.oclass[idx].oclass = GM200_COMPUTE_CLASS;
370 break;
371 case 0x110:
372 sclass->sclass.oclass[idx].oclass = GM107_COMPUTE_CLASS;
373 break;
374 case 0x100:
375 case 0xf0:
376 sclass->sclass.oclass[idx].oclass = NVF0_COMPUTE_CLASS;
377 break;
378 case 0xe0:
379 sclass->sclass.oclass[idx].oclass = NVE4_COMPUTE_CLASS;
380 break;
381 default:
382 sclass->sclass.oclass[idx].oclass = NVC0_COMPUTE_CLASS;
383 break;
384 }
385 sclass->sclass.oclass[idx].minver = -1;
386 sclass->sclass.oclass[idx].maxver = -1;
387 break;
388 }
389 default:
390 break;
391 }
392
393 return 0;
394 }
395
396 static ioctl_fn_t driver_ioctls[] = {
397 [DRM_NOUVEAU_GETPARAM] = nouveau_ioctl_get_param,
398 [DRM_NOUVEAU_NVIF] = nouveau_ioctl_nvif,
399 [DRM_NOUVEAU_CHANNEL_ALLOC] = nouveau_ioctl_channel_alloc,
400 [DRM_NOUVEAU_CHANNEL_FREE] = nouveau_ioctl_noop,
401 [DRM_NOUVEAU_GROBJ_ALLOC] = nouveau_ioctl_noop,
402 [DRM_NOUVEAU_NOTIFIEROBJ_ALLOC] = nouveau_ioctl_noop,
403 [DRM_NOUVEAU_GPUOBJ_FREE] = nouveau_ioctl_noop,
404 [DRM_NOUVEAU_GEM_NEW] = nouveau_ioctl_gem_new,
405 [DRM_NOUVEAU_GEM_PUSHBUF] = nouveau_ioctl_gem_pushbuf,
406 [DRM_NOUVEAU_GEM_CPU_PREP] = nouveau_ioctl_noop,
407 [DRM_NOUVEAU_GEM_INFO] = nouveau_ioctl_gem_info,
408 [DRM_NOUVEAU_GEM_CPU_FINI] = nouveau_ioctl_gem_info,
409 [DRM_NOUVEAU_VM_INIT] = nouveau_ioctl_noop,
410 [DRM_NOUVEAU_VM_BIND] = nouveau_ioctl_noop,
411 [DRM_NOUVEAU_EXEC] = nouveau_ioctl_noop,
412 };
413
414 static void
nouveau_driver_get_device_info(void)415 nouveau_driver_get_device_info(void)
416 {
417 const char *env = getenv("NOUVEAU_CHIPSET");
418
419 if (!env) {
420 device_info.chip_id = 0xf0;
421 return;
422 }
423
424 device_info.chip_id = strtol(env, NULL, 16);
425 }
426
427 void
drm_shim_driver_init(void)428 drm_shim_driver_init(void)
429 {
430 shim_device.bus_type = DRM_BUS_PCI;
431 shim_device.driver_name = "nouveau";
432 shim_device.driver_ioctls = driver_ioctls;
433 shim_device.driver_ioctl_count = ARRAY_SIZE(driver_ioctls);
434
435 shim_device.version_major = 1;
436 shim_device.version_minor = 3;
437 shim_device.version_patchlevel = 1;
438
439 nouveau_driver_get_device_info();
440
441 /* Ask userspace to consider all fences completed. */
442 setenv("NOUVEAU_DISABLE_FENCES", "true", true);
443
444 /* nothing looks at the pci id, so fix it to a GTX 780 */
445 static const char uevent_content[] =
446 "DRIVER=nouveau\n"
447 "PCI_CLASS=30000\n"
448 "PCI_ID=10de:1004\n"
449 "PCI_SUBSYS_ID=1028:075B\n"
450 "PCI_SLOT_NAME=0000:01:00.0\n"
451 "MODALIAS=pci:v000010ded00005916sv00001028sd0000075Bbc03sc00i00\n";
452 drm_shim_override_file(uevent_content,
453 "/sys/dev/char/%d:%d/device/uevent",
454 DRM_MAJOR, render_node_minor);
455 drm_shim_override_file("0x0\n",
456 "/sys/dev/char/%d:%d/device/revision",
457 DRM_MAJOR, render_node_minor);
458 drm_shim_override_file("0x10de",
459 "/sys/dev/char/%d:%d/device/vendor",
460 DRM_MAJOR, render_node_minor);
461 drm_shim_override_file("0x10de",
462 "/sys/devices/pci0000:00/0000:01:00.0/vendor");
463 drm_shim_override_file("0x1004",
464 "/sys/dev/char/%d:%d/device/device",
465 DRM_MAJOR, render_node_minor);
466 drm_shim_override_file("0x1004",
467 "/sys/devices/pci0000:00/0000:01:00.0/device");
468 drm_shim_override_file("0x1234",
469 "/sys/dev/char/%d:%d/device/subsystem_vendor",
470 DRM_MAJOR, render_node_minor);
471 drm_shim_override_file("0x1234",
472 "/sys/devices/pci0000:00/0000:01:00.0/subsystem_vendor");
473 drm_shim_override_file("0x1234",
474 "/sys/dev/char/%d:%d/device/subsystem_device",
475 DRM_MAJOR, render_node_minor);
476 drm_shim_override_file("0x1234",
477 "/sys/devices/pci0000:00/0000:01:00.0/subsystem_device");
478 }
479