xref: /aosp_15_r20/external/mesa3d/src/intel/vulkan/grl/genX_grl_dispatch.c (revision 6104692788411f58d303aa86923a9ff6ecaded22)
1 /*
2  * Copyright © 2021 Corporation
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice (including the next
12  * paragraph) shall be included in all copies or substantial portions of the
13  * Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21  * IN THE SOFTWARE.
22  */
23 
24 #include "anv_private.h"
25 #include "genX_grl.h"
26 
27 static struct anv_shader_bin *
get_shader_bin(struct anv_device * device,enum grl_cl_kernel kernel)28 get_shader_bin(struct anv_device *device,
29                enum grl_cl_kernel kernel)
30 {
31    const char *key = genX(grl_get_cl_kernel_sha1)(kernel);
32    int key_len = strlen(key);
33 
34    bool cache_hit = false;
35    struct anv_shader_bin *bin =
36       anv_device_search_for_kernel(device, device->internal_cache,
37                                    key, key_len, &cache_hit);
38    if (bin != NULL)
39       return bin;
40 
41    uint32_t dummy_param[32];
42    struct brw_kernel kernel_data;
43    genX(grl_get_cl_kernel)(&kernel_data, kernel);
44 
45    assert(kernel_data.prog_data.base.nr_params <= ARRAY_SIZE(dummy_param));
46    kernel_data.prog_data.base.param = dummy_param;
47 
48    struct anv_push_descriptor_info empty_push_desc_info = {};
49    struct anv_pipeline_bind_map bind_map = {
50       .kernel_args_size = kernel_data.args_size,
51       .kernel_arg_count = kernel_data.arg_count,
52       .kernel_args = (struct brw_kernel_arg_desc *)kernel_data.args,
53    };
54 
55    struct anv_shader_upload_params upload_params = {
56       .stage               = MESA_SHADER_KERNEL,
57       .key_data            = key,
58       .key_size            = key_len,
59       .kernel_data         = kernel_data.code,
60       .kernel_size         = kernel_data.prog_data.base.program_size,
61       .prog_data           = &kernel_data.prog_data.base,
62       .prog_data_size      = sizeof(kernel_data.prog_data),
63       .bind_map            = &bind_map,
64       .push_desc_info      = &empty_push_desc_info,
65    };
66 
67    bin = anv_device_upload_kernel(device, device->internal_cache,
68                                   &upload_params);
69 
70    /* The cache already has a reference and it's not going anywhere so there
71     * is no need to hold a second reference.
72     */
73    anv_shader_bin_unref(device, bin);
74 
75    return bin;
76 }
77 
78 void
genX(grl_dispatch)79 genX(grl_dispatch)(struct anv_cmd_buffer *cmd_buffer,
80                    enum grl_cl_kernel kernel,
81                    const uint32_t *global_size,
82                    uint32_t arg_count,
83                    const struct anv_kernel_arg *args)
84 {
85    struct anv_device *device = cmd_buffer->device;
86 
87    const struct intel_l3_weights w =
88       intel_get_default_l3_weights(device->info, true, true);
89 
90    struct anv_kernel ak = {
91       .bin = get_shader_bin(device, kernel),
92       .l3_config = intel_get_l3_config(device->info, w),
93    };
94 
95    genX(cmd_buffer_dispatch_kernel)(cmd_buffer, &ak, global_size,
96                                     arg_count, args);
97 }
98 
99 uint32_t
genX(grl_max_scratch_size)100 genX(grl_max_scratch_size)(void)
101 {
102    uint32_t scratch_size = 0;
103 
104    for (uint32_t i = 0; i < GRL_CL_KERNEL_MAX; i++) {
105       struct brw_kernel kernel_data;
106       genX(grl_get_cl_kernel)(&kernel_data, i);
107 
108       scratch_size = MAX2(kernel_data.prog_data.base.total_scratch,
109                           scratch_size);
110    }
111 
112    return scratch_size;
113 }
114