xref: /aosp_15_r20/external/mesa3d/src/intel/vulkan/genX_mi_builder.h (revision 6104692788411f58d303aa86923a9ff6ecaded22)
1 /* Copyright © 2024 Intel Corporation
2  * SPDX-License-Identifier: MIT
3  */
4 
5 #pragma once
6 
7 #include "genxml/gen_macros.h"
8 #include "genxml/genX_pack.h"
9 
10 /* We reserve :
11  *    - GPR 13 for STATE_BASE_ADDRESS bindless surface base address
12  *    - GPR 14 for perf queries
13  *    - GPR 15 for conditional rendering
14  */
15 #define MI_BUILDER_NUM_ALLOC_GPRS 13
16 #define MI_BUILDER_CAN_WRITE_BATCH true
17 /* Don't do any write check by default, we manually set it where it matters.
18  */
19 #define MI_BUILDER_DEFAULT_WRITE_CHECK false
20 #define __gen_get_batch_dwords anv_batch_emit_dwords
21 #define __gen_address_offset anv_address_add
22 #define __gen_get_batch_address(b, a) anv_batch_address(b, a)
23 #define __gen_get_write_fencing_status(b) (&(b)->write_fence_status)
24 #include "common/mi_builder.h"
25