1 /*
2 * Copyright © 2020 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 */
23
24 #include <stdio.h>
25 #include <stdlib.h>
26 #include <unistd.h>
27 #include <sys/ioctl.h>
28 #include <sys/mman.h>
29 #include <sys/types.h>
30 #include <sys/socket.h>
31 #include <sys/time.h>
32 #include <sys/resource.h>
33 #include <sys/un.h>
34
35 #include "common/intel_gem.h"
36 #include "dev/intel_device_info.h"
37 #include "dev/intel_device_info_serialize.h"
38 #include "drm-uapi/i915_drm.h"
39 #include "drm-shim/drm_shim.h"
40 #include "util/macros.h"
41 #include "util/vma.h"
42
43 struct i915_device {
44 struct intel_device_info devinfo;
45 uint32_t device_id;
46 };
47
48 struct i915_bo {
49 struct shim_bo base;
50 uint32_t tiling_mode;
51 uint32_t stride;
52 };
53
54 static struct i915_device i915 = {};
55 static bool i915_device_from_json = false;
56
57 bool drm_shim_driver_prefers_first_render_node = true;
58
59 static int
i915_ioctl_noop(int fd,unsigned long request,void * arg)60 i915_ioctl_noop(int fd, unsigned long request, void *arg)
61 {
62 return 0;
63 }
64
65 static int
i915_ioctl_gem_set_tiling(int fd,unsigned long request,void * arg)66 i915_ioctl_gem_set_tiling(int fd, unsigned long request, void *arg)
67 {
68 struct shim_fd *shim_fd = drm_shim_fd_lookup(fd);
69 struct drm_i915_gem_set_tiling *tiling_arg = arg;
70 struct i915_bo *bo = (struct i915_bo *) drm_shim_bo_lookup(shim_fd, tiling_arg->handle);
71
72 if (!bo)
73 return -1;
74
75 bo->tiling_mode = tiling_arg->tiling_mode;
76 bo->stride = tiling_arg->stride;
77
78 return 0;
79 }
80
81 static int
i915_ioctl_gem_get_tiling(int fd,unsigned long request,void * arg)82 i915_ioctl_gem_get_tiling(int fd, unsigned long request, void *arg)
83 {
84 struct shim_fd *shim_fd = drm_shim_fd_lookup(fd);
85 struct drm_i915_gem_get_tiling *tiling_arg = arg;
86 struct i915_bo *bo = (struct i915_bo *) drm_shim_bo_lookup(shim_fd, tiling_arg->handle);
87
88 if (!bo)
89 return -1;
90
91 tiling_arg->tiling_mode = bo->tiling_mode;
92 tiling_arg->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
93 tiling_arg->phys_swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
94
95 return 0;
96 }
97
98 static int
i915_ioctl_gem_create(int fd,unsigned long request,void * arg)99 i915_ioctl_gem_create(int fd, unsigned long request, void *arg)
100 {
101 struct shim_fd *shim_fd = drm_shim_fd_lookup(fd);
102 struct drm_i915_gem_create *create = arg;
103 struct i915_bo *bo = calloc(1, sizeof(*bo));
104
105 drm_shim_bo_init(&bo->base, create->size);
106
107 create->handle = drm_shim_bo_get_handle(shim_fd, &bo->base);
108
109 drm_shim_bo_put(&bo->base);
110
111 return 0;
112 }
113
114 static int
i915_ioctl_gem_create_ext(int fd,unsigned long request,void * arg)115 i915_ioctl_gem_create_ext(int fd, unsigned long request, void *arg)
116 {
117 struct shim_fd *shim_fd = drm_shim_fd_lookup(fd);
118 struct drm_i915_gem_create_ext *create = arg;
119 struct i915_bo *bo = calloc(1, sizeof(*bo));
120
121 drm_shim_bo_init(&bo->base, create->size);
122
123 create->handle = drm_shim_bo_get_handle(shim_fd, &bo->base);
124
125 drm_shim_bo_put(&bo->base);
126
127 return 0;
128 }
129
130 static int
i915_ioctl_gem_mmap(int fd,unsigned long request,void * arg)131 i915_ioctl_gem_mmap(int fd, unsigned long request, void *arg)
132 {
133 struct shim_fd *shim_fd = drm_shim_fd_lookup(fd);
134 struct drm_i915_gem_mmap *mmap_arg = arg;
135 struct shim_bo *bo = drm_shim_bo_lookup(shim_fd, mmap_arg->handle);
136
137 if (!bo)
138 return -1;
139
140 if (!bo->map)
141 bo->map = drm_shim_mmap(shim_fd, bo->size, PROT_READ | PROT_WRITE, MAP_SHARED, -1,
142 drm_shim_bo_get_mmap_offset(shim_fd, bo));
143
144 mmap_arg->addr_ptr = (uint64_t) (bo->map + mmap_arg->offset);
145
146 return 0;
147 }
148
149 static int
i915_ioctl_gem_mmap_offset(int fd,unsigned long request,void * arg)150 i915_ioctl_gem_mmap_offset(int fd, unsigned long request, void *arg)
151 {
152 struct shim_fd *shim_fd = drm_shim_fd_lookup(fd);
153 struct drm_i915_gem_mmap_offset *mmap_arg = arg;
154 struct shim_bo *bo = drm_shim_bo_lookup(shim_fd, mmap_arg->handle);
155
156 if (!bo)
157 return -1;
158
159 if (!bo->map)
160 bo->map = drm_shim_mmap(shim_fd, bo->size, PROT_READ | PROT_WRITE, MAP_SHARED, -1,
161 drm_shim_bo_get_mmap_offset(shim_fd, bo));
162
163 mmap_arg->offset = drm_shim_bo_get_mmap_offset(shim_fd, bo);
164
165 return 0;
166 }
167
168 static int
i915_ioctl_gem_userptr(int fd,unsigned long request,void * arg)169 i915_ioctl_gem_userptr(int fd, unsigned long request, void *arg)
170 {
171 struct shim_fd *shim_fd = drm_shim_fd_lookup(fd);
172 struct drm_i915_gem_userptr *userptr = arg;
173 struct i915_bo *bo = calloc(1, sizeof(*bo));
174
175 drm_shim_bo_init(&bo->base, userptr->user_size);
176
177 userptr->handle = drm_shim_bo_get_handle(shim_fd, &bo->base);
178
179 drm_shim_bo_put(&bo->base);
180
181 return 0;
182 }
183
184 static int
i915_ioctl_gem_context_create(int fd,unsigned long request,void * arg)185 i915_ioctl_gem_context_create(int fd, unsigned long request, void *arg)
186 {
187 struct drm_i915_gem_context_create *create = arg;
188
189 create->ctx_id = 1; /* Just return a fake non zero ID. */
190
191 return 0;
192 }
193
194 static int
i915_ioctl_gem_context_getparam(int fd,unsigned long request,void * arg)195 i915_ioctl_gem_context_getparam(int fd, unsigned long request, void *arg)
196 {
197 struct drm_i915_gem_context_param *param = arg;
198
199 if (param->param == I915_CONTEXT_PARAM_GTT_SIZE) {
200 if (i915.devinfo.ver >= 8 && i915.devinfo.platform != INTEL_PLATFORM_CHV)
201 param->value = 1ull << 48;
202 else
203 param->value = 1ull << 31;
204 } else {
205 param->value = 0;
206 }
207
208 return 0;
209 }
210
211 static int
i915_ioctl_get_param(int fd,unsigned long request,void * arg)212 i915_ioctl_get_param(int fd, unsigned long request, void *arg)
213 {
214 drm_i915_getparam_t *gp = arg;
215
216 switch (gp->param) {
217 case I915_PARAM_CHIPSET_ID:
218 *gp->value = i915.device_id;
219 return 0;
220 case I915_PARAM_REVISION:
221 *gp->value = 0;
222 return 0;
223 case I915_PARAM_CS_TIMESTAMP_FREQUENCY:
224 *gp->value = i915.devinfo.timestamp_frequency;
225 return 0;
226 case I915_PARAM_HAS_ALIASING_PPGTT:
227 if (i915.devinfo.ver < 6)
228 *gp->value = I915_GEM_PPGTT_NONE;
229 else if (i915.devinfo.ver <= 7)
230 *gp->value = I915_GEM_PPGTT_ALIASING;
231 else
232 *gp->value = I915_GEM_PPGTT_FULL;
233 return 0;
234
235 case I915_PARAM_NUM_FENCES_AVAIL:
236 *gp->value = 8; /* gfx2/3 value, unused in brw/iris */
237 return 0;
238
239 case I915_PARAM_HAS_BLT:
240 *gp->value = 1; /* gfx2/3 value, unused in brw/iris */
241 return 0;
242
243 case I915_PARAM_HAS_BSD:
244 case I915_PARAM_HAS_LLC:
245 case I915_PARAM_HAS_VEBOX:
246 *gp->value = 0; /* gfx2/3 value, unused in brw/iris */
247 return 0;
248
249 case I915_PARAM_HAS_GEM:
250 case I915_PARAM_HAS_RELAXED_DELTA:
251 case I915_PARAM_HAS_RELAXED_FENCING:
252 case I915_PARAM_HAS_WAIT_TIMEOUT:
253 case I915_PARAM_HAS_EXECBUF2:
254 case I915_PARAM_HAS_EXEC_SOFTPIN:
255 case I915_PARAM_HAS_EXEC_CAPTURE:
256 case I915_PARAM_HAS_EXEC_FENCE:
257 case I915_PARAM_HAS_EXEC_FENCE_ARRAY:
258 case I915_PARAM_HAS_CONTEXT_ISOLATION:
259 case I915_PARAM_HAS_EXEC_ASYNC:
260 case I915_PARAM_HAS_EXEC_NO_RELOC:
261 case I915_PARAM_HAS_EXEC_BATCH_FIRST:
262 *gp->value = true;
263 return 0;
264 case I915_PARAM_HAS_EXEC_TIMELINE_FENCES:
265 *gp->value = true;
266 return 0;
267 case I915_PARAM_CMD_PARSER_VERSION:
268 /* Most recent version in drivers/gpu/drm/i915/i915_cmd_parser.c */
269 *gp->value = 10;
270 return 0;
271 case I915_PARAM_MMAP_VERSION:
272 case I915_PARAM_MMAP_GTT_VERSION:
273 *gp->value = 4 /* MMAP_OFFSET support */;
274 return 0;
275 case I915_PARAM_SUBSLICE_TOTAL:
276 *gp->value = 0;
277 for (uint32_t s = 0; s < i915.devinfo.num_slices; s++)
278 *gp->value += i915.devinfo.num_subslices[s];
279 return 0;
280 case I915_PARAM_EU_TOTAL:
281 *gp->value = 0;
282 for (uint32_t s = 0; s < i915.devinfo.num_slices; s++)
283 *gp->value += i915.devinfo.num_subslices[s] * i915.devinfo.max_eus_per_subslice;
284 return 0;
285 case I915_PARAM_PERF_REVISION:
286 *gp->value = 3;
287 return 0;
288 case I915_PARAM_HAS_USERPTR_PROBE:
289 *gp->value = 0;
290 return 0;
291 default:
292 break;
293 }
294
295 fprintf(stderr, "Unknown DRM_IOCTL_I915_GET_PARAM %d\n", gp->param);
296 return -1;
297 }
298
299 static int
query_write_topology(struct drm_i915_query_item * item)300 query_write_topology(struct drm_i915_query_item *item)
301 {
302 struct drm_i915_query_topology_info *info =
303 (void *) (uintptr_t) item->data_ptr;
304 int32_t length =
305 sizeof(*info) +
306 DIV_ROUND_UP(i915.devinfo.num_slices, 8) +
307 i915.devinfo.num_slices * DIV_ROUND_UP(i915.devinfo.num_subslices[0], 8) +
308 i915.devinfo.num_slices * i915.devinfo.num_subslices[0] *
309 DIV_ROUND_UP(i915.devinfo.max_eus_per_subslice, 8);
310
311 if (item->length == 0) {
312 item->length = length;
313 return 0;
314 }
315
316 if (item->length < length) {
317 fprintf(stderr, "size too small\n");
318 return -EINVAL;
319 }
320
321 if (info->flags) {
322 fprintf(stderr, "invalid topology flags\n");
323 return -EINVAL;
324 }
325
326 info->max_slices = i915.devinfo.num_slices;
327 info->max_subslices = i915.devinfo.num_subslices[0];
328 info->max_eus_per_subslice = i915.devinfo.max_eus_per_subslice;
329
330 info->subslice_offset = DIV_ROUND_UP(i915.devinfo.num_slices, 8);
331 info->subslice_stride = DIV_ROUND_UP(i915.devinfo.num_subslices[0], 8);
332 info->eu_offset = info->subslice_offset + info->max_slices * info->subslice_stride;
333 info->eu_stride = DIV_ROUND_UP(info->max_eus_per_subslice, 8);
334
335 uint32_t slice_mask = (1u << i915.devinfo.num_slices) - 1;
336 for (uint32_t i = 0; i < info->subslice_offset; i++)
337 info->data[i] = (slice_mask >> (8 * i)) & 0xff;
338
339 for (uint32_t s = 0; s < i915.devinfo.num_slices; s++) {
340 uint32_t subslice_mask = (1u << i915.devinfo.num_subslices[s]) - 1;
341 for (uint32_t i = 0; i < info->subslice_stride; i++) {
342 info->data[info->subslice_offset + s * info->subslice_stride + i] =
343 (subslice_mask >> (8 * i)) & 0xff;
344 }
345 }
346
347 for (uint32_t s = 0; s < i915.devinfo.num_slices; s++) {
348 for (uint32_t ss = 0; ss < i915.devinfo.num_subslices[s]; ss++) {
349 uint32_t eu_mask = (1u << info->max_eus_per_subslice) - 1;
350 for (uint32_t i = 0; i < DIV_ROUND_UP(info->max_eus_per_subslice, 8); i++) {
351 info->data[info->eu_offset +
352 (s * info->max_subslices + ss) * DIV_ROUND_UP(info->max_eus_per_subslice, 8) + i] =
353 (eu_mask >> (8 * i)) & 0xff;
354 }
355 }
356 }
357
358 return 0;
359 }
360
361 static int
i915_ioctl_query(int fd,unsigned long request,void * arg)362 i915_ioctl_query(int fd, unsigned long request, void *arg)
363 {
364 struct drm_i915_query *query = arg;
365 struct drm_i915_query_item *items = (void *) (uintptr_t) query->items_ptr;
366
367 if (query->flags) {
368 fprintf(stderr, "invalid query flags\n");
369 return -EINVAL;
370 }
371
372 for (uint32_t i = 0; i < query->num_items; i++) {
373 struct drm_i915_query_item *item = &items[i];
374
375 switch (item->query_id) {
376 case DRM_I915_QUERY_TOPOLOGY_INFO:
377 case DRM_I915_QUERY_GEOMETRY_SUBSLICES: {
378 int ret = query_write_topology(item);
379 if (ret)
380 item->length = ret;
381 break;
382 }
383
384 case DRM_I915_QUERY_ENGINE_INFO: {
385 uint32_t num_copy = 1;
386 uint32_t num_render = 1;
387 uint32_t num_engines = num_copy + num_render;
388
389 struct drm_i915_query_engine_info *info =
390 (struct drm_i915_query_engine_info*)(uintptr_t)item->data_ptr;
391
392 int32_t data_length =
393 sizeof(*info) +
394 num_engines * sizeof(info->engines[0]);
395
396 if (item->length == 0) {
397 item->length = data_length;
398 return 0;
399 } else if (item->length < data_length) {
400 item->length = -EINVAL;
401 return -1;
402 } else {
403 memset(info, 0, data_length);
404
405 for (uint32_t e = 0; e < num_render; e++, info->num_engines++) {
406 info->engines[info->num_engines].engine.engine_class =
407 INTEL_ENGINE_CLASS_RENDER;
408 info->engines[info->num_engines].engine.engine_instance = e;
409 }
410
411 for (uint32_t e = 0; e < num_copy; e++, info->num_engines++) {
412 info->engines[info->num_engines].engine.engine_class =
413 INTEL_ENGINE_CLASS_COPY;
414 info->engines[info->num_engines].engine.engine_instance = e;
415 }
416
417 assert(info->num_engines == num_engines);
418
419 if (item->length > data_length)
420 item->length = data_length;
421
422 return 0;
423 }
424 }
425
426 case DRM_I915_QUERY_PERF_CONFIG:
427 /* This is known but not supported by the shim. Handling this here
428 * suppresses some spurious warning messages in shader-db runs.
429 */
430 item->length = -EINVAL;
431 break;
432
433 case DRM_I915_QUERY_MEMORY_REGIONS: {
434 uint32_t num_regions = i915.devinfo.has_local_mem ? 2 : 1;
435 struct drm_i915_query_memory_regions *info =
436 (struct drm_i915_query_memory_regions*)(uintptr_t)item->data_ptr;
437 size_t data_length = sizeof(struct drm_i915_query_memory_regions) +
438 num_regions * sizeof(struct drm_i915_memory_region_info);
439
440 if (item->length == 0) {
441 item->length = data_length;
442 return 0;
443 } else if (item->length < (int32_t)data_length) {
444 item->length = -EINVAL;
445 return -1;
446 } else {
447 memset(info, 0, data_length);
448 info->num_regions = num_regions;
449 info->regions[0].region.memory_class = I915_MEMORY_CLASS_SYSTEM;
450 info->regions[0].region.memory_instance = 0;
451 /* Report 4Gb even if it's not actually true, it looks more like a
452 * real device.
453 */
454 info->regions[0].probed_size = 4ull * 1024 * 1024 * 1024;
455 info->regions[0].unallocated_size = -1ll;
456 if (i915.devinfo.has_local_mem) {
457 info->regions[1].region.memory_class = I915_MEMORY_CLASS_DEVICE;
458 info->regions[1].region.memory_instance = 0;
459 info->regions[1].probed_size = 4ull * 1024 * 1024 * 1024;
460 info->regions[1].unallocated_size = -1ll;
461 }
462 return 0;
463 }
464 break;
465 }
466
467 default:
468 fprintf(stderr, "Unknown drm_i915_query_item id=%lli\n", item->query_id);
469 item->length = -EINVAL;
470 break;
471 }
472 }
473
474 return 0;
475 }
476
477 static int
i915_gem_get_aperture(int fd,unsigned long request,void * arg)478 i915_gem_get_aperture(int fd, unsigned long request, void *arg)
479 {
480 struct drm_i915_gem_get_aperture *aperture = arg;
481
482 if (i915.devinfo.ver >= 8 &&
483 i915.devinfo.platform != INTEL_PLATFORM_CHV) {
484 aperture->aper_size = 1ull << 48;
485 aperture->aper_available_size = 1ull << 48;
486 } else {
487 aperture->aper_size = 1ull << 31;
488 aperture->aper_size = 1ull << 31;
489 }
490
491 return 0;
492 }
493
494 /* Provide a binary blob of struct intel_device_info to the caller
495 *
496 * This is used in conjunction with INTEL_STUB_GPU_JSON to initialize a
497 * stubbed driver with device info from a file.
498 */
499 static int
i915_ioctl_load_device_info(int fd,unsigned long request,void * arg)500 i915_ioctl_load_device_info(int fd, unsigned long request, void *arg)
501 {
502 if(!i915_device_from_json)
503 return -1;
504
505 struct drm_intel_stub_devinfo *stub_arg = (struct drm_intel_stub_devinfo*) arg;
506 struct intel_device_info *stub_info = (struct intel_device_info*) stub_arg->addr;
507
508 if (stub_arg->size != sizeof(i915.devinfo)) {
509 assert(false);
510 return -1;
511 }
512 memcpy(stub_info, &i915.devinfo, sizeof(i915.devinfo));
513 return 0;
514 }
515
516 #define DRM_I915_LAST (DRM_COMMAND_END - DRM_COMMAND_BASE - 1)
517 #define DRM_I915_LOAD_STUB_DEVINFO DRM_I915_LAST
518
519 static ioctl_fn_t driver_ioctls[] = {
520 [DRM_I915_GETPARAM] = i915_ioctl_get_param,
521 [DRM_I915_QUERY] = i915_ioctl_query,
522
523 [DRM_I915_GET_RESET_STATS] = i915_ioctl_noop,
524
525 [DRM_I915_GEM_CREATE] = i915_ioctl_gem_create,
526 [DRM_I915_GEM_CREATE_EXT] = i915_ioctl_gem_create_ext,
527 [DRM_I915_GEM_MMAP] = i915_ioctl_gem_mmap,
528 [DRM_I915_GEM_MMAP_GTT] = i915_ioctl_gem_mmap_offset,
529 [DRM_I915_GEM_SET_TILING] = i915_ioctl_gem_set_tiling,
530 [DRM_I915_GEM_CONTEXT_CREATE] = i915_ioctl_gem_context_create,
531 [DRM_I915_GEM_CONTEXT_DESTROY] = i915_ioctl_noop,
532 [DRM_I915_GEM_CONTEXT_GETPARAM] = i915_ioctl_gem_context_getparam,
533 [DRM_I915_GEM_CONTEXT_SETPARAM] = i915_ioctl_noop,
534 [DRM_I915_GEM_EXECBUFFER2] = i915_ioctl_noop,
535 /* [DRM_I915_GEM_EXECBUFFER2_WR] = i915_ioctl_noop,
536 same value as DRM_I915_GEM_EXECBUFFER2. */
537
538 [DRM_I915_GEM_USERPTR] = i915_ioctl_gem_userptr,
539
540 [DRM_I915_GEM_GET_APERTURE] = i915_gem_get_aperture,
541
542 [DRM_I915_REG_READ] = i915_ioctl_noop,
543
544 [DRM_I915_GEM_SET_DOMAIN] = i915_ioctl_noop,
545 [DRM_I915_GEM_GET_CACHING] = i915_ioctl_noop,
546 [DRM_I915_GEM_SET_CACHING] = i915_ioctl_noop,
547 [DRM_I915_GEM_GET_TILING] = i915_ioctl_gem_get_tiling,
548 [DRM_I915_GEM_MADVISE] = i915_ioctl_noop,
549 [DRM_I915_GEM_WAIT] = i915_ioctl_noop,
550 [DRM_I915_GEM_BUSY] = i915_ioctl_noop,
551 [DRM_I915_LOAD_STUB_DEVINFO] = i915_ioctl_load_device_info,
552 };
553
554 void
drm_shim_driver_init(void)555 drm_shim_driver_init(void)
556 {
557 i915.device_id = 0;
558 const char *json_dev_str = getenv("INTEL_STUB_GPU_JSON");
559 if (json_dev_str != NULL) {
560 if (!intel_device_info_from_json(json_dev_str, &i915.devinfo))
561 return;
562 i915.device_id = i915.devinfo.pci_device_id;
563 i915_device_from_json = true;
564 } else {
565 const char *device_id_str = getenv("INTEL_STUB_GPU_DEVICE_ID");
566 if (device_id_str != NULL) {
567 /* Set as 0 if strtoul fails */
568 i915.device_id = strtoul(device_id_str, NULL, 16);
569 }
570 if (i915.device_id == 0) {
571 const char *user_platform = getenv("INTEL_STUB_GPU_PLATFORM");
572 /* Use SKL if nothing is specified. */
573 i915.device_id = intel_device_name_to_pci_device_id(user_platform ?: "skl");
574 }
575 if (!intel_get_device_info_from_pci_id(i915.device_id, &i915.devinfo))
576 return;
577 }
578
579 shim_device.bus_type = DRM_BUS_PCI;
580 shim_device.driver_name = "i915";
581 shim_device.driver_ioctls = driver_ioctls;
582 shim_device.driver_ioctl_count = ARRAY_SIZE(driver_ioctls);
583
584 char uevent_content[1024];
585 snprintf(uevent_content, sizeof(uevent_content),
586 "DRIVER=i915\n"
587 "PCI_CLASS=30000\n"
588 "PCI_ID=8086:%x\n"
589 "PCI_SUBSYS_ID=1028:075B\n"
590 "PCI_SLOT_NAME=0000:00:02.0\n"
591 "MODALIAS=pci:v00008086d00005916sv00001028sd0000075Bbc03sc00i00\n",
592 i915.device_id);
593 drm_shim_override_file(uevent_content,
594 "/sys/dev/char/%d:%d/device/uevent",
595 DRM_MAJOR, render_node_minor);
596 drm_shim_override_file("0x0\n",
597 "/sys/dev/char/%d:%d/device/revision",
598 DRM_MAJOR, render_node_minor);
599 char device_content[10];
600 snprintf(device_content, sizeof(device_content),
601 "0x%x\n", i915.device_id);
602 drm_shim_override_file("0x8086",
603 "/sys/dev/char/%d:%d/device/vendor",
604 DRM_MAJOR, render_node_minor);
605 drm_shim_override_file("0x8086",
606 "/sys/devices/pci0000:00/0000:00:02.0/vendor");
607 drm_shim_override_file(device_content,
608 "/sys/dev/char/%d:%d/device/device",
609 DRM_MAJOR, render_node_minor);
610 drm_shim_override_file(device_content,
611 "/sys/devices/pci0000:00/0000:00:02.0/device");
612 drm_shim_override_file("0x1234",
613 "/sys/dev/char/%d:%d/device/subsystem_vendor",
614 DRM_MAJOR, render_node_minor);
615 drm_shim_override_file("0x1234",
616 "/sys/devices/pci0000:00/0000:00:02.0/subsystem_vendor");
617 drm_shim_override_file("0x1234",
618 "/sys/dev/char/%d:%d/device/subsystem_device",
619 DRM_MAJOR, render_node_minor);
620 drm_shim_override_file("0x1234",
621 "/sys/devices/pci0000:00/0000:00:02.0/subsystem_device");
622 }
623