1 /*
2 * Copyright 2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "isl_gfx8.h"
25 #include "isl_priv.h"
26
27 bool
isl_gfx8_choose_msaa_layout(const struct isl_device * dev,const struct isl_surf_init_info * info,enum isl_tiling tiling,enum isl_msaa_layout * msaa_layout)28 isl_gfx8_choose_msaa_layout(const struct isl_device *dev,
29 const struct isl_surf_init_info *info,
30 enum isl_tiling tiling,
31 enum isl_msaa_layout *msaa_layout)
32 {
33 bool require_array = false;
34 bool require_interleaved = false;
35
36 assert(info->samples >= 1);
37
38 if (info->samples == 1) {
39 *msaa_layout = ISL_MSAA_LAYOUT_NONE;
40 return true;
41 }
42
43 /* From the Broadwell PRM >> Volume2d: Command Structures >>
44 * RENDER_SURFACE_STATE Multisampled Surface Storage Format:
45 *
46 * All multisampled render target surfaces must have this field set to
47 * MSFMT_MSS
48 */
49 if (info->usage & ISL_SURF_USAGE_RENDER_TARGET_BIT)
50 require_array = true;
51
52 /* From the Broadwell PRM >> Volume2d: Command Structures >>
53 * RENDER_SURFACE_STATE Number of Multisamples:
54 *
55 * - If this field is any value other than MULTISAMPLECOUNT_1, the
56 * Surface Type must be SURFTYPE_2D This field must be set to
57 * MULTISAMPLECOUNT_1 unless the surface is a Sampling Engine surface
58 * or Render Target surface.
59 *
60 * - If this field is any value other than MULTISAMPLECOUNT_1, Surface
61 * Min LOD, Mip Count / LOD, and Resource Min LOD must be set to zero.
62 */
63 if (info->dim != ISL_SURF_DIM_2D)
64 return notify_failure(info, "msaa only supported on 2D surfaces");
65 if (info->levels > 1)
66 return notify_failure(info, "msaa not supported with LOD > 1");
67
68 /* More obvious restrictions */
69 assert(!isl_surf_usage_is_display(info->usage));
70 assert(tiling != ISL_TILING_LINEAR);
71
72 if (!isl_format_supports_multisampling(dev->info, info->format))
73 return notify_failure(info, "format does not support msaa");
74
75 if (isl_surf_usage_is_depth_or_stencil(info->usage) ||
76 (info->usage & ISL_SURF_USAGE_HIZ_BIT))
77 require_interleaved = true;
78
79 if (require_array && require_interleaved)
80 return notify_failure(info, "cannot require array & interleaved msaa layouts");
81
82 if (require_interleaved) {
83 *msaa_layout = ISL_MSAA_LAYOUT_INTERLEAVED;
84 return true;
85 }
86
87 *msaa_layout = ISL_MSAA_LAYOUT_ARRAY;
88 return true;
89 }
90
91 void
isl_gfx8_choose_image_alignment_el(const struct isl_device * dev,const struct isl_surf_init_info * restrict info,enum isl_tiling tiling,enum isl_dim_layout dim_layout,enum isl_msaa_layout msaa_layout,struct isl_extent3d * image_align_el)92 isl_gfx8_choose_image_alignment_el(const struct isl_device *dev,
93 const struct isl_surf_init_info *restrict info,
94 enum isl_tiling tiling,
95 enum isl_dim_layout dim_layout,
96 enum isl_msaa_layout msaa_layout,
97 struct isl_extent3d *image_align_el)
98 {
99 /* Handled by isl_choose_image_alignment_el */
100 assert(info->format != ISL_FORMAT_HIZ);
101
102 assert(!isl_tiling_is_std_y(tiling));
103
104 const struct isl_format_layout *fmtl = isl_format_get_layout(info->format);
105 if (fmtl->txc == ISL_TXC_CCS) {
106 /*
107 * Broadwell PRM Vol 7, "MCS Buffer for Render Target(s)" (p. 676):
108 *
109 * "Mip-mapped and arrayed surfaces are supported with MCS buffer
110 * layout with these alignments in the RT space: Horizontal
111 * Alignment = 256 and Vertical Alignment = 128.
112 */
113 *image_align_el = isl_extent3d(256 / fmtl->bw, 128 / fmtl->bh, 1);
114 return;
115 }
116
117 /* From the Broadwell PRM, Volume 4, "Memory Views" p. 186, the alignment
118 * parameters are summarized in the following table:
119 *
120 * Surface Defined By | Surface Format | Align Width | Align Height
121 * --------------------+-----------------+-------------+--------------
122 * DEPTH_BUFFER | D16_UNORM | 8 | 4
123 * | other | 4 | 4
124 * --------------------+-----------------+-------------+--------------
125 * STENCIL_BUFFER | N/A | 8 | 8
126 * --------------------+-----------------+-------------+--------------
127 * SURFACE_STATE | BC*, ETC*, EAC* | 4 | 4
128 * | FXT1 | 8 | 4
129 * | all others | HALIGN | VALIGN
130 * -------------------------------------------------------------------
131 */
132 if (isl_surf_usage_is_depth(info->usage)) {
133 *image_align_el = info->format == ISL_FORMAT_R16_UNORM ?
134 isl_extent3d(8, 4, 1) : isl_extent3d(4, 4, 1);
135 return;
136 } else if (isl_surf_usage_is_stencil(info->usage)) {
137 *image_align_el = isl_extent3d(8, 8, 1);
138 return;
139 } else if (isl_format_is_compressed(info->format)) {
140 /* Compressed formats all have alignment equal to block size. */
141 *image_align_el = isl_extent3d(1, 1, 1);
142 return;
143 }
144
145 /* For all other formats, the alignment is determined by the horizontal and
146 * vertical alignment fields of RENDER_SURFACE_STATE. There are a few
147 * restrictions, but we generally have a choice.
148 */
149
150 /* Vertical alignment is unrestricted so we choose the smallest allowed
151 * alignment because that will use the least memory
152 */
153 const uint32_t valign = 4;
154
155 /* XXX(chadv): I believe the hardware requires each image to be
156 * cache-aligned. If that's true, then defaulting to halign=4 is wrong for
157 * many formats. Depending on the format's block size, we may need to
158 * increase halign to 8.
159 */
160 uint32_t halign = 4;
161
162 if (!(info->usage & ISL_SURF_USAGE_DISABLE_AUX_BIT)) {
163 /* From the Broadwell PRM, Volume 2d "Command Reference: Structures",
164 * RENDER_SURFACE_STATE Surface Horizontal Alignment, p326:
165 *
166 * - When Auxiliary Surface Mode is set to AUX_CCS_D or AUX_CCS_E,
167 * HALIGN 16 must be used.
168 *
169 * This case handles color surfaces that may own an auxiliary MCS, CCS_D,
170 * or CCS_E. Depth buffers, including those that own an auxiliary HiZ
171 * surface, are handled above and do not require HALIGN_16.
172 */
173 assert(halign <= 16);
174 halign = 16;
175 }
176
177 if (ISL_GFX_VER(dev) >= 11 && isl_tiling_is_any_y(tiling) &&
178 fmtl->bpb == 32 && info->samples == 1) {
179 /* GEN_BUG_1406667188: Pixel Corruption in subspan combining (8x4
180 * combining) scenarios if halign=4.
181 *
182 * See RENDER_SURFACE_STATE in Ice Lake h/w spec:
183 *
184 * "For surface format = 32 bpp, num_multisamples = 1 , MIpcount > 0
185 * and surface walk = TiledY, HALIGN must be programmed to 8"
186 */
187 halign = MAX(halign, 8);
188 }
189
190 *image_align_el = isl_extent3d(halign, valign, 1);
191 }
192