1 /*
2 * Copyright (c) 2024 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "dev/intel_debug.h"
25 #include "isl_gfx20.h"
26 #include "isl_priv.h"
27
28 /**
29 * @brief Filter out tiling flags that are incompatible with the surface.
30 *
31 * The resultant outgoing @a flags is a subset of the incoming @a flags. The
32 * outgoing flags may be empty (0x0) if the incoming flags were too
33 * restrictive.
34 *
35 * For example, if the surface will be used for a display
36 * (ISL_SURF_USAGE_DISPLAY_BIT), then this function filters out all tiling
37 * flags except ISL_TILING_4_BIT, ISL_TILING_X_BIT, and ISL_TILING_LINEAR_BIT.
38 */
39 void
isl_gfx20_filter_tiling(const struct isl_device * dev,const struct isl_surf_init_info * restrict info,isl_tiling_flags_t * flags)40 isl_gfx20_filter_tiling(const struct isl_device *dev,
41 const struct isl_surf_init_info *restrict info,
42 isl_tiling_flags_t *flags)
43 {
44 /* Clear flags unsupported on this hardware */
45 assert(ISL_GFX_VERX10(dev) >= 200);
46
47 *flags &= ISL_TILING_LINEAR_BIT |
48 ISL_TILING_X_BIT |
49 ISL_TILING_4_BIT |
50 ISL_TILING_64_XE2_BIT;
51
52 if (isl_surf_usage_is_depth_or_stencil(info->usage)) {
53 *flags &= ISL_TILING_4_BIT | ISL_TILING_64_XE2_BIT;
54
55 /* We choose to avoid Tile64 for 3D depth/stencil buffers. The swizzle
56 * for Tile64 is dependent on the image dimension. So, reads and writes
57 * should specify the same dimension to consistently interpret the data.
58 * This is not possible for 3D depth/stencil buffers however. Such
59 * buffers can be sampled from with a 3D view, but rendering is only
60 * possible with a 2D view due to the limitations of
61 * 3DSTATE_(DEPTH|STENCIL)_BUFFER.
62 */
63 if (info->dim == ISL_SURF_DIM_3D)
64 *flags &= ~ISL_TILING_64_XE2_BIT;
65 }
66
67 if (info->usage & ISL_SURF_USAGE_DISPLAY_BIT)
68 *flags &= ~ISL_TILING_64_XE2_BIT;
69
70 /* From RENDER_SURFACE_STATE::AuxiliarySurfaceMode,
71 *
72 * MCS tiling format is always Tile4
73 */
74 if (info->usage & ISL_SURF_USAGE_MCS_BIT)
75 *flags &= ISL_TILING_4_BIT;
76
77 /* From RENDER_SURFACE_STATE::TileMode,
78 *
79 * TILEMODE_XMAJOR is only allowed if Surface Type is SURFTYPE_2D.
80 *
81 * X-tiling is only allowed for 2D surfaces.
82 */
83 if (info->dim != ISL_SURF_DIM_2D)
84 *flags &= ~ISL_TILING_X_BIT;
85
86 /* From ATS-M PRMs, Volume 2d: Command Reference: Structures,
87 * RENDER_SURFACE_STATE:TileMode :
88 *
89 * "If Surface Type is SURFTYPE_1D this field must be TILEMODE_LINEAR,
90 * unless Sampler Legacy 1D Map Layout Disable is set to 0, in which
91 * case TILEMODE_YMAJOR is also allowed. Horizontal Alignment must be
92 * programmed for the required alignment between MIPs. MIP tails are
93 * not supported."
94 *
95 * Tile4 is the replacement for TileY0 on ACM.
96 */
97 if (info->dim == ISL_SURF_DIM_1D)
98 *flags &= ISL_TILING_LINEAR_BIT | ISL_TILING_4_BIT;
99
100 /* TILE64 does not work with YCRCB formats, according to bspec 58767:
101 * "Packed YUV surface formats such as YCRCB_NORMAL, YCRCB_SWAPUVY etc.
102 * will not support as Tile64"
103 */
104 if (isl_format_is_yuv(info->format))
105 *flags &= ~ISL_TILING_64_XE2_BIT;
106
107 /* Tile64 tilings for 3D have a different swizzling than a 2D surface. So
108 * filter them out if the usage wants 2D/3D compatibility.
109 */
110 if (info->usage & ISL_SURF_USAGE_2D_3D_COMPATIBLE_BIT)
111 *flags &= ~ISL_TILING_64_XE2_BIT;
112
113 /* From RENDER_SURFACE_STATE::NumberofMultisamples,
114 *
115 * This field must not be programmed to anything other than
116 * [MULTISAMPLECOUNT_1] unless the Tile Mode field is programmed to
117 * Tile64.
118 *
119 * Tile64 is required for multisampling.
120 */
121 if (info->samples > 1)
122 *flags &= ISL_TILING_64_XE2_BIT;
123
124 /* Tile64 is not defined for format sizes that are 24, 48, and 96 bpb. */
125 if (isl_format_get_layout(info->format)->bpb % 3 == 0)
126 *flags &= ~ISL_TILING_64_XE2_BIT;
127
128 /* From 3DSTATE_CPSIZE_CONTROL_BUFFER::TiledMode,
129 *
130 * - 3h Tile4 4KB tile mode
131 * - 1h Tile64 64KB tile mode
132 * - 2h, 0h Reserved
133 *
134 * Tile4 and Tile64 are the only two valid values.
135 */
136 if (info->usage & ISL_SURF_USAGE_CPB_BIT)
137 *flags &= ISL_TILING_4_BIT | ISL_TILING_64_XE2_BIT;
138 }
139
140 void
isl_gfx20_choose_image_alignment_el(const struct isl_device * dev,const struct isl_surf_init_info * restrict info,const struct isl_tile_info * tile_info,enum isl_dim_layout dim_layout,enum isl_msaa_layout msaa_layout,struct isl_extent3d * image_align_el)141 isl_gfx20_choose_image_alignment_el(const struct isl_device *dev,
142 const struct isl_surf_init_info *restrict info,
143 const struct isl_tile_info *tile_info,
144 enum isl_dim_layout dim_layout,
145 enum isl_msaa_layout msaa_layout,
146 struct isl_extent3d *image_align_el)
147 {
148 enum isl_tiling tiling = tile_info->tiling;
149
150 /* Handled by isl_choose_image_alignment_el */
151 assert(info->format != ISL_FORMAT_GFX125_HIZ);
152
153 const struct isl_format_layout *fmtl = isl_format_get_layout(info->format);
154
155 if (tiling == ISL_TILING_64_XE2) {
156 /* From RENDER_SURFACE_STATE::SurfaceHorizontalAlignment,
157 *
158 * This field is ignored for Tile64 surface formats because horizontal
159 * alignment is always to the start of the next tile in that case.
160 *
161 * From RENDER_SURFACE_STATE::SurfaceQPitch,
162 *
163 * Because MSAA is only supported for Tile64, QPitch must also be
164 * programmed to an aligned tile boundary for MSAA surfaces.
165 *
166 * Images in this surface must be tile-aligned. The table on the Bspec
167 * page, "2D/CUBE Alignment Requirement", shows that the vertical
168 * alignment is also a tile height for non-MSAA as well.
169 */
170 *image_align_el = isl_extent3d(tile_info->logical_extent_el.w,
171 tile_info->logical_extent_el.h,
172 1);
173 } else if (isl_surf_usage_is_depth(info->usage)) {
174 /* From RENDER_SURFACE_STATE::SurfaceHorizontalAlignment,
175 *
176 * - 16b Depth Surfaces Must Be HALIGN=16Bytes (8texels)
177 * - 32b Depth Surfaces Must Be HALIGN=32Bytes (8texels)
178 *
179 * From RENDER_SURFACE_STATE::SurfaceVerticalAlignment,
180 *
181 * This field is intended to be set to VALIGN_4 if the surface
182 * was rendered as a depth buffer [...]
183 *
184 * and
185 *
186 * This field should also be set to VALIGN_8 if the surface was
187 * rendered as a D16_UNORM depth buffer [...]
188 */
189 *image_align_el =
190 info->format != ISL_FORMAT_R16_UNORM ?
191 isl_extent3d(8, 4, 1) :
192 isl_extent3d(8, 8, 1);
193 } else if (isl_surf_usage_is_stencil(info->usage) ||
194 isl_surf_usage_is_cpb(info->usage)) {
195 /* From RENDER_SURFACE_STATE::SurfaceHorizontalAlignment,
196 *
197 * - Stencil Surfaces (8b) Must be HALIGN=16Bytes (16texels)
198 *
199 * From RENDER_SURFACE_STATE::SurfaceVerticalAlignment,
200 *
201 * This field is intended to be set to VALIGN_8 only if
202 * the surface was rendered as a stencil buffer, since stencil buffer
203 * surfaces support only alignment of 8.
204 *
205 * TODO: Cite docs for CPB.
206 */
207 *image_align_el = isl_extent3d(16, 8, 1);
208 } else if (!isl_is_pow2(fmtl->bpb)) {
209 /* From RENDER_SURFACE_STATE::SurfaceHorizontalAlignment,
210 *
211 * - Linear Surfaces surfaces must use HALIGN=128, including 1D which
212 * is always Linear. For 24,48 and 96bpp this means 128texels.
213 * - Tiled 24bpp, 48bpp and 96bpp surfaces must use HALIGN=16
214 */
215 *image_align_el = tiling == ISL_TILING_LINEAR ?
216 isl_extent3d(128, 4, 1) :
217 isl_extent3d(16, 4, 1);
218 } else if (_isl_surf_info_supports_ccs(dev, info->format, info->usage) ||
219 tiling == ISL_TILING_LINEAR) {
220 /* From RENDER_SURFACE_STATE::SurfaceHorizontalAlignment,
221 *
222 * - Losslessly Compressed Surfaces Must be HALIGN=128 for all
223 * supported Bpp, if other restriction are not applied
224 * - Linear Surfaces surfaces must use HALIGN=128, including 1D which
225 * is always Linear.
226 */
227 *image_align_el = isl_extent3d(128 * 8 / fmtl->bpb, 4, 1);
228
229 /* WA_22018390030:
230 *
231 * Don't choose VALIGN_4 on Xe2 for color, non-volumetric, Tile4 surfaces
232 * which can be fast cleared. We choose the next smallest option instead,
233 * VALIGN_8.
234 */
235 if (!INTEL_DEBUG(DEBUG_NO_FAST_CLEAR) &&
236 intel_needs_workaround(dev->info, 22018390030) &&
237 tiling == ISL_TILING_4 &&
238 info->dim != ISL_SURF_DIM_3D) {
239 image_align_el->h = 8;
240 }
241 } else if (fmtl->bpb >= 64) {
242 assert(fmtl->bpb == 64 || fmtl->bpb == 128);
243 /* From RENDER_SURFACE_STATE::SurfaceHorizontalAlignment,
244 *
245 * - 64bpe and 128bpe Surfaces Must Be HALIGN=64Bytes or 128Bytes (4,
246 * 8 texels or 16 texels)
247 *
248 * HALIGN=128 is used for losslessly compressed or linear surfaces. For
249 * other surface types, pick the smaller alignment of HALIGN=64 to save
250 * space.
251 */
252 *image_align_el = isl_extent3d(64 * 8 / fmtl->bpb, 4, 1);
253 } else {
254 /* From RENDER_SURFACE_STATE::SurfaceHorizontalAlignment,
255 *
256 * HALIGN=16Bytes(8 texels) is allowed only for 16b Depth, Stencil
257 * Surfaces (8b) and Tiled 24bpp, 48bpp and 96bpp surfaces
258 *
259 * HALIGN=16 would save the most space, but it is reserved for the cases
260 * handled earlier in this if-ladder. Choose the next smallest alignment
261 * possible, HALIGN=32.
262 */
263 *image_align_el = isl_extent3d(32 * 8 / fmtl->bpb, 4, 1);
264 }
265 }
266