1 /*
2 * Copyright 2016 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include <stdint.h>
25
26 #define __gen_address_type uint64_t
27 #define __gen_user_data void
28
29 static uint64_t
__gen_combine_address(void * data,void * loc,uint64_t addr,uint32_t delta)30 __gen_combine_address(__attribute__((unused)) void *data,
31 __attribute__((unused)) void *loc, uint64_t addr,
32 uint32_t delta)
33 {
34 return addr + delta;
35 }
36
37 #include "genxml/gen_macros.h"
38 #include "genxml/genX_pack.h"
39
40 #include "isl_priv.h"
41 #include "isl_genX_helpers.h"
42
43 static const uint32_t isl_encode_ds_surftype[] = {
44 #if GFX_VER >= 9
45 /* From the SKL PRM, "3DSTATE_DEPTH_STENCIL::SurfaceType":
46 *
47 * "If depth/stencil is enabled with 1D render target, depth/stencil
48 * surface type needs to be set to 2D surface type and height set to 1.
49 * Depth will use (legacy) TileY and stencil will use TileW. For this
50 * case only, the Surface Type of the depth buffer can be 2D while the
51 * Surface Type of the render target(s) are 1D, representing an
52 * exception to a programming note above.
53 */
54 [ISL_SURF_DIM_1D] = SURFTYPE_2D,
55 #else
56 [ISL_SURF_DIM_1D] = SURFTYPE_1D,
57 #endif
58 [ISL_SURF_DIM_2D] = SURFTYPE_2D,
59 [ISL_SURF_DIM_3D] = SURFTYPE_3D,
60 };
61
62 #if GFX_VER >= 9
63 static const uint8_t isl_encode_tiling[] = {
64 #if GFX_VERx10 >= 125
65 [ISL_TILING_4] = TILE4,
66 [ISL_TILING_64] = TILE64,
67 [ISL_TILING_64_XE2] = TILE64,
68 #else
69 [ISL_TILING_Y0] = NONE,
70 [ISL_TILING_SKL_Yf] = TILEYF,
71 [ISL_TILING_SKL_Ys] = TILEYS,
72 [ISL_TILING_ICL_Yf] = TILEYF,
73 [ISL_TILING_ICL_Ys] = TILEYS,
74 #endif
75 };
76 #endif /* GFX_VER >= 9 */
77
78 void
isl_genX(emit_depth_stencil_hiz_s)79 isl_genX(emit_depth_stencil_hiz_s)(const struct isl_device *dev, void *batch,
80 const struct isl_depth_stencil_hiz_emit_info *restrict info)
81 {
82 if (info->depth_surf && info->stencil_surf) {
83 if (!dev->info->has_hiz_and_separate_stencil) {
84 assert(info->depth_surf == info->stencil_surf);
85 assert(info->depth_address == info->stencil_address);
86 }
87 assert(info->depth_surf->dim == info->stencil_surf->dim);
88 }
89
90 if (info->depth_surf) {
91 assert((info->depth_surf->usage & ISL_SURF_USAGE_DEPTH_BIT));
92 if (info->depth_surf->dim == ISL_SURF_DIM_3D) {
93 assert(info->view->base_array_layer + info->view->array_len <=
94 info->depth_surf->logical_level0_px.depth);
95 } else {
96 assert(info->view->base_array_layer + info->view->array_len <=
97 info->depth_surf->logical_level0_px.array_len);
98 }
99 }
100
101 if (info->stencil_surf) {
102 assert((info->stencil_surf->usage & ISL_SURF_USAGE_STENCIL_BIT));
103 if (info->stencil_surf->dim == ISL_SURF_DIM_3D) {
104 assert(info->view->base_array_layer + info->view->array_len <=
105 info->stencil_surf->logical_level0_px.depth);
106 } else {
107 assert(info->view->base_array_layer + info->view->array_len <=
108 info->stencil_surf->logical_level0_px.array_len);
109 }
110 }
111
112 struct GENX(3DSTATE_DEPTH_BUFFER) db = {
113 GENX(3DSTATE_DEPTH_BUFFER_header),
114 #if GFX_VER >= 6
115 .MOCS = info->mocs,
116 #endif
117 };
118
119 if (info->depth_surf) {
120 db.SurfaceType = isl_encode_ds_surftype[info->depth_surf->dim];
121 db.SurfaceFormat = isl_surf_get_depth_format(dev, info->depth_surf);
122 db.Width = info->depth_surf->logical_level0_px.width - 1;
123 db.Height = info->depth_surf->logical_level0_px.height - 1;
124 if (db.SurfaceType == SURFTYPE_3D)
125 db.Depth = info->depth_surf->logical_level0_px.depth - 1;
126 } else if (info->stencil_surf) {
127 /* On Gfx12+ 3DSTATE_STENCIL_BUFFER has its own fields for all of
128 * this. No need to replicate it here.
129 */
130 #if GFX_VER < 12
131 db.SurfaceType = isl_encode_ds_surftype[info->stencil_surf->dim];
132 db.SurfaceFormat = D32_FLOAT;
133 db.Width = info->stencil_surf->logical_level0_px.width - 1;
134 db.Height = info->stencil_surf->logical_level0_px.height - 1;
135 if (db.SurfaceType == SURFTYPE_3D)
136 db.Depth = info->stencil_surf->logical_level0_px.depth - 1;
137 #else
138 db.SurfaceType = SURFTYPE_NULL;
139 db.SurfaceFormat = D32_FLOAT;
140 #endif
141 } else {
142 db.SurfaceType = SURFTYPE_NULL;
143 db.SurfaceFormat = D32_FLOAT;
144 }
145
146 if (info->depth_surf || info->stencil_surf) {
147 /* These are based entirely on the view */
148 db.RenderTargetViewExtent = info->view->array_len - 1;
149 db.LOD = info->view->base_level;
150 db.MinimumArrayElement = info->view->base_array_layer;
151
152 /* From the Haswell PRM docs for 3DSTATE_DEPTH_BUFFER::Depth
153 *
154 * "This field specifies the total number of levels for a volume
155 * texture or the number of array elements allowed to be accessed
156 * starting at the Minimum Array Element for arrayed surfaces. If the
157 * volume texture is MIP-mapped, this field specifies the depth of
158 * the base MIP level."
159 *
160 * For 3D surfaces, we set it to the correct depth above. For non-3D
161 * surfaces, this is the same as RenderTargetViewExtent.
162 */
163 if (db.SurfaceType != SURFTYPE_3D)
164 db.Depth = db.RenderTargetViewExtent;
165 }
166
167 if (info->depth_surf) {
168 #if GFX_VER >= 7
169 db.DepthWriteEnable = true;
170 #endif
171 assert(info->depth_address % info->depth_surf->alignment_B == 0);
172 db.SurfaceBaseAddress = info->depth_address;
173
174 #if GFX_VERx10 >= 125
175 db.TiledMode = isl_encode_tiling[info->depth_surf->tiling];
176 db.MipTailStartLOD = info->depth_surf->miptail_start_level;
177 #if GFX_VERx10 < 20
178 db.CompressionMode = isl_aux_usage_has_ccs(info->hiz_usage);
179 #endif
180 db.RenderCompressionFormat =
181 isl_get_render_compression_format(info->depth_surf->format);
182 #elif GFX_VER >= 9
183 /* Gen9+ depth is always Y-tiled but it may be Y0, Yf, or Ys. */
184 assert(isl_tiling_is_any_y(info->depth_surf->tiling));
185 db.TiledResourceMode = isl_encode_tiling[info->depth_surf->tiling];
186 db.MipTailStartLOD = info->depth_surf->miptail_start_level;
187 #elif GFX_VER >= 7
188 /* Gen7+ depth is always Y-tiled. We don't even have a bit for it */
189 #else
190 assert(info->depth_surf->tiling == ISL_TILING_Y0);
191 db.TiledSurface = true;
192 db.TileWalk = TILEWALK_YMAJOR;
193 db.MIPMapLayoutMode = MIPLAYOUT_BELOW;
194 #endif
195
196 db.SurfacePitch = info->depth_surf->row_pitch_B - 1;
197 #if GFX_VER >= 8
198 db.SurfaceQPitch =
199 isl_surf_get_array_pitch_el_rows(info->depth_surf) >> 2;
200 #endif
201
202 #if GFX_VER == 12
203 db.ControlSurfaceEnable = db.DepthBufferCompressionEnable =
204 isl_aux_usage_has_ccs(info->hiz_usage);
205 #endif
206 #if GFX_VER >= 12
207 db.NullPageCoherencyEnable = info->depth_surf->usage & ISL_SURF_USAGE_SPARSE_BIT;
208 #endif
209 }
210
211 #if GFX_VER == 5 || GFX_VER == 6
212 const bool separate_stencil =
213 info->stencil_surf && info->stencil_surf->format == ISL_FORMAT_R8_UINT;
214 if (separate_stencil || info->hiz_usage == ISL_AUX_USAGE_HIZ) {
215 assert(ISL_DEV_USE_SEPARATE_STENCIL(dev));
216 /* From the IronLake PRM, Vol 2 Part 1:
217 *
218 * 3DSTATE_DEPTH_BUFFER::Separate Stencil Buffer Enable
219 * If this field is enabled, Hierarchical Depth Buffer Enable must
220 * also be enabled.
221 *
222 * 3DSTATE_DEPTH_BUFFER::Tiled Surface
223 * When Hierarchical Depth Buffer is enabled, this bit must be set.
224 */
225 db.SeparateStencilBufferEnable = true;
226 db.HierarchicalDepthBufferEnable = true;
227 db.TiledSurface = true;
228 }
229 #endif
230
231 #if GFX_VER >= 6
232 struct GENX(3DSTATE_STENCIL_BUFFER) sb = {
233 GENX(3DSTATE_STENCIL_BUFFER_header),
234 .MOCS = info->mocs,
235 };
236 #else
237 # define sb db
238 #endif
239
240 if (info->stencil_surf) {
241 #if GFX_VER >= 7 && GFX_VER < 12
242 db.StencilWriteEnable = true;
243 #endif
244 #if GFX_VERx10 >= 125
245 #if GFX_VER < 20
246 sb.CompressionMode = isl_aux_usage_has_ccs(info->stencil_aux_usage);
247 sb.RenderCompressionFormat =
248 isl_get_render_compression_format(info->stencil_surf->format);
249 #else
250 sb.CompressionFormat =
251 isl_get_render_compression_format(info->stencil_surf->format);
252 #endif
253 #endif
254 #if GFX_VER >= 12
255 sb.TiledMode = isl_encode_tiling[info->stencil_surf->tiling];
256 sb.MipTailStartLOD = info->stencil_surf->miptail_start_level;
257 sb.StencilWriteEnable = true;
258 sb.SurfaceType = SURFTYPE_2D;
259 sb.Width = info->stencil_surf->logical_level0_px.width - 1;
260 sb.Height = info->stencil_surf->logical_level0_px.height - 1;
261 sb.Depth = sb.RenderTargetViewExtent = info->view->array_len - 1;
262 sb.SurfLOD = info->view->base_level;
263 sb.MinimumArrayElement = info->view->base_array_layer;
264 assert(info->stencil_aux_usage == ISL_AUX_USAGE_NONE ||
265 info->stencil_aux_usage == ISL_AUX_USAGE_STC_CCS);
266 #if GFX_VER < 20
267 sb.StencilCompressionEnable =
268 info->stencil_aux_usage == ISL_AUX_USAGE_STC_CCS;
269 sb.ControlSurfaceEnable = sb.StencilCompressionEnable;
270 #endif
271 #elif GFX_VERx10 >= 75
272 sb.StencilBufferEnable = true;
273 #endif
274 assert(info->stencil_address % info->stencil_surf->alignment_B == 0);
275 sb.SurfaceBaseAddress = info->stencil_address;
276 sb.SurfacePitch = info->stencil_surf->row_pitch_B - 1;
277 #if GFX_VER >= 8
278 sb.SurfaceQPitch =
279 isl_surf_get_array_pitch_el_rows(info->stencil_surf) >> 2;
280 #endif
281 #if GFX_VER >= 12
282 sb.NullPageCoherencyEnable = info->stencil_surf->usage & ISL_SURF_USAGE_SPARSE_BIT;
283 #endif
284 } else {
285 #if GFX_VER >= 12
286 sb.SurfaceType = SURFTYPE_NULL;
287
288 /* The docs seem to indicate that if surf-type is null, then we may need
289 * to match the depth-buffer value for `Depth`. It may be a
290 * documentation bug, since the other fields don't require this.
291 *
292 * TODO: Confirm documentation and remove setting of `Depth` if not
293 * required.
294 */
295 sb.Depth = db.Depth;
296 #endif
297 }
298
299 #if GFX_VER >= 6
300 struct GENX(3DSTATE_HIER_DEPTH_BUFFER) hiz = {
301 GENX(3DSTATE_HIER_DEPTH_BUFFER_header),
302 .MOCS = info->mocs,
303 };
304 #if GFX_VER < 20
305 struct GENX(3DSTATE_CLEAR_PARAMS) clear = {
306 GENX(3DSTATE_CLEAR_PARAMS_header),
307 };
308 #endif
309
310 assert(info->hiz_usage == ISL_AUX_USAGE_NONE ||
311 isl_aux_usage_has_hiz(info->hiz_usage));
312 if (isl_aux_usage_has_hiz(info->hiz_usage)) {
313 assert(GFX_VER >= 12 || info->hiz_usage == ISL_AUX_USAGE_HIZ);
314 db.HierarchicalDepthBufferEnable = true;
315
316 assert(info->hiz_address % info->hiz_surf->alignment_B == 0);
317 hiz.SurfaceBaseAddress = info->hiz_address;
318 hiz.SurfacePitch = info->hiz_surf->row_pitch_B - 1;
319
320 #if GFX_VERx10 >= 125
321 /* From 3DSTATE_HIER_DEPTH_BUFFER_BODY::TiledMode,
322 *
323 * HZ buffer only supports Tile4 mode
324 *
325 * and from Bspec 47009, "Hierarchical Depth Buffer",
326 *
327 * The format of the data in the hierarchical depth buffer is not
328 * documented here, as this surface needs only to be allocated by
329 * software.
330 *
331 * We choose to apply the second quote to the first. ISL describes HiZ
332 * with a tiling that has the same extent as Tile4 (128Bx32), but a
333 * different internal layout. This has two benefits: 1) it allows us to
334 * have the correct allocation size and 2) we can continue to use a
335 * tiling that was determined to exist on some prior platforms.
336 */
337 assert(info->hiz_surf->tiling == ISL_TILING_HIZ);
338 hiz.TiledMode = TILE4;
339 #elif GFX_VERx10 >= 120
340 /* From 3DSTATE_HIER_DEPTH_BUFFER_BODY::TiledMode,
341 *
342 * HZ buffer only supports Tile Y mode.
343 *
344 * and
345 *
346 * Value | Name
347 * ----------------------------------------
348 * 0h | No tiled resource (Tile Y Mode).
349 */
350 assert(info->hiz_surf->tiling == ISL_TILING_HIZ);
351 hiz.TiledMode = NONE;
352 #endif
353
354 #if GFX_VER >= 12
355 hiz.HierarchicalDepthBufferWriteThruEnable =
356 info->hiz_usage == ISL_AUX_USAGE_HIZ_CCS_WT;
357
358 #if GFX_VER == 12
359 /* The bspec docs up to GFX 12 for this bit are fairly unclear about
360 * exactly what is and isn't supported with HiZ write-through. It's
361 * fairly clear that you can't sample from a multisampled depth buffer
362 * with CCS. This limitation isn't called out explicitly but the docs
363 * for the CCS_E value of RENDER_SURFACE_STATE::AuxiliarySurfaceMode say:
364 *
365 * "If Number of multisamples > 1, programming this value means MSAA
366 * compression is enabled for that surface. Auxiliary surface is MSC
367 * with tile y."
368 *
369 * Since this interpretation ignores whether the surface is
370 * depth/stencil or not and since multisampled depth buffers use
371 * ISL_MSAA_LAYOUT_INTERLEAVED which is incompatible with MCS
372 * compression, this means that we can't even specify MSAA depth CCS in
373 * RENDER_SURFACE_STATE::AuxiliarySurfaceMode. The BSpec also says, for
374 * 3DSTATE_HIER_DEPTH_BUFFER::HierarchicalDepthBufferWriteThruEnable,
375 *
376 * "This bit must NOT be set for >1x MSAA modes, since sampler
377 * doesn't support sampling from >1x MSAA depth buffer."
378 *
379 * Again, this is all focused around what the sampler can do and not
380 * what the depth hardware can do.
381 *
382 * Reading even more internal docs which can't be quoted here makes it
383 * pretty clear that, even if it's not currently called out in the
384 * BSpec, HiZ+CCS write-through isn't intended to work with MSAA and we
385 * shouldn't try to use it. Treat it as if it's disallowed even if the
386 * BSpec doesn't explicitly document that.
387 */
388 if (hiz.HierarchicalDepthBufferWriteThruEnable)
389 assert(info->depth_surf->samples == 1);
390 #endif /* #if GFX_VER == 12 */
391 #endif /* #if GFX_VER >= 12 */
392
393 #if GFX_VER >= 8
394 /* From the SKL PRM Vol2a:
395 *
396 * The interpretation of this field is dependent on Surface Type
397 * as follows:
398 * - SURFTYPE_1D: distance in pixels between array slices
399 * - SURFTYPE_2D/CUBE: distance in rows between array slices
400 * - SURFTYPE_3D: distance in rows between R - slices
401 *
402 * Unfortunately, the docs aren't 100% accurate here. They fail to
403 * mention that the 1-D rule only applies to linear 1-D images.
404 * Since depth and HiZ buffers are always tiled, they are treated as
405 * 2-D images. Prior to Sky Lake, this field is always in rows.
406 */
407 hiz.SurfaceQPitch =
408 isl_surf_get_array_pitch_sa_rows(info->hiz_surf) >> 2;
409 #endif
410
411 #if GFX_VER < 20
412 clear.DepthClearValueValid = true;
413 #if GFX_VER >= 8
414 clear.DepthClearValue = info->depth_clear_value;
415 #else
416 switch (info->depth_surf->format) {
417 case ISL_FORMAT_R32_FLOAT: {
418 union { float f; uint32_t u; } fu;
419 fu.f = info->depth_clear_value;
420 clear.DepthClearValue = fu.u;
421 break;
422 }
423 case ISL_FORMAT_R24_UNORM_X8_TYPELESS:
424 clear.DepthClearValue = info->depth_clear_value * ((1u << 24) - 1);
425 break;
426 case ISL_FORMAT_R16_UNORM:
427 clear.DepthClearValue = info->depth_clear_value * ((1u << 16) - 1);
428 break;
429 default:
430 unreachable("Invalid depth type");
431 }
432 #endif
433 #endif
434 }
435 #endif /* GFX_VER >= 6 */
436
437 /* Pack everything into the batch */
438 uint32_t *dw = batch;
439 GENX(3DSTATE_DEPTH_BUFFER_pack)(NULL, dw, &db);
440 dw += GENX(3DSTATE_DEPTH_BUFFER_length);
441
442 #if GFX_VER >= 6
443 GENX(3DSTATE_STENCIL_BUFFER_pack)(NULL, dw, &sb);
444 dw += GENX(3DSTATE_STENCIL_BUFFER_length);
445
446 GENX(3DSTATE_HIER_DEPTH_BUFFER_pack)(NULL, dw, &hiz);
447 dw += GENX(3DSTATE_HIER_DEPTH_BUFFER_length);
448
449 #if GFX_VER < 20
450 GENX(3DSTATE_CLEAR_PARAMS_pack)(NULL, dw, &clear);
451 dw += GENX(3DSTATE_CLEAR_PARAMS_length);
452 #endif /* GFX_VER < 20 */
453 #endif /* GFX_VER >= 6 */
454 }
455