1 /*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include <stdlib.h>
25 #include <stdio.h>
26 #include <stdbool.h>
27 #include "util/ralloc.h"
28 #include "brw_disasm.h"
29 #include "brw_eu.h"
30
31 #include <gtest/gtest.h>
32
33 struct CompactParams {
34 unsigned verx10;
35 unsigned align;
36 };
37
38 std::string
get_compact_params_name(const testing::TestParamInfo<CompactParams> p)39 get_compact_params_name(const testing::TestParamInfo<CompactParams> p)
40 {
41 CompactParams params = p.param;
42 std::stringstream ss;
43 ss << params.verx10 << "_";
44 switch (params.align) {
45 case BRW_ALIGN_1:
46 ss << "Align_1";
47 break;
48 case BRW_ALIGN_16:
49 ss << "Align_16";
50 break;
51 default:
52 unreachable("invalid align");
53 }
54 return ss.str();
55 }
56
57 static bool
test_compact_instruction(struct brw_codegen * p,brw_inst src)58 test_compact_instruction(struct brw_codegen *p, brw_inst src)
59 {
60 brw_compact_inst dst;
61 memset(&dst, 0xd0, sizeof(dst));
62
63 if (brw_try_compact_instruction(p->isa, &dst, &src)) {
64 brw_inst uncompacted;
65
66 brw_uncompact_instruction(p->isa, &uncompacted, &dst);
67 if (memcmp(&uncompacted, &src, sizeof(src))) {
68 brw_debug_compact_uncompact(p->isa, &src, &uncompacted);
69 return false;
70 }
71 } else {
72 brw_compact_inst unchanged;
73 memset(&unchanged, 0xd0, sizeof(unchanged));
74 /* It's not supposed to change dst unless it compacted. */
75 if (memcmp(&unchanged, &dst, sizeof(dst))) {
76 fprintf(stderr, "Failed to compact, but dst changed\n");
77 fprintf(stderr, " Instruction: ");
78 brw_disassemble_inst(stderr, p->isa, &src, false, 0, NULL);
79 return false;
80 }
81 }
82
83 return true;
84 }
85
86 /**
87 * When doing fuzz testing, pad bits won't round-trip.
88 *
89 * This sort of a superset of skip_bit, which is testing for changing bits that
90 * aren't worth testing for fuzzing. We also just want to clear bits that
91 * become meaningless once fuzzing twiddles a related bit.
92 */
93 static void
clear_pad_bits(const struct brw_isa_info * isa,brw_inst * inst)94 clear_pad_bits(const struct brw_isa_info *isa, brw_inst *inst)
95 {
96 const struct intel_device_info *devinfo = isa->devinfo;
97
98 if (brw_inst_opcode(isa, inst) != BRW_OPCODE_SEND &&
99 brw_inst_opcode(isa, inst) != BRW_OPCODE_SENDC &&
100 brw_inst_src0_reg_file(devinfo, inst) != IMM &&
101 brw_inst_src1_reg_file(devinfo, inst) != IMM) {
102 brw_inst_set_bits(inst, 127, 111, 0);
103 }
104 }
105
106 static bool
skip_bit(const struct brw_isa_info * isa,brw_inst * src,int bit)107 skip_bit(const struct brw_isa_info *isa, brw_inst *src, int bit)
108 {
109 const struct intel_device_info *devinfo = isa->devinfo;
110
111 /* pad bit */
112 if (bit == 7)
113 return true;
114
115 /* The compact bit -- uncompacted can't have it set. */
116 if (bit == 29)
117 return true;
118
119 if (is_3src(isa, brw_inst_opcode(isa, src))) {
120 if (bit == 127)
121 return true;
122 } else {
123 if (bit == 47)
124 return true;
125
126 if (bit == 11)
127 return true;
128
129 if (bit == 95)
130 return true;
131 }
132
133 /* sometimes these are pad bits. */
134 if (brw_inst_opcode(isa, src) != BRW_OPCODE_SEND &&
135 brw_inst_opcode(isa, src) != BRW_OPCODE_SENDC &&
136 brw_inst_src0_reg_file(devinfo, src) != IMM &&
137 brw_inst_src1_reg_file(devinfo, src) != IMM &&
138 bit >= 121) {
139 return true;
140 }
141
142 return false;
143 }
144
145 static bool
test_fuzz_compact_instruction(struct brw_codegen * p,brw_inst src)146 test_fuzz_compact_instruction(struct brw_codegen *p, brw_inst src)
147 {
148 for (int bit0 = 0; bit0 < 128; bit0++) {
149 if (skip_bit(p->isa, &src, bit0))
150 continue;
151
152 for (int bit1 = 0; bit1 < 128; bit1++) {
153 brw_inst instr = src;
154 uint64_t *bits = instr.data;
155
156 if (skip_bit(p->isa, &src, bit1))
157 continue;
158
159 bits[bit0 / 64] ^= (1ull << (bit0 & 63));
160 bits[bit1 / 64] ^= (1ull << (bit1 & 63));
161
162 clear_pad_bits(p->isa, &instr);
163
164 if (!brw_validate_instruction(p->isa, &instr, 0, sizeof(brw_inst), NULL))
165 continue;
166
167 if (!test_compact_instruction(p, instr)) {
168 printf(" twiddled bits for fuzzing %d, %d\n", bit0, bit1);
169 return false;
170 }
171 }
172 }
173
174 return true;
175 }
176
177 class CompactTestFixture : public testing::TestWithParam<CompactParams> {
178 protected:
SetUp()179 virtual void SetUp() {
180 CompactParams params = GetParam();
181 mem_ctx = ralloc_context(NULL);
182 devinfo = rzalloc(mem_ctx, intel_device_info);
183 p = rzalloc(mem_ctx, brw_codegen);
184
185 devinfo->verx10 = params.verx10;
186 devinfo->ver = devinfo->verx10 / 10;
187
188 brw_init_isa_info(&isa, devinfo);
189 brw_init_codegen(&isa, p, p);
190 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
191 brw_set_default_access_mode(p, params.align);
192 };
193
TearDown()194 virtual void TearDown() {
195 EXPECT_EQ(p->nr_insn, 1);
196 EXPECT_TRUE(test_compact_instruction(p, p->store[0]));
197 EXPECT_TRUE(test_fuzz_compact_instruction(p, p->store[0]));
198
199 ralloc_free(mem_ctx);
200 };
201
202 void *mem_ctx;
203 struct brw_isa_info isa;
204 intel_device_info *devinfo;
205 brw_codegen *p;
206 };
207
208 class Instructions : public CompactTestFixture {};
209
210 INSTANTIATE_TEST_SUITE_P(
211 CompactTest,
212 Instructions,
213 testing::Values(
214 CompactParams{ 90, BRW_ALIGN_1 }, CompactParams{ 90, BRW_ALIGN_16 },
215 CompactParams{ 110, BRW_ALIGN_1 },
216 CompactParams{ 120, BRW_ALIGN_1 },
217 CompactParams{ 125, BRW_ALIGN_1 }
218 ),
219 get_compact_params_name);
220
TEST_P(Instructions,ADD_GRF_GRF_GRF)221 TEST_P(Instructions, ADD_GRF_GRF_GRF)
222 {
223 struct brw_reg g0 = brw_vec8_grf(0, 0);
224 struct brw_reg g2 = brw_vec8_grf(2, 0);
225 struct brw_reg g4 = brw_vec8_grf(4, 0);
226
227 brw_ADD(p, g0, g2, g4);
228 }
229
TEST_P(Instructions,ADD_GRF_GRF_IMM)230 TEST_P(Instructions, ADD_GRF_GRF_IMM)
231 {
232 struct brw_reg g0 = brw_vec8_grf(0, 0);
233 struct brw_reg g2 = brw_vec8_grf(2, 0);
234
235 brw_ADD(p, g0, g2, brw_imm_f(1.0));
236 }
237
TEST_P(Instructions,ADD_GRF_GRF_IMM_d)238 TEST_P(Instructions, ADD_GRF_GRF_IMM_d)
239 {
240 struct brw_reg g0 = retype(brw_vec8_grf(0, 0), BRW_TYPE_D);
241 struct brw_reg g2 = retype(brw_vec8_grf(2, 0), BRW_TYPE_D);
242
243 brw_ADD(p, g0, g2, brw_imm_d(1));
244 }
245
TEST_P(Instructions,MOV_GRF_GRF)246 TEST_P(Instructions, MOV_GRF_GRF)
247 {
248 struct brw_reg g0 = brw_vec8_grf(0, 0);
249 struct brw_reg g2 = brw_vec8_grf(2, 0);
250
251 brw_MOV(p, g0, g2);
252 }
253
TEST_P(Instructions,ADD_vec1_GRF_GRF_GRF)254 TEST_P(Instructions, ADD_vec1_GRF_GRF_GRF)
255 {
256 struct brw_reg g0 = brw_vec1_grf(0, 0);
257 struct brw_reg g2 = brw_vec1_grf(2, 0);
258 struct brw_reg g4 = brw_vec1_grf(4, 0);
259
260 brw_ADD(p, g0, g2, g4);
261 }
262
TEST_P(Instructions,f0_0_MOV_GRF_GRF)263 TEST_P(Instructions, f0_0_MOV_GRF_GRF)
264 {
265 struct brw_reg g0 = brw_vec8_grf(0, 0);
266 struct brw_reg g2 = brw_vec8_grf(2, 0);
267
268 brw_push_insn_state(p);
269 brw_set_default_predicate_control(p, BRW_PREDICATE_NORMAL);
270 brw_MOV(p, g0, g2);
271 brw_pop_insn_state(p);
272 }
273
274 /* The handling of f0.1 vs f0.0 changes between gfx6 and gfx7. Explicitly test
275 * it, so that we run the fuzzing can run over all the other bits that might
276 * interact with it.
277 */
TEST_P(Instructions,f0_1_MOV_GRF_GRF)278 TEST_P(Instructions, f0_1_MOV_GRF_GRF)
279 {
280 struct brw_reg g0 = brw_vec8_grf(0, 0);
281 struct brw_reg g2 = brw_vec8_grf(2, 0);
282
283 brw_push_insn_state(p);
284 brw_set_default_predicate_control(p, BRW_PREDICATE_NORMAL);
285 brw_inst *mov = brw_MOV(p, g0, g2);
286 brw_inst_set_flag_subreg_nr(p->devinfo, mov, 1);
287 brw_pop_insn_state(p);
288 }
289