1 /* 2 * Copyright 2024 Intel Corporation 3 * SPDX-License-Identifier: MIT 4 */ 5 6 #ifndef INTEL_SHADER_ENUMS_H 7 #define INTEL_SHADER_ENUMS_H 8 9 #include <stdint.h> 10 11 #include "compiler/shader_enums.h" 12 #include "util/enum_operators.h" 13 14 #ifdef __cplusplus 15 extern "C" { 16 #endif 17 18 enum intel_msaa_flags { 19 /** Must be set whenever any dynamic MSAA is used 20 * 21 * This flag mostly exists to let us assert that the driver understands 22 * dynamic MSAA so we don't run into trouble with drivers that don't. 23 */ 24 INTEL_MSAA_FLAG_ENABLE_DYNAMIC = (1 << 0), 25 26 /** True if the framebuffer is multisampled */ 27 INTEL_MSAA_FLAG_MULTISAMPLE_FBO = (1 << 1), 28 29 /** True if this shader has been dispatched per-sample */ 30 INTEL_MSAA_FLAG_PERSAMPLE_DISPATCH = (1 << 2), 31 32 /** True if inputs should be interpolated per-sample by default */ 33 INTEL_MSAA_FLAG_PERSAMPLE_INTERP = (1 << 3), 34 35 /** True if this shader has been dispatched with alpha-to-coverage */ 36 INTEL_MSAA_FLAG_ALPHA_TO_COVERAGE = (1 << 4), 37 38 /** True if this shader has been dispatched coarse 39 * 40 * This is intentionally chose to be bit 15 to correspond to the coarse bit 41 * in the pixel interpolator messages. 42 */ 43 INTEL_MSAA_FLAG_COARSE_PI_MSG = (1 << 15), 44 45 /** True if this shader has been dispatched coarse 46 * 47 * This is intentionally chose to be bit 18 to correspond to the coarse bit 48 * in the render target messages. 49 */ 50 INTEL_MSAA_FLAG_COARSE_RT_WRITES = (1 << 18), 51 }; 52 MESA_DEFINE_CPP_ENUM_BITFIELD_OPERATORS(intel_msaa_flags) 53 54 /** 55 * @defgroup Tessellator parameter enumerations. 56 * 57 * These correspond to the hardware values in 3DSTATE_TE, and are provided 58 * as part of the tessellation evaluation shader. 59 * 60 * @{ 61 */ 62 enum intel_tess_partitioning { 63 INTEL_TESS_PARTITIONING_INTEGER = 0, 64 INTEL_TESS_PARTITIONING_ODD_FRACTIONAL = 1, 65 INTEL_TESS_PARTITIONING_EVEN_FRACTIONAL = 2, 66 }; 67 68 enum intel_tess_output_topology { 69 INTEL_TESS_OUTPUT_TOPOLOGY_POINT = 0, 70 INTEL_TESS_OUTPUT_TOPOLOGY_LINE = 1, 71 INTEL_TESS_OUTPUT_TOPOLOGY_TRI_CW = 2, 72 INTEL_TESS_OUTPUT_TOPOLOGY_TRI_CCW = 3, 73 }; 74 75 enum intel_tess_domain { 76 INTEL_TESS_DOMAIN_QUAD = 0, 77 INTEL_TESS_DOMAIN_TRI = 1, 78 INTEL_TESS_DOMAIN_ISOLINE = 2, 79 }; 80 /** @} */ 81 82 enum intel_shader_dispatch_mode { 83 INTEL_DISPATCH_MODE_4X1_SINGLE = 0, 84 INTEL_DISPATCH_MODE_4X2_DUAL_INSTANCE = 1, 85 INTEL_DISPATCH_MODE_4X2_DUAL_OBJECT = 2, 86 INTEL_DISPATCH_MODE_SIMD8 = 3, 87 88 INTEL_DISPATCH_MODE_TCS_SINGLE_PATCH = 0, 89 INTEL_DISPATCH_MODE_TCS_MULTI_PATCH = 2, 90 }; 91 92 /** 93 * Data structure recording the relationship between the gl_varying_slot enum 94 * and "slots" within the vertex URB entry (VUE). A "slot" is defined as a 95 * single octaword within the VUE (128 bits). 96 * 97 * Note that each BRW register contains 256 bits (2 octawords), so when 98 * accessing the VUE in URB_NOSWIZZLE mode, each register corresponds to two 99 * consecutive VUE slots. When accessing the VUE in URB_INTERLEAVED mode (as 100 * in a vertex shader), each register corresponds to a single VUE slot, since 101 * it contains data for two separate vertices. 102 */ 103 struct intel_vue_map { 104 /** 105 * Bitfield representing all varying slots that are (a) stored in this VUE 106 * map, and (b) actually written by the shader. Does not include any of 107 * the additional varying slots defined in brw_varying_slot. 108 */ 109 uint64_t slots_valid; 110 111 /** 112 * Is this VUE map for a separate shader pipeline? 113 * 114 * Separable programs (GL_ARB_separate_shader_objects) can be mixed and matched 115 * without the linker having a chance to dead code eliminate unused varyings. 116 * 117 * This means that we have to use a fixed slot layout, based on the output's 118 * location field, rather than assigning slots in a compact contiguous block. 119 */ 120 bool separate; 121 122 /** 123 * Map from gl_varying_slot value to VUE slot. For gl_varying_slots that are 124 * not stored in a slot (because they are not written, or because 125 * additional processing is applied before storing them in the VUE), the 126 * value is -1. 127 */ 128 signed char varying_to_slot[VARYING_SLOT_TESS_MAX]; 129 130 /** 131 * Map from VUE slot to gl_varying_slot value. For slots that do not 132 * directly correspond to a gl_varying_slot, the value comes from 133 * brw_varying_slot. 134 * 135 * For slots that are not in use, the value is BRW_VARYING_SLOT_PAD. 136 */ 137 signed char slot_to_varying[VARYING_SLOT_TESS_MAX]; 138 139 /** 140 * Total number of VUE slots in use 141 */ 142 int num_slots; 143 144 /** 145 * Number of position VUE slots. If num_pos_slots > 1, primitive 146 * replication is being used. 147 */ 148 int num_pos_slots; 149 150 /** 151 * Number of per-patch VUE slots. Only valid for tessellation control 152 * shader outputs and tessellation evaluation shader inputs. 153 */ 154 int num_per_patch_slots; 155 156 /** 157 * Number of per-vertex VUE slots. Only valid for tessellation control 158 * shader outputs and tessellation evaluation shader inputs. 159 */ 160 int num_per_vertex_slots; 161 }; 162 163 struct intel_cs_dispatch_info { 164 uint32_t group_size; 165 uint32_t simd_size; 166 uint32_t threads; 167 168 /* RightExecutionMask field used in GPGPU_WALKER. */ 169 uint32_t right_mask; 170 }; 171 172 enum PACKED intel_compute_walk_order { 173 INTEL_WALK_ORDER_XYZ = 0, 174 INTEL_WALK_ORDER_XZY = 1, 175 INTEL_WALK_ORDER_YXZ = 2, 176 INTEL_WALK_ORDER_YZX = 3, 177 INTEL_WALK_ORDER_ZXY = 4, 178 INTEL_WALK_ORDER_ZYX = 5, 179 }; 180 181 #ifdef __cplusplus 182 } /* extern "C" */ 183 #endif 184 185 #endif /* INTEL_SHADER_ENUMS_H */ 186