1 /* 2 * Copyright 2024 Intel Corporation 3 * SPDX-License-Identifier: MIT 4 */ 5 6 #include "elk_nir_options.h" 7 8 #define COMMON_OPTIONS \ 9 .compact_arrays = true, \ 10 .discard_is_demote = true, \ 11 .has_uclz = true, \ 12 .lower_fdiv = true, \ 13 .lower_scmp = true, \ 14 .lower_flrp16 = true, \ 15 .lower_fmod = true, \ 16 .lower_ufind_msb = true, \ 17 .lower_uadd_carry = true, \ 18 .lower_usub_borrow = true, \ 19 .lower_flrp64 = true, \ 20 .lower_fisnormal = true, \ 21 .lower_isign = true, \ 22 .lower_ldexp = true, \ 23 .lower_bitfield_extract = true, \ 24 .lower_bitfield_insert = true, \ 25 .lower_device_index_to_zero = true, \ 26 .vectorize_io = true, \ 27 .vectorize_tess_levels = true, \ 28 .use_interpolated_input_intrinsics = true, \ 29 .has_ddx_intrinsics = true, \ 30 .scalarize_ddx = true, \ 31 .lower_insert_byte = true, \ 32 .lower_insert_word = true, \ 33 .vertex_id_zero_based = true, \ 34 .lower_base_vertex = true, \ 35 .support_16bit_alu = true, \ 36 .lower_uniforms_to_ubo = true 37 38 #define COMMON_SCALAR_OPTIONS \ 39 .lower_to_scalar = true, \ 40 .lower_pack_half_2x16 = true, \ 41 .lower_pack_snorm_2x16 = true, \ 42 .lower_pack_snorm_4x8 = true, \ 43 .lower_pack_unorm_2x16 = true, \ 44 .lower_pack_unorm_4x8 = true, \ 45 .lower_unpack_half_2x16 = true, \ 46 .lower_unpack_snorm_2x16 = true, \ 47 .lower_unpack_snorm_4x8 = true, \ 48 .lower_unpack_unorm_2x16 = true, \ 49 .lower_unpack_unorm_4x8 = true, \ 50 .lower_hadd64 = true, \ 51 .avoid_ternary_with_two_constants = true, \ 52 .has_pack_32_4x8 = true, \ 53 .max_unroll_iterations = 32, \ 54 .force_indirect_unrolling = nir_var_function_temp, \ 55 .divergence_analysis_options = \ 56 (nir_divergence_single_patch_per_tcs_subgroup | \ 57 nir_divergence_single_patch_per_tes_subgroup | \ 58 nir_divergence_shader_record_ptr_uniform) 59 60 const struct nir_shader_compiler_options elk_scalar_nir_options = { 61 COMMON_OPTIONS, 62 COMMON_SCALAR_OPTIONS, 63 }; 64 65 const struct nir_shader_compiler_options elk_vector_nir_options = { 66 COMMON_OPTIONS, 67 68 /* In the vec4 backend, our dpN instruction replicates its result to all the 69 * components of a vec4. We would like NIR to give us replicated fdot 70 * instructions because it can optimize better for us. 71 */ 72 .fdot_replicates = true, 73 74 .lower_usub_sat = true, 75 .lower_pack_snorm_2x16 = true, 76 .lower_pack_unorm_2x16 = true, 77 .lower_unpack_snorm_2x16 = true, 78 .lower_unpack_unorm_2x16 = true, 79 .lower_extract_byte = true, 80 .lower_extract_word = true, 81 .intel_vec4 = true, 82 .max_unroll_iterations = 32, 83 }; 84