1 /*
2 * Copyright © 2014 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 /**
25 * @file elk_inst.h
26 *
27 * A representation of i965 EU assembly instructions, with helper methods to
28 * get and set various fields. This is the actual hardware format.
29 */
30
31 #ifndef ELK_INST_H
32 #define ELK_INST_H
33
34 #include <assert.h>
35 #include <stdint.h>
36
37 #include "elk_eu_defines.h"
38 #include "elk_isa_info.h"
39 #include "elk_reg_type.h"
40 #include "dev/intel_device_info.h"
41
42 #ifdef __cplusplus
43 extern "C" {
44 #endif
45
46 /* elk_context.h has a forward declaration of elk_inst, so name the struct. */
47 typedef struct elk_inst {
48 uint64_t data[2];
49 } elk_inst;
50
51 static inline uint64_t elk_inst_bits(const elk_inst *inst,
52 unsigned high, unsigned low);
53 static inline void elk_inst_set_bits(elk_inst *inst,
54 unsigned high, unsigned low,
55 uint64_t value);
56
57 #define FC(name, hi4, lo4, assertions) \
58 static inline void \
59 elk_inst_set_##name(const struct intel_device_info *devinfo, \
60 elk_inst *inst, uint64_t v) \
61 { \
62 assert(assertions); \
63 elk_inst_set_bits(inst, hi4, lo4, v); \
64 } \
65 static inline uint64_t \
66 elk_inst_##name(const struct intel_device_info *devinfo, \
67 const elk_inst *inst) \
68 { \
69 assert(assertions); \
70 return elk_inst_bits(inst, hi4, lo4); \
71 }
72
73 /* A simple macro for fields which stay in the same place on all generations. */
74 #define F(name, hi4, lo4) FC(name, hi4, lo4, true)
75
76 #define BOUNDS(hi4, lo4, hi45, lo45, hi5, lo5, hi6, lo6, \
77 hi7, lo7, hi8, lo8) \
78 unsigned high, low; \
79 if (devinfo->ver >= 8) { \
80 high = hi8; low = lo8; \
81 } else if (devinfo->ver >= 7) { \
82 high = hi7; low = lo7; \
83 } else if (devinfo->ver >= 6) { \
84 high = hi6; low = lo6; \
85 } else if (devinfo->ver >= 5) { \
86 high = hi5; low = lo5; \
87 } else if (devinfo->verx10 >= 45) { \
88 high = hi45; low = lo45; \
89 } else { \
90 high = hi4; low = lo4; \
91 } \
92 assert(((int) high) != -1 && ((int) low) != -1);
93
94 /* A general macro for cases where the field has moved to several different
95 * bit locations across generations. GCC appears to combine cases where the
96 * bits are identical, removing some of the inefficiency.
97 */
98 #define FF(name, hi4, lo4, hi45, lo45, hi5, lo5, hi6, lo6, \
99 hi7, lo7, hi8, lo8) \
100 static inline void \
101 elk_inst_set_##name(const struct intel_device_info *devinfo, \
102 elk_inst *inst, uint64_t value) \
103 { \
104 BOUNDS(hi4, lo4, hi45, lo45, hi5, lo5, hi6, lo6, \
105 hi7, lo7, hi8, lo8) \
106 elk_inst_set_bits(inst, high, low, value); \
107 } \
108 static inline uint64_t \
109 elk_inst_##name(const struct intel_device_info *devinfo, const elk_inst *inst)\
110 { \
111 BOUNDS(hi4, lo4, hi45, lo45, hi5, lo5, hi6, lo6, \
112 hi7, lo7, hi8, lo8) \
113 return elk_inst_bits(inst, high, low); \
114 }
115
116 /* A macro for fields which moved as of Gfx8+. */
117 #define F8(name, gfx4_high, gfx4_low, gfx8_high, gfx8_low) \
118 FF(name, \
119 /* 4: */ gfx4_high, gfx4_low, \
120 /* 4.5: */ gfx4_high, gfx4_low, \
121 /* 5: */ gfx4_high, gfx4_low, \
122 /* 6: */ gfx4_high, gfx4_low, \
123 /* 7: */ gfx4_high, gfx4_low, \
124 /* 8: */ gfx8_high, gfx8_low);
125
126 F(src1_vstride, /* 4+ */ 120, 117)
127 F(src1_width, /* 4+ */ 116, 114)
128 F(src1_da16_swiz_w, /* 4+ */ 115, 114)
129 F(src1_da16_swiz_z, /* 4+ */ 113, 112)
130 F(src1_hstride, /* 4+ */ 113, 112)
131 F(src1_address_mode, /* 4+ */ 111, 111)
132 /** Src1.SrcMod @{ */
133 F(src1_negate, /* 4+ */ 110, 110)
134 F(src1_abs, /* 4+ */ 109, 109)
135 /** @} */
136 F8(src1_ia_subreg_nr, /* 4+ */ 108, 106, /* 8+ */ 108, 105)
137 F(src1_da_reg_nr, /* 4+ */ 108, 101)
138 F(src1_da16_subreg_nr, /* 4+ */ 100, 100)
139 F(src1_da1_subreg_nr, /* 4+ */ 100, 96)
140 F(src1_da16_swiz_y, /* 4+ */ 99, 98)
141 F(src1_da16_swiz_x, /* 4+ */ 97, 96)
142 F8(src1_reg_hw_type, /* 4+ */ 46, 44, /* 8+ */ 94, 91)
143 F8(src1_reg_file, /* 4+ */ 43, 42, /* 8+ */ 90, 89)
144 F(src0_vstride, /* 4+ */ 88, 85)
145 F(src0_width, /* 4+ */ 84, 82)
146 F(src0_da16_swiz_w, /* 4+ */ 83, 82)
147 F(src0_da16_swiz_z, /* 4+ */ 81, 80)
148 F(src0_hstride, /* 4+ */ 81, 80)
149 F(src0_address_mode, /* 4+ */ 79, 79)
150 /** Src0.SrcMod @{ */
151 F(src0_negate, /* 4+ */ 78, 78)
152 F(src0_abs, /* 4+ */ 77, 77)
153 /** @} */
154 F8(src0_ia_subreg_nr, /* 4+ */ 76, 74, /* 8+ */ 76, 73)
155 F(src0_da_reg_nr, /* 4+ */ 76, 69)
156 F(src0_da16_subreg_nr, /* 4+ */ 68, 68)
157 F(src0_da1_subreg_nr, /* 4+ */ 68, 64)
158 F(src0_da16_swiz_y, /* 4+ */ 67, 66)
159 F(src0_da16_swiz_x, /* 4+ */ 65, 64)
160 F(dst_address_mode, /* 4+ */ 63, 63)
161 F(dst_hstride, /* 4+ */ 62, 61)
162 F8(dst_ia_subreg_nr, /* 4+ */ 60, 58, /* 8+ */ 60, 57)
163 F(dst_da_reg_nr, /* 4+ */ 60, 53)
164 F(dst_da16_subreg_nr, /* 4+ */ 52, 52)
165 F(dst_da1_subreg_nr, /* 4+ */ 52, 48)
166 F(da16_writemask, /* 4+ */ 51, 48) /* Dst.ChanEn */
167 F8(src0_reg_hw_type, /* 4+ */ 41, 39, /* 8+ */ 46, 43)
168 F8(src0_reg_file, /* 4+ */ 38, 37, /* 8+ */ 42, 41)
169 F(src0_is_imm, /* 4+ */ -1, -1)
170 F8(dst_reg_hw_type, /* 4+ */ 36, 34, /* 8+ */ 40, 37)
171 F8(dst_reg_file, /* 4+ */ 33, 32, /* 8+ */ 36, 35)
172 F8(mask_control, /* 4+ */ 9, 9, /* 8+ */ 34, 34)
173 FF(flag_reg_nr,
174 /* 4-6: doesn't exist */ -1, -1, -1, -1, -1, -1, -1, -1,
175 /* 7: */ 90, 90,
176 /* 8: */ 33, 33)
177 F8(flag_subreg_nr, /* 4+ */ 89, 89, /* 8+ */ 32, 32)
178 F(saturate, /* 4+ */ 31, 31)
179 F(debug_control, /* 4+ */ 30, 30)
180 F(cmpt_control, /* 4+ */ 29, 29)
181 FC(branch_control, /* 4+ */ 28, 28, devinfo->ver >= 8)
182 FC(acc_wr_control, /* 4+ */ 28, 28, devinfo->ver >= 6)
183 FC(mask_control_ex, /* 4+ */ 28, 28, devinfo->verx10 == 45 ||
184 devinfo->ver == 5)
185 F(cond_modifier, /* 4+ */ 27, 24)
186 FC(math_function, /* 4+ */ 27, 24, devinfo->ver >= 6)
187 F(exec_size, /* 4+ */ 23, 21)
188 F(pred_inv, /* 4+ */ 20, 20)
189 F(pred_control, /* 4+ */ 19, 16)
190 F(thread_control, /* 4+ */ 15, 14)
191 F(atomic_control, /* 4+ */ -1, -1)
192 F(qtr_control, /* 4+ */ 13, 12)
193 FF(nib_control,
194 /* 4-6: doesn't exist */ -1, -1, -1, -1, -1, -1, -1, -1,
195 /* 7: */ 47, 47,
196 /* 8: */ 11, 11);
197 F8(no_dd_check, /* 4+ */ 11, 11, /* 8+ */ 10, 10)
198 F8(no_dd_clear, /* 4+ */ 10, 10, /* 8+ */ 9, 9)
199 F(access_mode, /* 4+ */ 8, 8)
200 /* Bit 7 is Reserved (for future Opcode expansion) */
201 F(hw_opcode, /* 4+ */ 6, 0)
202
203 /**
204 * Three-source instructions:
205 * @{
206 */
207 F(3src_src2_reg_nr, /* 4+ */ 125, 118) /* same in align1 */
208 F(3src_a16_src2_subreg_nr, /* 4+ */ 117, 115) /* Extra discontiguous bit on CHV? */
209 F(3src_a16_src2_swizzle, /* 4+ */ 114, 107)
210 F(3src_a16_src2_rep_ctrl, /* 4+ */ 106, 106)
211 F(3src_src1_reg_nr, /* 4+ */ 104, 97) /* same in align1 */
212 F(3src_a16_src1_subreg_nr, /* 4+ */ 96, 94) /* Extra discontiguous bit on CHV? */
213 F(3src_a16_src1_swizzle, /* 4+ */ 93, 86)
214 F(3src_a16_src1_rep_ctrl, /* 4+ */ 85, 85)
215 F(3src_src0_reg_nr, /* 4+ */ 83, 76) /* same in align1 */
216 F(3src_a16_src0_subreg_nr, /* 4+ */ 75, 73) /* Extra discontiguous bit on CHV? */
217 F(3src_a16_src0_swizzle, /* 4+ */ 72, 65)
218 F(3src_a16_src0_rep_ctrl, /* 4+ */ 64, 64)
219 F(3src_dst_reg_nr, /* 4+ */ 63, 56) /* same in align1 */
220 F(3src_a16_dst_subreg_nr, /* 4+ */ 55, 53)
221 F(3src_a16_dst_writemask, /* 4+ */ 52, 49)
222 F8(3src_a16_nib_ctrl, /* 4+ */ 47, 47, /* 8+ */ 11, 11) /* only exists on IVB+ */
223 F8(3src_a16_dst_hw_type, /* 4+ */ 45, 44, /* 8+ */ 48, 46) /* only exists on IVB+ */
224 F8(3src_a16_src_hw_type, /* 4+ */ 43, 42, /* 8+ */ 45, 43)
225 F8(3src_src2_negate, /* 4+ */ 41, 41, /* 8+ */ 42, 42)
226 F8(3src_src2_abs, /* 4+ */ 40, 40, /* 8+ */ 41, 41)
227 F8(3src_src1_negate, /* 4+ */ 39, 39, /* 8+ */ 40, 40)
228 F8(3src_src1_abs, /* 4+ */ 38, 38, /* 8+ */ 39, 39)
229 F8(3src_src0_negate, /* 4+ */ 37, 37, /* 8+ */ 38, 38)
230 F8(3src_src0_abs, /* 4+ */ 36, 36, /* 8+ */ 37, 37)
231 F8(3src_a16_src1_type, /* 4+ */ -1, -1, /* 8+ */ 36, 36)
232 F8(3src_a16_src2_type, /* 4+ */ -1, -1, /* 8+ */ 35, 35)
233 F8(3src_a16_flag_reg_nr, /* 4+ */ 34, 34, /* 8+ */ 33, 33)
234 F8(3src_a16_flag_subreg_nr, /* 4+ */ 33, 33, /* 8+ */ 32, 32)
235 FF(3src_a16_dst_reg_file,
236 /* 4-5: doesn't exist - no 3-source instructions */ -1, -1, -1, -1, -1, -1,
237 /* 6: */ 32, 32,
238 /* 7-8: doesn't exist - no MRFs */ -1, -1, -1, -1)
239 F(3src_saturate, /* 4+ */ 31, 31)
240 F(3src_debug_control, /* 4+ */ 30, 30)
241 F(3src_cmpt_control, /* 4+ */ 29, 29)
242 F(3src_acc_wr_control, /* 4+ */ 28, 28)
243 F(3src_cond_modifier, /* 4+ */ 27, 24)
244 F(3src_exec_size, /* 4+ */ 23, 21)
245 F(3src_pred_inv, /* 4+ */ 20, 20)
246 F(3src_pred_control, /* 4+ */ 19, 16)
247 F(3src_thread_control, /* 4+ */ 15, 14)
248 F(3src_qtr_control, /* 4+ */ 13, 12)
249 F8(3src_no_dd_check, /* 4+ */ 11, 11, /* 8+ */ 10, 10)
250 F8(3src_no_dd_clear, /* 4+ */ 10, 10, /* 8+ */ 9, 9)
251 F8(3src_mask_control, /* 4+ */ 9, 9, /* 8+ */ 34, 34)
252 F(3src_access_mode, /* 4+ */ 8, 8)
253 /* Bit 7 is Reserved (for future Opcode expansion) */
254 F(3src_hw_opcode, /* 4+ */ 6, 0)
255 /** @} */
256
257 #define REG_TYPE(reg) \
258 static inline void \
259 elk_inst_set_3src_a16_##reg##_type(const struct intel_device_info *devinfo, \
260 elk_inst *inst, enum elk_reg_type type) \
261 { \
262 unsigned hw_type = elk_reg_type_to_a16_hw_3src_type(devinfo, type); \
263 elk_inst_set_3src_a16_##reg##_hw_type(devinfo, inst, hw_type); \
264 } \
265 \
266 static inline enum elk_reg_type \
267 elk_inst_3src_a16_##reg##_type(const struct intel_device_info *devinfo, \
268 const elk_inst *inst) \
269 { \
270 unsigned hw_type = elk_inst_3src_a16_##reg##_hw_type(devinfo, inst); \
271 return elk_a16_hw_3src_type_to_reg_type(devinfo, hw_type); \
272 }
273
REG_TYPE(dst)274 REG_TYPE(dst)
275 REG_TYPE(src)
276 #undef REG_TYPE
277
278 /**
279 * Three-source align1 instructions:
280 * @{
281 */
282 F(3src_a1_src2_subreg_nr, /* 4+ */ 117, 113)
283 F(3src_a1_src1_subreg_nr, /* 4+ */ 96, 92)
284 F(3src_a1_src0_subreg_nr, /* 4+ */ 75, 71)
285 F8(3src_a1_src2_reg_file, /* 4+ */ -1, -1, /* 8+ */ 45, 45)
286
287 /** @} */
288
289 /**
290 * Flow control instruction bits:
291 * @{
292 */
293 static inline void
294 elk_inst_set_uip(const struct intel_device_info *devinfo,
295 elk_inst *inst, int32_t value)
296 {
297 assert(devinfo->ver >= 6);
298
299 if (devinfo->ver >= 8) {
300 elk_inst_set_bits(inst, 95, 64, (uint32_t)value);
301 } else {
302 assert(value <= (1 << 16) - 1);
303 assert(value > -(1 << 16));
304 elk_inst_set_bits(inst, 127, 112, (uint16_t)value);
305 }
306 }
307
308 static inline int32_t
elk_inst_uip(const struct intel_device_info * devinfo,const elk_inst * inst)309 elk_inst_uip(const struct intel_device_info *devinfo, const elk_inst *inst)
310 {
311 assert(devinfo->ver >= 6);
312
313 if (devinfo->ver >= 8) {
314 return elk_inst_bits(inst, 95, 64);
315 } else {
316 return (int16_t)elk_inst_bits(inst, 127, 112);
317 }
318 }
319
320 static inline void
elk_inst_set_jip(const struct intel_device_info * devinfo,elk_inst * inst,int32_t value)321 elk_inst_set_jip(const struct intel_device_info *devinfo,
322 elk_inst *inst, int32_t value)
323 {
324 assert(devinfo->ver >= 6);
325
326 if (devinfo->ver >= 8) {
327 elk_inst_set_bits(inst, 127, 96, (uint32_t)value);
328 } else {
329 assert(value <= (1 << 15) - 1);
330 assert(value >= -(1 << 15));
331 elk_inst_set_bits(inst, 111, 96, (uint16_t)value);
332 }
333 }
334
335 static inline int32_t
elk_inst_jip(const struct intel_device_info * devinfo,const elk_inst * inst)336 elk_inst_jip(const struct intel_device_info *devinfo, const elk_inst *inst)
337 {
338 assert(devinfo->ver >= 6);
339
340 if (devinfo->ver >= 8) {
341 return elk_inst_bits(inst, 127, 96);
342 } else {
343 return (int16_t)elk_inst_bits(inst, 111, 96);
344 }
345 }
346
347 /** Like FC, but using int16_t to handle negative jump targets. */
348 #define FJ(name, high, low, assertions) \
349 static inline void \
350 elk_inst_set_##name(const struct intel_device_info *devinfo, elk_inst *inst, int16_t v) \
351 { \
352 assert(assertions); \
353 (void) devinfo; \
354 elk_inst_set_bits(inst, high, low, (uint16_t) v); \
355 } \
356 static inline int16_t \
357 elk_inst_##name(const struct intel_device_info *devinfo, const elk_inst *inst)\
358 { \
359 assert(assertions); \
360 (void) devinfo; \
361 return elk_inst_bits(inst, high, low); \
362 }
363
364 FJ(gfx6_jump_count, 63, 48, devinfo->ver == 6)
365 FJ(gfx4_jump_count, 111, 96, devinfo->ver < 6)
366 FC(gfx4_pop_count, /* 4+ */ 115, 112, devinfo->ver < 6)
367 /** @} */
368
369 /**
370 * SEND instructions:
371 * @{
372 */
373 F8(send_src0_reg_file, /* 4+ */ 38, 37, /* 8+ */ 42, 41)
374 /** @} */
375
376 /* Message descriptor bits */
377 #define MD(x) ((x) + 96)
378 #define MD12(x) ((x) >= 30 ? (x) - 30 + 122 : \
379 (x) >= 25 ? (x) - 25 + 67 : \
380 (x) >= 20 ? (x) - 20 + 51 : \
381 (x) >= 11 ? (x) - 11 + 113 : \
382 (x) - 0 + 81)
383
384 /**
385 * Set the SEND(C) message descriptor immediate.
386 *
387 * This doesn't include the SFID nor the EOT field that were considered to be
388 * part of the message descriptor by ancient versions of the BSpec, because
389 * they are present in the instruction even if the message descriptor is
390 * provided indirectly in the address register, so we want to specify them
391 * separately.
392 */
393 static inline void
elk_inst_set_send_desc(const struct intel_device_info * devinfo,elk_inst * inst,uint32_t value)394 elk_inst_set_send_desc(const struct intel_device_info *devinfo,
395 elk_inst *inst, uint32_t value)
396 {
397 if (devinfo->ver >= 5) {
398 elk_inst_set_bits(inst, 124, 96, value);
399 assert(value >> 29 == 0);
400 } else {
401 elk_inst_set_bits(inst, 119, 96, value);
402 assert(value >> 24 == 0);
403 }
404 }
405
406 /**
407 * Get the SEND(C) message descriptor immediate.
408 *
409 * \sa elk_inst_set_send_desc().
410 */
411 static inline uint32_t
elk_inst_send_desc(const struct intel_device_info * devinfo,const elk_inst * inst)412 elk_inst_send_desc(const struct intel_device_info *devinfo,
413 const elk_inst *inst)
414 {
415 if (devinfo->ver >= 5) {
416 return elk_inst_bits(inst, 124, 96);
417 } else {
418 return elk_inst_bits(inst, 119, 96);
419 }
420 }
421
422 /**
423 * Fields for SEND messages:
424 * @{
425 */
426 F(eot, /* 4+ */ 127, 127)
427 FF(mlen,
428 /* 4: */ 119, 116,
429 /* 4.5: */ 119, 116,
430 /* 5: */ 124, 121,
431 /* 6: */ 124, 121,
432 /* 7: */ 124, 121,
433 /* 8: */ 124, 121)
434 FF(rlen,
435 /* 4: */ 115, 112,
436 /* 4.5: */ 115, 112,
437 /* 5: */ 120, 116,
438 /* 6: */ 120, 116,
439 /* 7: */ 120, 116,
440 /* 8: */ 120, 116)
441 FF(header_present,
442 /* 4: doesn't exist */ -1, -1, -1, -1,
443 /* 5: */ 115, 115,
444 /* 6: */ 115, 115,
445 /* 7: */ 115, 115,
446 /* 8: */ 115, 115)
447 F(gateway_notify, /* 4+ */ MD(16), MD(15))
448 FF(function_control,
449 /* 4: */ 111, 96,
450 /* 4.5: */ 111, 96,
451 /* 5: */ 114, 96,
452 /* 6: */ 114, 96,
453 /* 7: */ 114, 96,
454 /* 8: */ 114, 96)
455 FF(gateway_subfuncid,
456 /* 4: */ MD(1), MD(0),
457 /* 4.5: */ MD(1), MD(0),
458 /* 5: */ MD(1), MD(0), /* 2:0, but bit 2 is reserved MBZ */
459 /* 6: */ MD(2), MD(0),
460 /* 7: */ MD(2), MD(0),
461 /* 8: */ MD(2), MD(0))
462 FF(sfid,
463 /* 4: */ 123, 120, /* called msg_target */
464 /* 4.5 */ 123, 120,
465 /* 5: */ 95, 92,
466 /* 6: */ 27, 24,
467 /* 7: */ 27, 24,
468 /* 8: */ 27, 24)
469 F8(null_rt, /* 4+ */ -1, -1, /* 8+ */ 80, 80)
470 FC(base_mrf, /* 4+ */ 27, 24, devinfo->ver < 6);
471 /** @} */
472
473 /**
474 * URB message function control bits:
475 * @{
476 */
477 FF(urb_per_slot_offset,
478 /* 4-6: */ -1, -1, -1, -1, -1, -1, -1, -1,
479 /* 7: */ MD(16), MD(16),
480 /* 8: */ MD(17), MD(17))
481 FC(urb_channel_mask_present, /* 4+ */ MD(15), MD(15), devinfo->ver >= 8)
482 FC(urb_complete, /* 4+ */ MD(15), MD(15), devinfo->ver < 8)
483 FC(urb_used, /* 4+ */ MD(14), MD(14), devinfo->ver < 7)
484 FC(urb_allocate, /* 4+ */ MD(13), MD(13), devinfo->ver < 7)
485 FF(urb_swizzle_control,
486 /* 4: */ MD(11), MD(10),
487 /* 4.5: */ MD(11), MD(10),
488 /* 5: */ MD(11), MD(10),
489 /* 6: */ MD(11), MD(10),
490 /* 7: */ MD(14), MD(14),
491 /* 8: */ MD(15), MD(15))
492 FF(urb_global_offset,
493 /* 4: */ MD( 9), MD(4),
494 /* 4.5: */ MD( 9), MD(4),
495 /* 5: */ MD( 9), MD(4),
496 /* 6: */ MD( 9), MD(4),
497 /* 7: */ MD(13), MD(3),
498 /* 8: */ MD(14), MD(4))
499 FF(urb_opcode,
500 /* 4: */ MD( 3), MD(0),
501 /* 4.5: */ MD( 3), MD(0),
502 /* 5: */ MD( 3), MD(0),
503 /* 6: */ MD( 3), MD(0),
504 /* 7: */ MD( 2), MD(0),
505 /* 8: */ MD( 3), MD(0))
506 /** @} */
507
508 /**
509 * Gfx4-5 math messages:
510 * @{
511 */
512 FC(math_msg_data_type, /* 4+ */ MD(7), MD(7), devinfo->ver < 6)
513 FC(math_msg_saturate, /* 4+ */ MD(6), MD(6), devinfo->ver < 6)
514 FC(math_msg_precision, /* 4+ */ MD(5), MD(5), devinfo->ver < 6)
515 FC(math_msg_signed_int, /* 4+ */ MD(4), MD(4), devinfo->ver < 6)
516 FC(math_msg_function, /* 4+ */ MD(3), MD(0), devinfo->ver < 6)
517 /** @} */
518
519 /**
520 * Sampler message function control bits:
521 * @{
522 */
523 FF(sampler_simd_mode,
524 /* 4: doesn't exist */ -1, -1, -1, -1,
525 /* 5: */ MD(17), MD(16),
526 /* 6: */ MD(17), MD(16),
527 /* 7: */ MD(18), MD(17),
528 /* 8: */ MD(18), MD(17))
529 FF(sampler_msg_type,
530 /* 4: */ MD(15), MD(14),
531 /* 4.5: */ MD(15), MD(12),
532 /* 5: */ MD(15), MD(12),
533 /* 6: */ MD(15), MD(12),
534 /* 7: */ MD(16), MD(12),
535 /* 8: */ MD(16), MD(12))
536 FC(sampler_return_format, /* 4+ */ MD(13), MD(12), devinfo->verx10 == 40)
537 FF(sampler,
538 /* 4: */ MD(11), MD(8),
539 /* 4.5: */ MD(11), MD(8),
540 /* 5: */ MD(11), MD(8),
541 /* 6: */ MD(11), MD(8),
542 /* 7: */ MD(11), MD(8),
543 /* 8: */ MD(11), MD(8))
544 F(binding_table_index, /* 4+ */ MD(7), MD(0)) /* also used by other messages */
545 /** @} */
546
547 /**
548 * Data port message function control bits:
549 * @{
550 */
551 FC(dp_category, /* 4+ */ MD(18), MD(18), devinfo->ver >= 7)
552
553 /* Gfx4-5 store fields in different bits for read/write messages. */
554 FF(dp_read_msg_type,
555 /* 4: */ MD(13), MD(12),
556 /* 4.5: */ MD(13), MD(11),
557 /* 5: */ MD(13), MD(11),
558 /* 6: */ MD(16), MD(13),
559 /* 7: */ MD(17), MD(14),
560 /* 8: */ MD(17), MD(14))
561 FF(dp_write_msg_type,
562 /* 4: */ MD(14), MD(12),
563 /* 4.5: */ MD(14), MD(12),
564 /* 5: */ MD(14), MD(12),
565 /* 6: */ MD(16), MD(13),
566 /* 7: */ MD(17), MD(14),
567 /* 8: */ MD(17), MD(14))
568 FF(dp_read_msg_control,
569 /* 4: */ MD(11), MD( 8),
570 /* 4.5: */ MD(10), MD( 8),
571 /* 5: */ MD(10), MD( 8),
572 /* 6: */ MD(12), MD( 8),
573 /* 7: */ MD(13), MD( 8),
574 /* 8: */ MD(13), MD( 8))
575 FF(dp_write_msg_control,
576 /* 4: */ MD(11), MD( 8),
577 /* 4.5: */ MD(11), MD( 8),
578 /* 5: */ MD(11), MD( 8),
579 /* 6: */ MD(12), MD( 8),
580 /* 7: */ MD(13), MD( 8),
581 /* 8: */ MD(13), MD( 8))
582 FC(dp_read_target_cache, /* 4+ */ MD(15), MD(14), devinfo->ver < 6);
583
584 FF(dp_write_commit,
585 /* 4: */ MD(15), MD(15),
586 /* 4.5: */ MD(15), MD(15),
587 /* 5: */ MD(15), MD(15),
588 /* 6: */ MD(17), MD(17),
589 /* 7+: does not exist */ -1, -1, -1, -1)
590
591 /* Gfx6+ use the same bit locations for everything. */
592 FF(dp_msg_type,
593 /* 4-5: use dp_read_msg_type or dp_write_msg_type instead */
594 -1, -1, -1, -1, -1, -1,
595 /* 6: */ MD(16), MD(13),
596 /* 7: */ MD(17), MD(14),
597 /* 8: */ MD(18), MD(14))
598 FF(dp_msg_control,
599 /* 4: */ MD(11), MD( 8),
600 /* 4.5-5: use dp_read_msg_control or dp_write_msg_control */ -1, -1, -1, -1,
601 /* 6: */ MD(12), MD( 8),
602 /* 7: */ MD(13), MD( 8),
603 /* 8: */ MD(13), MD( 8))
604 /** @} */
605
606 /**
607 * Scratch message bits (Gfx7+):
608 * @{
609 */
610 FC(scratch_read_write, /* 4+ */ MD(17), MD(17), devinfo->ver >= 7) /* 0 = read, 1 = write */
611 FC(scratch_type, /* 4+ */ MD(16), MD(16), devinfo->ver >= 7) /* 0 = OWord, 1 = DWord */
612 FC(scratch_invalidate_after_read, /* 4+ */ MD(15), MD(15), devinfo->ver >= 7)
613 FC(scratch_block_size, /* 4+ */ MD(13), MD(12), devinfo->ver >= 7)
614 FF(scratch_addr_offset,
615 /* 4: */ -1, -1,
616 /* 4.5: */ -1, -1,
617 /* 5: */ -1, -1,
618 /* 6: */ -1, -1,
619 /* 7: */ MD(11), MD(0),
620 /* 8: */ MD(11), MD(0))
621 /** @} */
622
623 /**
624 * Render Target message function control bits:
625 * @{
626 */
627 FF(rt_last,
628 /* 4: */ MD(11), MD(11),
629 /* 4.5: */ MD(11), MD(11),
630 /* 5: */ MD(11), MD(11),
631 /* 6: */ MD(12), MD(12),
632 /* 7: */ MD(12), MD(12),
633 /* 8: */ MD(12), MD(12))
634 FC(rt_slot_group, /* 4+ */ MD(11), MD(11), devinfo->ver >= 6)
635 F(rt_message_type, /* 4+ */ MD(10), MD( 8))
636 /** @} */
637
638 /**
639 * Thread Spawn message function control bits:
640 * @{
641 */
642 F(ts_resource_select, /* 4+ */ MD( 4), MD( 4))
643 F(ts_request_type, /* 4+ */ MD( 1), MD( 1))
644 F(ts_opcode, /* 4+ */ MD( 0), MD( 0))
645 /** @} */
646
647 /**
648 * Pixel Interpolator message function control bits:
649 * @{
650 */
651 F(pi_simd_mode, /* 4+ */ MD(16), MD(16))
652 F(pi_nopersp, /* 4+ */ MD(14), MD(14))
653 F(pi_message_type, /* 4+ */ MD(13), MD(12))
654 F(pi_slot_group, /* 4+ */ MD(11), MD(11))
655 F(pi_message_data, /* 4+ */ MD(7), MD(0))
656 /** @} */
657
658 /**
659 * Immediates:
660 * @{
661 */
662 static inline int
elk_inst_imm_d(const struct intel_device_info * devinfo,const elk_inst * insn)663 elk_inst_imm_d(const struct intel_device_info *devinfo, const elk_inst *insn)
664 {
665 (void) devinfo;
666 return elk_inst_bits(insn, 127, 96);
667 }
668
669 static inline unsigned
elk_inst_imm_ud(const struct intel_device_info * devinfo,const elk_inst * insn)670 elk_inst_imm_ud(const struct intel_device_info *devinfo, const elk_inst *insn)
671 {
672 (void) devinfo;
673 return elk_inst_bits(insn, 127, 96);
674 }
675
676 static inline uint64_t
elk_inst_imm_uq(const struct intel_device_info * devinfo,const elk_inst * insn)677 elk_inst_imm_uq(const struct intel_device_info *devinfo,
678 const elk_inst *insn)
679 {
680 assert(devinfo->ver >= 8);
681 return elk_inst_bits(insn, 127, 64);
682 }
683
684 static inline float
elk_inst_imm_f(const struct intel_device_info * devinfo,const elk_inst * insn)685 elk_inst_imm_f(const struct intel_device_info *devinfo, const elk_inst *insn)
686 {
687 union {
688 float f;
689 uint32_t u;
690 } ft;
691 (void) devinfo;
692 ft.u = elk_inst_bits(insn, 127, 96);
693 return ft.f;
694 }
695
696 static inline double
elk_inst_imm_df(const struct intel_device_info * devinfo,const elk_inst * insn)697 elk_inst_imm_df(const struct intel_device_info *devinfo, const elk_inst *insn)
698 {
699 union {
700 double d;
701 uint64_t u;
702 } dt;
703 dt.u = elk_inst_imm_uq(devinfo, insn);
704 return dt.d;
705 }
706
707 static inline void
elk_inst_set_imm_d(const struct intel_device_info * devinfo,elk_inst * insn,int value)708 elk_inst_set_imm_d(const struct intel_device_info *devinfo,
709 elk_inst *insn, int value)
710 {
711 (void) devinfo;
712 return elk_inst_set_bits(insn, 127, 96, value);
713 }
714
715 static inline void
elk_inst_set_imm_ud(const struct intel_device_info * devinfo,elk_inst * insn,unsigned value)716 elk_inst_set_imm_ud(const struct intel_device_info *devinfo,
717 elk_inst *insn, unsigned value)
718 {
719 (void) devinfo;
720 return elk_inst_set_bits(insn, 127, 96, value);
721 }
722
723 static inline void
elk_inst_set_imm_f(const struct intel_device_info * devinfo,elk_inst * insn,float value)724 elk_inst_set_imm_f(const struct intel_device_info *devinfo,
725 elk_inst *insn, float value)
726 {
727 union {
728 float f;
729 uint32_t u;
730 } ft;
731 (void) devinfo;
732 ft.f = value;
733 elk_inst_set_bits(insn, 127, 96, ft.u);
734 }
735
736 static inline void
elk_inst_set_imm_df(const struct intel_device_info * devinfo,elk_inst * insn,double value)737 elk_inst_set_imm_df(const struct intel_device_info *devinfo,
738 elk_inst *insn, double value)
739 {
740 union {
741 double d;
742 uint64_t u;
743 } dt;
744 (void) devinfo;
745 dt.d = value;
746
747 elk_inst_set_bits(insn, 127, 64, dt.u);
748 }
749
750 static inline void
elk_inst_set_imm_uq(const struct intel_device_info * devinfo,elk_inst * insn,uint64_t value)751 elk_inst_set_imm_uq(const struct intel_device_info *devinfo,
752 elk_inst *insn, uint64_t value)
753 {
754 (void) devinfo;
755 elk_inst_set_bits(insn, 127, 64, value);
756 }
757
758 /** @} */
759
760 #define REG_TYPE(reg) \
761 static inline void \
762 elk_inst_set_##reg##_file_type(const struct intel_device_info *devinfo, \
763 elk_inst *inst, enum elk_reg_file file, \
764 enum elk_reg_type type) \
765 { \
766 assert(file <= ELK_IMMEDIATE_VALUE); \
767 unsigned hw_type = elk_reg_type_to_hw_type(devinfo, file, type); \
768 elk_inst_set_##reg##_reg_file(devinfo, inst, file); \
769 elk_inst_set_##reg##_reg_hw_type(devinfo, inst, hw_type); \
770 } \
771 \
772 static inline enum elk_reg_type \
773 elk_inst_##reg##_type(const struct intel_device_info *devinfo, \
774 const elk_inst *inst) \
775 { \
776 unsigned file = __builtin_strcmp("dst", #reg) == 0 ? \
777 (unsigned) ELK_GENERAL_REGISTER_FILE : \
778 elk_inst_##reg##_reg_file(devinfo, inst); \
779 unsigned hw_type = elk_inst_##reg##_reg_hw_type(devinfo, inst); \
780 return elk_hw_type_to_reg_type(devinfo, (enum elk_reg_file)file, hw_type); \
781 }
782
783 REG_TYPE(dst)
REG_TYPE(src0)784 REG_TYPE(src0)
785 REG_TYPE(src1)
786 #undef REG_TYPE
787
788
789 /* The AddrImm fields are split into two discontiguous sections on Gfx8+ */
790 #define ELK_IA1_ADDR_IMM(reg, g4_high, g4_low, g8_nine, g8_high, g8_low) \
791 static inline void \
792 elk_inst_set_##reg##_ia1_addr_imm(const struct \
793 intel_device_info *devinfo, \
794 elk_inst *inst, \
795 unsigned value) \
796 { \
797 if (devinfo->ver >= 8) { \
798 assert((value & ~0x3ff) == 0); \
799 elk_inst_set_bits(inst, g8_high, g8_low, value & 0x1ff); \
800 elk_inst_set_bits(inst, g8_nine, g8_nine, value >> 9); \
801 } else { \
802 assert((value & ~0x3ff) == 0); \
803 elk_inst_set_bits(inst, g4_high, g4_low, value); \
804 } \
805 } \
806 static inline unsigned \
807 elk_inst_##reg##_ia1_addr_imm(const struct intel_device_info *devinfo, \
808 const elk_inst *inst) \
809 { \
810 if (devinfo->ver >= 8) { \
811 return elk_inst_bits(inst, g8_high, g8_low) | \
812 (elk_inst_bits(inst, g8_nine, g8_nine) << 9); \
813 } else { \
814 return elk_inst_bits(inst, g4_high, g4_low); \
815 } \
816 }
817
818 /* AddrImm for Align1 Indirect Addressing */
819 /* -Gen 4- ----Gfx8---- */
820 ELK_IA1_ADDR_IMM(src1, 105, 96, 121, 104, 96)
821 ELK_IA1_ADDR_IMM(src0, 73, 64, 95, 72, 64)
822 ELK_IA1_ADDR_IMM(dst, 57, 48, 47, 56, 48)
823
824 #define ELK_IA16_ADDR_IMM(reg, g4_high, g4_low, g8_nine, g8_high, g8_low) \
825 static inline void \
826 elk_inst_set_##reg##_ia16_addr_imm(const struct \
827 intel_device_info *devinfo, \
828 elk_inst *inst, unsigned value) \
829 { \
830 assert((value & ~0x3ff) == 0); \
831 if (devinfo->ver >= 8) { \
832 assert(GET_BITS(value, 3, 0) == 0); \
833 elk_inst_set_bits(inst, g8_high, g8_low, GET_BITS(value, 8, 4)); \
834 elk_inst_set_bits(inst, g8_nine, g8_nine, GET_BITS(value, 9, 9)); \
835 } else { \
836 elk_inst_set_bits(inst, g4_high, g4_low, value); \
837 } \
838 } \
839 static inline unsigned \
840 elk_inst_##reg##_ia16_addr_imm(const struct intel_device_info *devinfo, \
841 const elk_inst *inst) \
842 { \
843 if (devinfo->ver >= 8) { \
844 return (elk_inst_bits(inst, g8_high, g8_low) << 4) | \
845 (elk_inst_bits(inst, g8_nine, g8_nine) << 9); \
846 } else { \
847 return elk_inst_bits(inst, g4_high, g4_low); \
848 } \
849 }
850
851 /* AddrImm[9:0] for Align16 Indirect Addressing:
852 * Compared to Align1, these are missing the low 4 bits.
853 * -Gen 4- ----Gfx8----
854 */
855 ELK_IA16_ADDR_IMM(src1, 105, 96, 121, 104, 100)
856 ELK_IA16_ADDR_IMM(src0, 73, 64, 95, 72, 68)
857 ELK_IA16_ADDR_IMM(dst, 57, 52, 47, 56, 52)
858 ELK_IA16_ADDR_IMM(send_src0, -1, -1, 78, 72, 68)
859 ELK_IA16_ADDR_IMM(send_dst, -1, -1, 62, 56, 52)
860
861 /**
862 * Fetch a set of contiguous bits from the instruction.
863 *
864 * Bits indices range from 0..127; fields may not cross 64-bit boundaries.
865 */
866 static inline uint64_t
867 elk_inst_bits(const elk_inst *inst, unsigned high, unsigned low)
868 {
869 assume(high < 128);
870 assume(high >= low);
871 /* We assume the field doesn't cross 64-bit boundaries. */
872 const unsigned word = high / 64;
873 assert(word == low / 64);
874
875 high %= 64;
876 low %= 64;
877
878 const uint64_t mask = (~0ull >> (64 - (high - low + 1)));
879
880 return (inst->data[word] >> low) & mask;
881 }
882
883 /**
884 * Set bits in the instruction, with proper shifting and masking.
885 *
886 * Bits indices range from 0..127; fields may not cross 64-bit boundaries.
887 */
888 static inline void
elk_inst_set_bits(elk_inst * inst,unsigned high,unsigned low,uint64_t value)889 elk_inst_set_bits(elk_inst *inst, unsigned high, unsigned low, uint64_t value)
890 {
891 assume(high < 128);
892 assume(high >= low);
893 const unsigned word = high / 64;
894 assert(word == low / 64);
895
896 high %= 64;
897 low %= 64;
898
899 const uint64_t mask = (~0ull >> (64 - (high - low + 1))) << low;
900
901 /* Make sure the supplied value actually fits in the given bitfield. */
902 assert((value & (mask >> low)) == value);
903
904 inst->data[word] = (inst->data[word] & ~mask) | (value << low);
905 }
906
907 #undef ELK_IA16_ADDR_IMM
908 #undef ELK_IA1_ADDR_IMM
909 #undef MD
910 #undef F8
911 #undef FF
912 #undef BOUNDS
913 #undef F
914 #undef FC
915 #undef F20
916 #undef FD20
917
918 typedef struct {
919 uint64_t data;
920 } elk_compact_inst;
921
922 /**
923 * Fetch a set of contiguous bits from the compacted instruction.
924 *
925 * Bits indices range from 0..63.
926 */
927 static inline unsigned
elk_compact_inst_bits(const elk_compact_inst * inst,unsigned high,unsigned low)928 elk_compact_inst_bits(const elk_compact_inst *inst, unsigned high, unsigned low)
929 {
930 assume(high < 64);
931 assume(high >= low);
932 const uint64_t mask = (1ull << (high - low + 1)) - 1;
933
934 return (inst->data >> low) & mask;
935 }
936
937 /**
938 * Set bits in the compacted instruction.
939 *
940 * Bits indices range from 0..63.
941 */
942 static inline void
elk_compact_inst_set_bits(elk_compact_inst * inst,unsigned high,unsigned low,uint64_t value)943 elk_compact_inst_set_bits(elk_compact_inst *inst, unsigned high, unsigned low,
944 uint64_t value)
945 {
946 assume(high < 64);
947 assume(high >= low);
948 const uint64_t mask = ((1ull << (high - low + 1)) - 1) << low;
949
950 /* Make sure the supplied value actually fits in the given bitfield. */
951 assert((value & (mask >> low)) == value);
952
953 inst->data = (inst->data & ~mask) | (value << low);
954 }
955
956 #define FC(name, high, low, assertions) \
957 static inline void \
958 elk_compact_inst_set_##name(const struct \
959 intel_device_info *devinfo, \
960 elk_compact_inst *inst, unsigned v) \
961 { \
962 assert(assertions); \
963 elk_compact_inst_set_bits(inst, high, low, v); \
964 } \
965 static inline unsigned \
966 elk_compact_inst_##name(const struct intel_device_info *devinfo, \
967 const elk_compact_inst *inst) \
968 { \
969 assert(assertions); \
970 return elk_compact_inst_bits(inst, high, low); \
971 }
972
973 /* A simple macro for fields which stay in the same place on all generations. */
974 #define F(name, high, low) FC(name, high, low, true)
975
976 /* A macro for fields which moved as of Gfx8+. */
977 #define F8(name, high, low, hi8, lo8) \
978 static inline void \
979 elk_compact_inst_set_##name(const struct \
980 intel_device_info *devinfo, \
981 elk_compact_inst *inst, unsigned v) \
982 { \
983 if (devinfo->ver >= 8) \
984 elk_compact_inst_set_bits(inst, hi8, lo8, v); \
985 else \
986 elk_compact_inst_set_bits(inst, high, low, v); \
987 } \
988 static inline unsigned \
989 elk_compact_inst_##name(const struct intel_device_info *devinfo, \
990 const elk_compact_inst *inst) \
991 { \
992 if (devinfo->ver >= 8) \
993 return elk_compact_inst_bits(inst, hi8, lo8); \
994 else \
995 return elk_compact_inst_bits(inst, high, low); \
996 }
997
998 F(src1_reg_nr, /* 4+ */ 63, 56)
999 F(src0_reg_nr, /* 4+ */ 55, 48)
1000 F8(dst_reg_nr, /* 4+ */ 47, 40, /* 8+ */ 47, 40)
1001 F(src1_index, /* 4+ */ 39, 35)
1002 F8(src0_index, /* 4+ */ 34, 30, /* 8+ */ 34, 30)
1003 F(cmpt_control, /* 4+ */ 29, 29) /* Same location as elk_inst */
1004 FC(flag_subreg_nr, /* 4+ */ 28, 28, devinfo->ver <= 6)
1005 F(cond_modifier, /* 4+ */ 27, 24) /* Same location as elk_inst */
1006 FC(acc_wr_control, /* 4+ */ 23, 23, devinfo->ver >= 6)
1007 FC(mask_control_ex, /* 4+ */ 23, 23, devinfo->verx10 == 45 || devinfo->ver == 5)
1008 F8(subreg_index, /* 4+ */ 22, 18, /* 8+ */ 22, 18)
1009 F8(datatype_index, /* 4+ */ 17, 13, /* 8+ */ 17, 13)
1010 F8(control_index, /* 4+ */ 12, 8, /* 8+ */ 12, 8)
1011 F(debug_control, /* 4+ */ 7, 7)
1012 F(hw_opcode, /* 4+ */ 6, 0) /* Same location as elk_inst */
1013
1014 static inline unsigned
elk_compact_inst_imm(const struct intel_device_info * devinfo,const elk_compact_inst * inst)1015 elk_compact_inst_imm(const struct intel_device_info *devinfo,
1016 const elk_compact_inst *inst)
1017 {
1018 return (elk_compact_inst_bits(inst, 39, 35) << 8) |
1019 (elk_compact_inst_bits(inst, 63, 56));
1020 }
1021
1022 /**
1023 * (Gfx8+) Compacted three-source instructions:
1024 * @{
1025 */
1026 FC(3src_src2_reg_nr, /* 4+ */ 63, 57, devinfo->ver >= 8)
1027 FC(3src_src1_reg_nr, /* 4+ */ 56, 50, devinfo->ver >= 8)
1028 FC(3src_src0_reg_nr, /* 4+ */ 49, 43, devinfo->ver >= 8)
1029 FC(3src_src2_subreg_nr, /* 4+ */ 42, 40, devinfo->ver >= 8)
1030 FC(3src_src1_subreg_nr, /* 4+ */ 39, 37, devinfo->ver >= 8)
1031 FC(3src_src0_subreg_nr, /* 4+ */ 36, 34, devinfo->ver >= 8)
1032 FC(3src_src2_rep_ctrl, /* 4+ */ 33, 33, devinfo->ver >= 8)
1033 FC(3src_src1_rep_ctrl, /* 4+ */ 32, 32, devinfo->ver >= 8)
1034 FC(3src_saturate, /* 4+ */ 31, 31, devinfo->ver >= 8)
1035 FC(3src_debug_control, /* 4+ */ 30, 30, devinfo->ver >= 8)
1036 FC(3src_cmpt_control, /* 4+ */ 29, 29, devinfo->ver >= 8)
1037 FC(3src_src0_rep_ctrl, /* 4+ */ 28, 28, devinfo->ver >= 8)
1038 /* Reserved */
1039 F8(3src_dst_reg_nr, /* 4+ */ 18, 12, /* 8+ */ 18, 12)
1040 F8(3src_source_index, /* 4+ */ -1, -1, /* 8+ */ 11, 10)
1041 F8(3src_control_index, /* 4+ */ -1, -1, /* 8+ */ 9, 8)
1042 /* Bit 7 is Reserved (for future Opcode expansion) */
1043 FC(3src_hw_opcode, /* 4+ */ 6, 0, devinfo->ver >= 8)
1044 /** @} */
1045
1046 #undef F
1047
1048 static inline void
elk_inst_set_opcode(const struct elk_isa_info * isa,struct elk_inst * inst,enum elk_opcode opcode)1049 elk_inst_set_opcode(const struct elk_isa_info *isa,
1050 struct elk_inst *inst, enum elk_opcode opcode)
1051 {
1052 elk_inst_set_hw_opcode(isa->devinfo, inst, elk_opcode_encode(isa, opcode));
1053 }
1054
1055 static inline enum elk_opcode
elk_inst_opcode(const struct elk_isa_info * isa,const struct elk_inst * inst)1056 elk_inst_opcode(const struct elk_isa_info *isa,
1057 const struct elk_inst *inst)
1058 {
1059 return elk_opcode_decode(isa, elk_inst_hw_opcode(isa->devinfo, inst));
1060 }
1061
1062 #ifdef __cplusplus
1063 }
1064 #endif
1065
1066 #endif
1067