1 /* 2 Copyright (C) Intel Corp. 2006. All Rights Reserved. 3 Intel funded Tungsten Graphics to 4 develop this 3D driver. 5 6 Permission is hereby granted, free of charge, to any person obtaining 7 a copy of this software and associated documentation files (the 8 "Software"), to deal in the Software without restriction, including 9 without limitation the rights to use, copy, modify, merge, publish, 10 distribute, sublicense, and/or sell copies of the Software, and to 11 permit persons to whom the Software is furnished to do so, subject to 12 the following conditions: 13 14 The above copyright notice and this permission notice (including the 15 next paragraph) shall be included in all copies or substantial 16 portions of the Software. 17 18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 25 26 **********************************************************************/ 27 /* 28 * Authors: 29 * Keith Whitwell <[email protected]> 30 */ 31 32 #ifndef ELK_EU_DEFINES_H 33 #define ELK_EU_DEFINES_H 34 35 #include <stdint.h> 36 #include <stdlib.h> 37 #include "util/macros.h" 38 #include "dev/intel_device_info.h" 39 #include "elk_eu_opcodes.h" 40 41 /* The following hunk, up-to "Execution Unit" is used by both the 42 * intel/compiler and i965 codebase. */ 43 44 #define INTEL_MASK(high, low) (((1u<<((high)-(low)+1))-1)<<(low)) 45 /* Using the GNU statement expression extension */ 46 #define SET_FIELD(value, field) \ 47 ({ \ 48 uint32_t fieldval = (uint32_t)(value) << field ## _SHIFT; \ 49 assert((fieldval & ~ field ## _MASK) == 0); \ 50 fieldval & field ## _MASK; \ 51 }) 52 53 #define SET_BITS(value, high, low) \ 54 ({ \ 55 const uint32_t fieldval = (uint32_t)(value) << (low); \ 56 assert((fieldval & ~INTEL_MASK(high, low)) == 0); \ 57 fieldval & INTEL_MASK(high, low); \ 58 }) 59 60 #define GET_BITS(data, high, low) ((data & INTEL_MASK((high), (low))) >> (low)) 61 #define GET_FIELD(word, field) (((word) & field ## _MASK) >> field ## _SHIFT) 62 63 /* Bitfields for the URB_WRITE message, DW2 of message header: */ 64 #define URB_WRITE_PRIM_END 0x1 65 #define URB_WRITE_PRIM_START 0x2 66 #define URB_WRITE_PRIM_TYPE_SHIFT 2 67 68 #define ELK_SPRITE_POINT_ENABLE 16 69 70 # define GFX7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT 0 71 # define GFX7_GS_CONTROL_DATA_FORMAT_GSCTL_SID 1 72 73 /* Execution Unit (EU) defines 74 */ 75 76 #define ELK_ALIGN_1 0 77 #define ELK_ALIGN_16 1 78 79 #define ELK_ADDRESS_DIRECT 0 80 #define ELK_ADDRESS_REGISTER_INDIRECT_REGISTER 1 81 82 #define ELK_CHANNEL_X 0 83 #define ELK_CHANNEL_Y 1 84 #define ELK_CHANNEL_Z 2 85 #define ELK_CHANNEL_W 3 86 87 enum elk_compression { 88 ELK_COMPRESSION_NONE = 0, 89 ELK_COMPRESSION_2NDHALF = 1, 90 ELK_COMPRESSION_COMPRESSED = 2, 91 }; 92 93 #define GFX6_COMPRESSION_1Q 0 94 #define GFX6_COMPRESSION_2Q 1 95 #define GFX6_COMPRESSION_3Q 2 96 #define GFX6_COMPRESSION_4Q 3 97 #define GFX6_COMPRESSION_1H 0 98 #define GFX6_COMPRESSION_2H 2 99 100 enum ENUM_PACKED elk_conditional_mod { 101 ELK_CONDITIONAL_NONE = 0, 102 ELK_CONDITIONAL_Z = 1, 103 ELK_CONDITIONAL_NZ = 2, 104 ELK_CONDITIONAL_EQ = 1, /* Z */ 105 ELK_CONDITIONAL_NEQ = 2, /* NZ */ 106 ELK_CONDITIONAL_G = 3, 107 ELK_CONDITIONAL_GE = 4, 108 ELK_CONDITIONAL_L = 5, 109 ELK_CONDITIONAL_LE = 6, 110 ELK_CONDITIONAL_R = 7, /* Gen <= 5 */ 111 ELK_CONDITIONAL_O = 8, 112 ELK_CONDITIONAL_U = 9, 113 }; 114 115 #define ELK_DEBUG_NONE 0 116 #define ELK_DEBUG_BREAKPOINT 1 117 118 #define ELK_DEPENDENCY_NORMAL 0 119 #define ELK_DEPENDENCY_NOTCLEARED 1 120 #define ELK_DEPENDENCY_NOTCHECKED 2 121 #define ELK_DEPENDENCY_DISABLE 3 122 123 enum ENUM_PACKED elk_execution_size { 124 ELK_EXECUTE_1 = 0, 125 ELK_EXECUTE_2 = 1, 126 ELK_EXECUTE_4 = 2, 127 ELK_EXECUTE_8 = 3, 128 ELK_EXECUTE_16 = 4, 129 ELK_EXECUTE_32 = 5, 130 }; 131 132 enum ENUM_PACKED elk_horizontal_stride { 133 ELK_HORIZONTAL_STRIDE_0 = 0, 134 ELK_HORIZONTAL_STRIDE_1 = 1, 135 ELK_HORIZONTAL_STRIDE_2 = 2, 136 ELK_HORIZONTAL_STRIDE_4 = 3, 137 }; 138 139 enum ENUM_PACKED gfx10_align1_3src_src_horizontal_stride { 140 ELK_ALIGN1_3SRC_SRC_HORIZONTAL_STRIDE_0 = 0, 141 ELK_ALIGN1_3SRC_SRC_HORIZONTAL_STRIDE_1 = 1, 142 ELK_ALIGN1_3SRC_SRC_HORIZONTAL_STRIDE_2 = 2, 143 ELK_ALIGN1_3SRC_SRC_HORIZONTAL_STRIDE_4 = 3, 144 }; 145 146 enum ENUM_PACKED gfx10_align1_3src_dst_horizontal_stride { 147 ELK_ALIGN1_3SRC_DST_HORIZONTAL_STRIDE_1 = 0, 148 ELK_ALIGN1_3SRC_DST_HORIZONTAL_STRIDE_2 = 1, 149 }; 150 151 #define ELK_INSTRUCTION_NORMAL 0 152 #define ELK_INSTRUCTION_SATURATE 1 153 154 #define ELK_MASK_ENABLE 0 155 #define ELK_MASK_DISABLE 1 156 157 /** @{ 158 * 159 * Gfx6 has replaced "mask enable/disable" with WECtrl, which is 160 * effectively the same but much simpler to think about. Now, there 161 * are two contributors ANDed together to whether channels are 162 * executed: The predication on the instruction, and the channel write 163 * enable. 164 */ 165 /** 166 * This is the default value. It means that a channel's write enable is set 167 * if the per-channel IP is pointing at this instruction. 168 */ 169 #define ELK_WE_NORMAL 0 170 /** 171 * This is used like ELK_MASK_DISABLE, and causes all channels to have 172 * their write enable set. Note that predication still contributes to 173 * whether the channel actually gets written. 174 */ 175 #define ELK_WE_ALL 1 176 /** @} */ 177 178 enum elk_urb_write_flags { 179 ELK_URB_WRITE_NO_FLAGS = 0, 180 181 /** 182 * Causes a new URB entry to be allocated, and its address stored in the 183 * destination register (gen < 7). 184 */ 185 ELK_URB_WRITE_ALLOCATE = 0x1, 186 187 /** 188 * Causes the current URB entry to be deallocated (gen < 7). 189 */ 190 ELK_URB_WRITE_UNUSED = 0x2, 191 192 /** 193 * Causes the thread to terminate. 194 */ 195 ELK_URB_WRITE_EOT = 0x4, 196 197 /** 198 * Indicates that the given URB entry is complete, and may be sent further 199 * down the 3D pipeline (gen < 7). 200 */ 201 ELK_URB_WRITE_COMPLETE = 0x8, 202 203 /** 204 * Indicates that an additional offset (which may be different for the two 205 * vec4 slots) is stored in the message header (gen == 7). 206 */ 207 ELK_URB_WRITE_PER_SLOT_OFFSET = 0x10, 208 209 /** 210 * Indicates that the channel masks in the URB_WRITE message header should 211 * not be overridden to 0xff (gen == 7). 212 */ 213 ELK_URB_WRITE_USE_CHANNEL_MASKS = 0x20, 214 215 /** 216 * Indicates that the data should be sent to the URB using the 217 * URB_WRITE_OWORD message rather than URB_WRITE_HWORD (gen == 7). This 218 * causes offsets to be interpreted as multiples of an OWORD instead of an 219 * HWORD, and only allows one OWORD to be written. 220 */ 221 ELK_URB_WRITE_OWORD = 0x40, 222 223 /** 224 * Convenient combination of flags: end the thread while simultaneously 225 * marking the given URB entry as complete. 226 */ 227 ELK_URB_WRITE_EOT_COMPLETE = ELK_URB_WRITE_EOT | ELK_URB_WRITE_COMPLETE, 228 229 /** 230 * Convenient combination of flags: mark the given URB entry as complete 231 * and simultaneously allocate a new one. 232 */ 233 ELK_URB_WRITE_ALLOCATE_COMPLETE = 234 ELK_URB_WRITE_ALLOCATE | ELK_URB_WRITE_COMPLETE, 235 }; 236 237 enum fb_write_logical_srcs { 238 FB_WRITE_LOGICAL_SRC_COLOR0, /* REQUIRED */ 239 FB_WRITE_LOGICAL_SRC_COLOR1, /* for dual source blend messages */ 240 FB_WRITE_LOGICAL_SRC_SRC0_ALPHA, 241 FB_WRITE_LOGICAL_SRC_SRC_DEPTH, /* gl_FragDepth */ 242 FB_WRITE_LOGICAL_SRC_DST_DEPTH, /* GFX4-5: passthrough from thread */ 243 FB_WRITE_LOGICAL_SRC_OMASK, /* Sample Mask (gl_SampleMask) */ 244 FB_WRITE_LOGICAL_SRC_COMPONENTS, /* REQUIRED */ 245 FB_WRITE_LOGICAL_NUM_SRCS 246 }; 247 248 enum tex_logical_srcs { 249 /** Texture coordinates */ 250 TEX_LOGICAL_SRC_COORDINATE, 251 /** Shadow comparator */ 252 TEX_LOGICAL_SRC_SHADOW_C, 253 /** dPdx if the operation takes explicit derivatives, otherwise LOD value */ 254 TEX_LOGICAL_SRC_LOD, 255 /** dPdy if the operation takes explicit derivatives */ 256 TEX_LOGICAL_SRC_LOD2, 257 /** Min LOD */ 258 TEX_LOGICAL_SRC_MIN_LOD, 259 /** Sample index */ 260 TEX_LOGICAL_SRC_SAMPLE_INDEX, 261 /** MCS data */ 262 TEX_LOGICAL_SRC_MCS, 263 /** REQUIRED: Texture surface index */ 264 TEX_LOGICAL_SRC_SURFACE, 265 /** Texture sampler index */ 266 TEX_LOGICAL_SRC_SAMPLER, 267 /** Texture surface bindless handle */ 268 TEX_LOGICAL_SRC_SURFACE_HANDLE, 269 /** Texture sampler bindless handle */ 270 TEX_LOGICAL_SRC_SAMPLER_HANDLE, 271 /** Texel offset for gathers */ 272 TEX_LOGICAL_SRC_TG4_OFFSET, 273 /** REQUIRED: Number of coordinate components (as UD immediate) */ 274 TEX_LOGICAL_SRC_COORD_COMPONENTS, 275 /** REQUIRED: Number of derivative components (as UD immediate) */ 276 TEX_LOGICAL_SRC_GRAD_COMPONENTS, 277 /** REQUIRED: request residency (as UD immediate) */ 278 TEX_LOGICAL_SRC_RESIDENCY, 279 280 TEX_LOGICAL_NUM_SRCS, 281 }; 282 283 enum pull_uniform_constant_srcs { 284 /** Surface binding table index */ 285 PULL_UNIFORM_CONSTANT_SRC_SURFACE, 286 /** Surface bindless handle */ 287 PULL_UNIFORM_CONSTANT_SRC_SURFACE_HANDLE, 288 /** Surface offset */ 289 PULL_UNIFORM_CONSTANT_SRC_OFFSET, 290 /** Pull size */ 291 PULL_UNIFORM_CONSTANT_SRC_SIZE, 292 293 PULL_UNIFORM_CONSTANT_SRCS, 294 }; 295 296 enum pull_varying_constant_srcs { 297 /** Surface binding table index */ 298 PULL_VARYING_CONSTANT_SRC_SURFACE, 299 /** Surface bindless handle */ 300 PULL_VARYING_CONSTANT_SRC_SURFACE_HANDLE, 301 /** Surface offset */ 302 PULL_VARYING_CONSTANT_SRC_OFFSET, 303 /** Pull alignment */ 304 PULL_VARYING_CONSTANT_SRC_ALIGNMENT, 305 306 PULL_VARYING_CONSTANT_SRCS, 307 }; 308 309 enum get_buffer_size_srcs { 310 /** Surface binding table index */ 311 GET_BUFFER_SIZE_SRC_SURFACE, 312 /** Surface bindless handle */ 313 GET_BUFFER_SIZE_SRC_SURFACE_HANDLE, 314 /** LOD */ 315 GET_BUFFER_SIZE_SRC_LOD, 316 317 GET_BUFFER_SIZE_SRCS 318 }; 319 320 enum surface_logical_srcs { 321 /** Surface binding table index */ 322 SURFACE_LOGICAL_SRC_SURFACE, 323 /** Surface bindless handle */ 324 SURFACE_LOGICAL_SRC_SURFACE_HANDLE, 325 /** Surface address; could be multi-dimensional for typed opcodes */ 326 SURFACE_LOGICAL_SRC_ADDRESS, 327 /** Data to be written or used in an atomic op */ 328 SURFACE_LOGICAL_SRC_DATA, 329 /** Surface number of dimensions. Affects the size of ADDRESS */ 330 SURFACE_LOGICAL_SRC_IMM_DIMS, 331 /** Per-opcode immediate argument. For atomics, this is the atomic opcode */ 332 SURFACE_LOGICAL_SRC_IMM_ARG, 333 /** 334 * Some instructions with side-effects should not be predicated on 335 * sample mask, e.g. lowered stores to scratch. 336 */ 337 SURFACE_LOGICAL_SRC_ALLOW_SAMPLE_MASK, 338 339 SURFACE_LOGICAL_NUM_SRCS 340 }; 341 342 enum a64_logical_srcs { 343 /** Address the A64 message operates on */ 344 A64_LOGICAL_ADDRESS, 345 /** Source for the operation (unused of LOAD ops) */ 346 A64_LOGICAL_SRC, 347 /** Per-opcode immediate argument. Number of dwords, bit size, or atomic op. */ 348 A64_LOGICAL_ARG, 349 /** 350 * Some instructions do want to run on helper lanes (like ray queries). 351 */ 352 A64_LOGICAL_ENABLE_HELPERS, 353 354 A64_LOGICAL_NUM_SRCS 355 }; 356 357 enum urb_logical_srcs { 358 URB_LOGICAL_SRC_HANDLE, 359 URB_LOGICAL_SRC_PER_SLOT_OFFSETS, 360 URB_LOGICAL_SRC_CHANNEL_MASK, 361 /** Data to be written. BAD_FILE for reads. */ 362 URB_LOGICAL_SRC_DATA, 363 URB_LOGICAL_SRC_COMPONENTS, 364 URB_LOGICAL_NUM_SRCS 365 }; 366 367 enum interpolator_logical_srcs { 368 /** Interpolation offset */ 369 INTERP_SRC_OFFSET, 370 /** Message data */ 371 INTERP_SRC_MSG_DESC, 372 /** Flag register for dynamic mode */ 373 INTERP_SRC_DYNAMIC_MODE, 374 375 INTERP_NUM_SRCS 376 }; 377 378 379 #ifdef __cplusplus 380 /** 381 * Allow elk_urb_write_flags enums to be ORed together. 382 */ 383 inline elk_urb_write_flags 384 operator|(elk_urb_write_flags x, elk_urb_write_flags y) 385 { 386 return static_cast<elk_urb_write_flags>(static_cast<int>(x) | 387 static_cast<int>(y)); 388 } 389 #endif 390 391 enum ENUM_PACKED elk_predicate { 392 ELK_PREDICATE_NONE = 0, 393 ELK_PREDICATE_NORMAL = 1, 394 ELK_PREDICATE_ALIGN1_ANYV = 2, 395 ELK_PREDICATE_ALIGN1_ALLV = 3, 396 ELK_PREDICATE_ALIGN1_ANY2H = 4, 397 ELK_PREDICATE_ALIGN1_ALL2H = 5, 398 ELK_PREDICATE_ALIGN1_ANY4H = 6, 399 ELK_PREDICATE_ALIGN1_ALL4H = 7, 400 ELK_PREDICATE_ALIGN1_ANY8H = 8, 401 ELK_PREDICATE_ALIGN1_ALL8H = 9, 402 ELK_PREDICATE_ALIGN1_ANY16H = 10, 403 ELK_PREDICATE_ALIGN1_ALL16H = 11, 404 ELK_PREDICATE_ALIGN1_ANY32H = 12, 405 ELK_PREDICATE_ALIGN1_ALL32H = 13, 406 ELK_PREDICATE_ALIGN16_REPLICATE_X = 2, 407 ELK_PREDICATE_ALIGN16_REPLICATE_Y = 3, 408 ELK_PREDICATE_ALIGN16_REPLICATE_Z = 4, 409 ELK_PREDICATE_ALIGN16_REPLICATE_W = 5, 410 ELK_PREDICATE_ALIGN16_ANY4H = 6, 411 ELK_PREDICATE_ALIGN16_ALL4H = 7, 412 XE2_PREDICATE_ANY = 2, 413 XE2_PREDICATE_ALL = 3 414 }; 415 416 enum ENUM_PACKED elk_reg_file { 417 ELK_ARCHITECTURE_REGISTER_FILE = 0, 418 ELK_GENERAL_REGISTER_FILE = 1, 419 ELK_MESSAGE_REGISTER_FILE = 2, 420 ELK_IMMEDIATE_VALUE = 3, 421 422 ARF = ELK_ARCHITECTURE_REGISTER_FILE, 423 FIXED_GRF = ELK_GENERAL_REGISTER_FILE, 424 MRF = ELK_MESSAGE_REGISTER_FILE, 425 IMM = ELK_IMMEDIATE_VALUE, 426 427 /* These are not hardware values */ 428 VGRF, 429 ATTR, 430 UNIFORM, /* prog_data->params[reg] */ 431 BAD_FILE, 432 }; 433 434 enum ENUM_PACKED gfx10_align1_3src_reg_file { 435 ELK_ALIGN1_3SRC_GENERAL_REGISTER_FILE = 0, 436 ELK_ALIGN1_3SRC_IMMEDIATE_VALUE = 1, /* src0, src2 */ 437 ELK_ALIGN1_3SRC_ACCUMULATOR = 1, /* dest, src1 */ 438 }; 439 440 /* CNL adds Align1 support for 3-src instructions. Bit 35 of the instruction 441 * word is "Execution Datatype" which controls whether the instruction operates 442 * on float or integer types. The register arguments have fields that offer 443 * more fine control their respective types. 444 */ 445 enum ENUM_PACKED gfx10_align1_3src_exec_type { 446 ELK_ALIGN1_3SRC_EXEC_TYPE_INT = 0, 447 ELK_ALIGN1_3SRC_EXEC_TYPE_FLOAT = 1, 448 }; 449 450 #define ELK_ARF_NULL 0x00 451 #define ELK_ARF_ADDRESS 0x10 452 #define ELK_ARF_ACCUMULATOR 0x20 453 #define ELK_ARF_FLAG 0x30 454 #define ELK_ARF_MASK 0x40 455 #define ELK_ARF_MASK_STACK 0x50 456 #define ELK_ARF_MASK_STACK_DEPTH 0x60 457 #define ELK_ARF_STATE 0x70 458 #define ELK_ARF_CONTROL 0x80 459 #define ELK_ARF_NOTIFICATION_COUNT 0x90 460 #define ELK_ARF_IP 0xA0 461 #define ELK_ARF_TDR 0xB0 462 #define ELK_ARF_TIMESTAMP 0xC0 463 464 #define ELK_MRF_COMPR4 (1 << 7) 465 466 #define ELK_AMASK 0 467 #define ELK_IMASK 1 468 #define ELK_LMASK 2 469 #define ELK_CMASK 3 470 471 472 473 #define ELK_THREAD_NORMAL 0 474 #define ELK_THREAD_ATOMIC 1 475 #define ELK_THREAD_SWITCH 2 476 477 enum ENUM_PACKED elk_vertical_stride { 478 ELK_VERTICAL_STRIDE_0 = 0, 479 ELK_VERTICAL_STRIDE_1 = 1, 480 ELK_VERTICAL_STRIDE_2 = 2, 481 ELK_VERTICAL_STRIDE_4 = 3, 482 ELK_VERTICAL_STRIDE_8 = 4, 483 ELK_VERTICAL_STRIDE_16 = 5, 484 ELK_VERTICAL_STRIDE_32 = 6, 485 ELK_VERTICAL_STRIDE_ONE_DIMENSIONAL = 0xF, 486 }; 487 488 enum ENUM_PACKED gfx10_align1_3src_vertical_stride { 489 ELK_ALIGN1_3SRC_VERTICAL_STRIDE_0 = 0, 490 ELK_ALIGN1_3SRC_VERTICAL_STRIDE_1 = 1, 491 ELK_ALIGN1_3SRC_VERTICAL_STRIDE_2 = 1, 492 ELK_ALIGN1_3SRC_VERTICAL_STRIDE_4 = 2, 493 ELK_ALIGN1_3SRC_VERTICAL_STRIDE_8 = 3, 494 }; 495 496 enum ENUM_PACKED elk_width { 497 ELK_WIDTH_1 = 0, 498 ELK_WIDTH_2 = 1, 499 ELK_WIDTH_4 = 2, 500 ELK_WIDTH_8 = 3, 501 ELK_WIDTH_16 = 4, 502 }; 503 504 /** 505 * Message target: Shared Function ID for where to SEND a message. 506 * 507 * These are enumerated in the ISA reference under "send - Send Message". 508 * In particular, see the following tables: 509 * - G45 PRM, Volume 4, Table 14-15 "Message Descriptor Definition" 510 * - Sandybridge PRM, Volume 4 Part 2, Table 8-16 "Extended Message Descriptor" 511 * - Ivybridge PRM, Volume 1 Part 1, section 3.2.7 "GPE Function IDs" 512 */ 513 enum elk_message_target { 514 ELK_SFID_NULL = 0, 515 ELK_SFID_MATH = 1, /* Only valid on Gfx4-5 */ 516 ELK_SFID_SAMPLER = 2, 517 ELK_SFID_MESSAGE_GATEWAY = 3, 518 ELK_SFID_DATAPORT_READ = 4, 519 ELK_SFID_DATAPORT_WRITE = 5, 520 ELK_SFID_URB = 6, 521 ELK_SFID_THREAD_SPAWNER = 7, 522 ELK_SFID_VME = 8, 523 524 GFX6_SFID_DATAPORT_SAMPLER_CACHE = 4, 525 GFX6_SFID_DATAPORT_RENDER_CACHE = 5, 526 GFX6_SFID_DATAPORT_CONSTANT_CACHE = 9, 527 528 GFX7_SFID_DATAPORT_DATA_CACHE = 10, 529 GFX7_SFID_PIXEL_INTERPOLATOR = 11, 530 HSW_SFID_DATAPORT_DATA_CACHE_1 = 12, 531 HSW_SFID_CRE = 13, 532 }; 533 534 #define GFX7_MESSAGE_TARGET_DP_DATA_CACHE 10 535 536 #define ELK_SAMPLER_RETURN_FORMAT_FLOAT32 0 537 #define ELK_SAMPLER_RETURN_FORMAT_UINT32 2 538 #define ELK_SAMPLER_RETURN_FORMAT_SINT32 3 539 540 #define GFX8_SAMPLER_RETURN_FORMAT_32BITS 0 541 #define GFX8_SAMPLER_RETURN_FORMAT_16BITS 1 542 543 #define ELK_SAMPLER_MESSAGE_SIMD8_SAMPLE 0 544 #define ELK_SAMPLER_MESSAGE_SIMD16_SAMPLE 0 545 #define ELK_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS 0 546 #define ELK_SAMPLER_MESSAGE_SIMD8_KILLPIX 1 547 #define ELK_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD 1 548 #define ELK_SAMPLER_MESSAGE_SIMD16_SAMPLE_LOD 1 549 #define ELK_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_GRADIENTS 2 550 #define ELK_SAMPLER_MESSAGE_SIMD8_SAMPLE_GRADIENTS 2 551 #define ELK_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_COMPARE 0 552 #define ELK_SAMPLER_MESSAGE_SIMD16_SAMPLE_COMPARE 2 553 #define ELK_SAMPLER_MESSAGE_SIMD8_SAMPLE_BIAS_COMPARE 0 554 #define ELK_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD_COMPARE 1 555 #define ELK_SAMPLER_MESSAGE_SIMD8_SAMPLE_LOD_COMPARE 1 556 #define ELK_SAMPLER_MESSAGE_SIMD4X2_RESINFO 2 557 #define ELK_SAMPLER_MESSAGE_SIMD16_RESINFO 2 558 #define ELK_SAMPLER_MESSAGE_SIMD4X2_LD 3 559 #define ELK_SAMPLER_MESSAGE_SIMD8_LD 3 560 #define ELK_SAMPLER_MESSAGE_SIMD16_LD 3 561 562 #define GFX5_SAMPLER_MESSAGE_SAMPLE 0 563 #define GFX5_SAMPLER_MESSAGE_SAMPLE_BIAS 1 564 #define GFX5_SAMPLER_MESSAGE_SAMPLE_LOD 2 565 #define GFX5_SAMPLER_MESSAGE_SAMPLE_COMPARE 3 566 #define GFX5_SAMPLER_MESSAGE_SAMPLE_DERIVS 4 567 #define GFX5_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE 5 568 #define GFX5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE 6 569 #define GFX5_SAMPLER_MESSAGE_SAMPLE_LD 7 570 #define GFX7_SAMPLER_MESSAGE_SAMPLE_GATHER4 8 571 #define GFX5_SAMPLER_MESSAGE_LOD 9 572 #define GFX5_SAMPLER_MESSAGE_SAMPLE_RESINFO 10 573 #define GFX6_SAMPLER_MESSAGE_SAMPLE_SAMPLEINFO 11 574 #define GFX7_SAMPLER_MESSAGE_SAMPLE_GATHER4_C 16 575 #define GFX7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO 17 576 #define GFX7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO_C 18 577 #define HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE 20 578 #define GFX7_SAMPLER_MESSAGE_SAMPLE_LD_MCS 29 579 #define GFX7_SAMPLER_MESSAGE_SAMPLE_LD2DMS 30 580 #define GFX7_SAMPLER_MESSAGE_SAMPLE_LD2DSS 31 581 582 /* for GFX5 only */ 583 #define ELK_SAMPLER_SIMD_MODE_SIMD4X2 0 584 #define ELK_SAMPLER_SIMD_MODE_SIMD8 1 585 #define ELK_SAMPLER_SIMD_MODE_SIMD16 2 586 #define ELK_SAMPLER_SIMD_MODE_SIMD32_64 3 587 588 #define ELK_DATAPORT_OWORD_BLOCK_1_OWORDLOW 0 589 #define ELK_DATAPORT_OWORD_BLOCK_1_OWORDHIGH 1 590 #define ELK_DATAPORT_OWORD_BLOCK_2_OWORDS 2 591 #define ELK_DATAPORT_OWORD_BLOCK_4_OWORDS 3 592 #define ELK_DATAPORT_OWORD_BLOCK_8_OWORDS 4 593 #define ELK_DATAPORT_OWORD_BLOCK_OWORDS(n) \ 594 ((n) == 1 ? ELK_DATAPORT_OWORD_BLOCK_1_OWORDLOW : \ 595 (n) == 2 ? ELK_DATAPORT_OWORD_BLOCK_2_OWORDS : \ 596 (n) == 4 ? ELK_DATAPORT_OWORD_BLOCK_4_OWORDS : \ 597 (n) == 8 ? ELK_DATAPORT_OWORD_BLOCK_8_OWORDS : \ 598 (abort(), ~0)) 599 #define ELK_DATAPORT_OWORD_BLOCK_DWORDS(n) \ 600 ((n) == 4 ? ELK_DATAPORT_OWORD_BLOCK_1_OWORDLOW : \ 601 (n) == 8 ? ELK_DATAPORT_OWORD_BLOCK_2_OWORDS : \ 602 (n) == 16 ? ELK_DATAPORT_OWORD_BLOCK_4_OWORDS : \ 603 (n) == 32 ? ELK_DATAPORT_OWORD_BLOCK_8_OWORDS : \ 604 (abort(), ~0)) 605 606 #define ELK_DATAPORT_OWORD_DUAL_BLOCK_1OWORD 0 607 #define ELK_DATAPORT_OWORD_DUAL_BLOCK_4OWORDS 2 608 609 #define ELK_DATAPORT_DWORD_SCATTERED_BLOCK_8DWORDS 2 610 #define ELK_DATAPORT_DWORD_SCATTERED_BLOCK_16DWORDS 3 611 612 /* This one stays the same across generations. */ 613 #define ELK_DATAPORT_READ_MESSAGE_OWORD_BLOCK_READ 0 614 /* GFX4 */ 615 #define ELK_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ 1 616 #define ELK_DATAPORT_READ_MESSAGE_MEDIA_BLOCK_READ 2 617 #define ELK_DATAPORT_READ_MESSAGE_DWORD_SCATTERED_READ 3 618 /* G45, GFX5 */ 619 #define G45_DATAPORT_READ_MESSAGE_RENDER_UNORM_READ 1 620 #define G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ 2 621 #define G45_DATAPORT_READ_MESSAGE_AVC_LOOP_FILTER_READ 3 622 #define G45_DATAPORT_READ_MESSAGE_MEDIA_BLOCK_READ 4 623 #define G45_DATAPORT_READ_MESSAGE_DWORD_SCATTERED_READ 6 624 /* GFX6 */ 625 #define GFX6_DATAPORT_READ_MESSAGE_RENDER_UNORM_READ 1 626 #define GFX6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ 2 627 #define GFX6_DATAPORT_READ_MESSAGE_MEDIA_BLOCK_READ 4 628 #define GFX6_DATAPORT_READ_MESSAGE_OWORD_UNALIGN_BLOCK_READ 5 629 #define GFX6_DATAPORT_READ_MESSAGE_DWORD_SCATTERED_READ 6 630 631 #define ELK_DATAPORT_READ_TARGET_DATA_CACHE 0 632 #define ELK_DATAPORT_READ_TARGET_RENDER_CACHE 1 633 #define ELK_DATAPORT_READ_TARGET_SAMPLER_CACHE 2 634 635 #define ELK_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE 0 636 #define ELK_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE_REPLICATED 1 637 #define ELK_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN01 2 638 #define ELK_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN23 3 639 #define ELK_DATAPORT_RENDER_TARGET_WRITE_SIMD8_SINGLE_SOURCE_SUBSPAN01 4 640 641 #define ELK_DATAPORT_WRITE_MESSAGE_OWORD_BLOCK_WRITE 0 642 #define ELK_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE 1 643 #define ELK_DATAPORT_WRITE_MESSAGE_MEDIA_BLOCK_WRITE 2 644 #define ELK_DATAPORT_WRITE_MESSAGE_DWORD_SCATTERED_WRITE 3 645 #define ELK_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_WRITE 4 646 #define ELK_DATAPORT_WRITE_MESSAGE_STREAMED_VERTEX_BUFFER_WRITE 5 647 #define ELK_DATAPORT_WRITE_MESSAGE_FLUSH_RENDER_CACHE 7 648 649 /* GFX6 */ 650 #define GFX6_DATAPORT_WRITE_MESSAGE_DWORD_ATOMIC_WRITE 7 651 #define GFX6_DATAPORT_WRITE_MESSAGE_OWORD_BLOCK_WRITE 8 652 #define GFX6_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE 9 653 #define GFX6_DATAPORT_WRITE_MESSAGE_MEDIA_BLOCK_WRITE 10 654 #define GFX6_DATAPORT_WRITE_MESSAGE_DWORD_SCATTERED_WRITE 11 655 #define GFX6_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_WRITE 12 656 #define GFX6_DATAPORT_WRITE_MESSAGE_STREAMED_VB_WRITE 13 657 #define GFX6_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_UNORM_WRITE 14 658 659 /* GFX7 */ 660 #define GFX7_DATAPORT_RC_MEDIA_BLOCK_READ 4 661 #define GFX7_DATAPORT_RC_TYPED_SURFACE_READ 5 662 #define GFX7_DATAPORT_RC_TYPED_ATOMIC_OP 6 663 #define GFX7_DATAPORT_RC_MEMORY_FENCE 7 664 #define GFX7_DATAPORT_RC_MEDIA_BLOCK_WRITE 10 665 #define GFX7_DATAPORT_RC_RENDER_TARGET_WRITE 12 666 #define GFX7_DATAPORT_RC_TYPED_SURFACE_WRITE 13 667 #define GFX7_DATAPORT_DC_OWORD_BLOCK_READ 0 668 #define GFX7_DATAPORT_DC_UNALIGNED_OWORD_BLOCK_READ 1 669 #define GFX7_DATAPORT_DC_OWORD_DUAL_BLOCK_READ 2 670 #define GFX7_DATAPORT_DC_DWORD_SCATTERED_READ 3 671 #define GFX7_DATAPORT_DC_BYTE_SCATTERED_READ 4 672 #define GFX7_DATAPORT_DC_UNTYPED_SURFACE_READ 5 673 #define GFX7_DATAPORT_DC_UNTYPED_ATOMIC_OP 6 674 #define GFX7_DATAPORT_DC_MEMORY_FENCE 7 675 #define GFX7_DATAPORT_DC_OWORD_BLOCK_WRITE 8 676 #define GFX7_DATAPORT_DC_OWORD_DUAL_BLOCK_WRITE 10 677 #define GFX7_DATAPORT_DC_DWORD_SCATTERED_WRITE 11 678 #define GFX7_DATAPORT_DC_BYTE_SCATTERED_WRITE 12 679 #define GFX7_DATAPORT_DC_UNTYPED_SURFACE_WRITE 13 680 681 #define GFX7_DATAPORT_SCRATCH_READ ((1 << 18) | \ 682 (0 << 17)) 683 #define GFX7_DATAPORT_SCRATCH_WRITE ((1 << 18) | \ 684 (1 << 17)) 685 #define GFX7_DATAPORT_SCRATCH_NUM_REGS_SHIFT 12 686 687 #define GFX7_PIXEL_INTERPOLATOR_LOC_SHARED_OFFSET 0 688 #define GFX7_PIXEL_INTERPOLATOR_LOC_SAMPLE 1 689 #define GFX7_PIXEL_INTERPOLATOR_LOC_CENTROID 2 690 #define GFX7_PIXEL_INTERPOLATOR_LOC_PER_SLOT_OFFSET 3 691 692 /* HSW */ 693 #define HSW_DATAPORT_DC_PORT0_OWORD_BLOCK_READ 0 694 #define HSW_DATAPORT_DC_PORT0_UNALIGNED_OWORD_BLOCK_READ 1 695 #define HSW_DATAPORT_DC_PORT0_OWORD_DUAL_BLOCK_READ 2 696 #define HSW_DATAPORT_DC_PORT0_DWORD_SCATTERED_READ 3 697 #define HSW_DATAPORT_DC_PORT0_BYTE_SCATTERED_READ 4 698 #define HSW_DATAPORT_DC_PORT0_MEMORY_FENCE 7 699 #define HSW_DATAPORT_DC_PORT0_OWORD_BLOCK_WRITE 8 700 #define HSW_DATAPORT_DC_PORT0_OWORD_DUAL_BLOCK_WRITE 10 701 #define HSW_DATAPORT_DC_PORT0_DWORD_SCATTERED_WRITE 11 702 #define HSW_DATAPORT_DC_PORT0_BYTE_SCATTERED_WRITE 12 703 704 #define HSW_DATAPORT_DC_PORT1_UNTYPED_SURFACE_READ 1 705 #define HSW_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_OP 2 706 #define HSW_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_OP_SIMD4X2 3 707 #define HSW_DATAPORT_DC_PORT1_MEDIA_BLOCK_READ 4 708 #define HSW_DATAPORT_DC_PORT1_TYPED_SURFACE_READ 5 709 #define HSW_DATAPORT_DC_PORT1_TYPED_ATOMIC_OP 6 710 #define HSW_DATAPORT_DC_PORT1_TYPED_ATOMIC_OP_SIMD4X2 7 711 #define HSW_DATAPORT_DC_PORT1_UNTYPED_SURFACE_WRITE 9 712 #define HSW_DATAPORT_DC_PORT1_MEDIA_BLOCK_WRITE 10 713 #define HSW_DATAPORT_DC_PORT1_ATOMIC_COUNTER_OP 11 714 #define HSW_DATAPORT_DC_PORT1_ATOMIC_COUNTER_OP_SIMD4X2 12 715 #define HSW_DATAPORT_DC_PORT1_TYPED_SURFACE_WRITE 13 716 #define GFX9_DATAPORT_DC_PORT1_A64_SCATTERED_READ 0x10 717 #define GFX8_DATAPORT_DC_PORT1_A64_UNTYPED_SURFACE_READ 0x11 718 #define GFX8_DATAPORT_DC_PORT1_A64_UNTYPED_ATOMIC_OP 0x12 719 #define GFX8_DATAPORT_DC_PORT1_A64_OWORD_BLOCK_READ 0x14 720 #define GFX8_DATAPORT_DC_PORT1_A64_OWORD_BLOCK_WRITE 0x15 721 #define GFX8_DATAPORT_DC_PORT1_A64_UNTYPED_SURFACE_WRITE 0x19 722 #define GFX8_DATAPORT_DC_PORT1_A64_SCATTERED_WRITE 0x1a 723 724 /* A64 scattered message subtype */ 725 #define GFX8_A64_SCATTERED_SUBTYPE_BYTE 0 726 #define GFX8_A64_SCATTERED_SUBTYPE_DWORD 1 727 #define GFX8_A64_SCATTERED_SUBTYPE_QWORD 2 728 #define GFX8_A64_SCATTERED_SUBTYPE_HWORD 3 729 730 /* Dataport special binding table indices: */ 731 #define ELK_BTI_STATELESS 255 732 #define GFX7_BTI_SLM 254 733 734 #define HSW_BTI_STATELESS_LOCALLY_COHERENT 255 735 #define HSW_BTI_STATELESS_NON_COHERENT 253 736 #define HSW_BTI_STATELESS_GLOBALLY_COHERENT 252 737 #define HSW_BTI_STATELESS_LLC_COHERENT 251 738 #define HSW_BTI_STATELESS_L3_UNCACHED 250 739 740 /* The hardware docs are a bit contradictory here. On Haswell, where they 741 * first added cache ability control, there were 5 different cache modes (see 742 * HSW_BTI_STATELESS_* above). On Broadwell, they reduced to two: 743 * 744 * - IA-Coherent (BTI=255): Coherent within Gen and coherent within the 745 * entire IA cache memory hierarchy. 746 * 747 * - Non-Coherent (BTI=253): Coherent within Gen, same cache type. 748 * 749 * Information about stateless cache coherency can be found in the "A32 750 * Stateless" section of the "3D Media GPGPU" volume of the PRM for each 751 * hardware generation. 752 * 753 * Unfortunately, the docs for MDC_STATELESS appear to have been copied and 754 * pasted from Haswell and give the Haswell definitions for the BTI values of 755 * 255 and 253 including a warning about accessing 253 surfaces from multiple 756 * threads. This seems to be a copy+paste error and the definitions from the 757 * "A32 Stateless" section should be trusted instead. 758 * 759 * Note that because the DRM sets bit 4 of HDC_CHICKEN0 on BDW, CHV and at 760 * least some pre-production steppings of SKL due to WaForceEnableNonCoherent, 761 * HDC memory access may have been overridden by the kernel to be non-coherent 762 * (matching the behavior of the same BTI on pre-Gfx8 hardware) and BTI 255 763 * may actually be an alias for BTI 253. 764 */ 765 #define GFX8_BTI_STATELESS_IA_COHERENT 255 766 #define GFX8_BTI_STATELESS_NON_COHERENT 253 767 768 /* Dataport atomic operations for Untyped Atomic Integer Operation message 769 * (and others). 770 */ 771 #define ELK_AOP_AND 1 772 #define ELK_AOP_OR 2 773 #define ELK_AOP_XOR 3 774 #define ELK_AOP_MOV 4 775 #define ELK_AOP_INC 5 776 #define ELK_AOP_DEC 6 777 #define ELK_AOP_ADD 7 778 #define ELK_AOP_SUB 8 779 #define ELK_AOP_REVSUB 9 780 #define ELK_AOP_IMAX 10 781 #define ELK_AOP_IMIN 11 782 #define ELK_AOP_UMAX 12 783 #define ELK_AOP_UMIN 13 784 #define ELK_AOP_CMPWR 14 785 #define ELK_AOP_PREDEC 15 786 787 /* Dataport atomic operations for Untyped Atomic Float Operation message. */ 788 #define ELK_AOP_FMAX 1 789 #define ELK_AOP_FMIN 2 790 #define ELK_AOP_FCMPWR 3 791 #define ELK_AOP_FADD 4 792 793 #define ELK_MATH_FUNCTION_INV 1 794 #define ELK_MATH_FUNCTION_LOG 2 795 #define ELK_MATH_FUNCTION_EXP 3 796 #define ELK_MATH_FUNCTION_SQRT 4 797 #define ELK_MATH_FUNCTION_RSQ 5 798 #define ELK_MATH_FUNCTION_SIN 6 799 #define ELK_MATH_FUNCTION_COS 7 800 #define ELK_MATH_FUNCTION_SINCOS 8 /* gfx4, gfx5 */ 801 #define ELK_MATH_FUNCTION_FDIV 9 /* gfx6+ */ 802 #define ELK_MATH_FUNCTION_POW 10 803 #define ELK_MATH_FUNCTION_INT_DIV_QUOTIENT_AND_REMAINDER 11 804 #define ELK_MATH_FUNCTION_INT_DIV_QUOTIENT 12 805 #define ELK_MATH_FUNCTION_INT_DIV_REMAINDER 13 806 #define GFX8_MATH_FUNCTION_INVM 14 807 #define GFX8_MATH_FUNCTION_RSQRTM 15 808 809 #define ELK_MATH_INTEGER_UNSIGNED 0 810 #define ELK_MATH_INTEGER_SIGNED 1 811 812 #define ELK_MATH_PRECISION_FULL 0 813 #define ELK_MATH_PRECISION_PARTIAL 1 814 815 #define ELK_MATH_SATURATE_NONE 0 816 #define ELK_MATH_SATURATE_SATURATE 1 817 818 #define ELK_MATH_DATA_VECTOR 0 819 #define ELK_MATH_DATA_SCALAR 1 820 821 #define ELK_URB_OPCODE_WRITE_HWORD 0 822 #define ELK_URB_OPCODE_WRITE_OWORD 1 823 #define ELK_URB_OPCODE_READ_HWORD 2 824 #define ELK_URB_OPCODE_READ_OWORD 3 825 #define GFX7_URB_OPCODE_ATOMIC_MOV 4 826 #define GFX7_URB_OPCODE_ATOMIC_INC 5 827 #define GFX8_URB_OPCODE_ATOMIC_ADD 6 828 #define GFX8_URB_OPCODE_SIMD8_WRITE 7 829 #define GFX8_URB_OPCODE_SIMD8_READ 8 830 831 #define ELK_URB_SWIZZLE_NONE 0 832 #define ELK_URB_SWIZZLE_INTERLEAVE 1 833 #define ELK_URB_SWIZZLE_TRANSPOSE 2 834 835 #define ELK_SCRATCH_SPACE_SIZE_1K 0 836 #define ELK_SCRATCH_SPACE_SIZE_2K 1 837 #define ELK_SCRATCH_SPACE_SIZE_4K 2 838 #define ELK_SCRATCH_SPACE_SIZE_8K 3 839 #define ELK_SCRATCH_SPACE_SIZE_16K 4 840 #define ELK_SCRATCH_SPACE_SIZE_32K 5 841 #define ELK_SCRATCH_SPACE_SIZE_64K 6 842 #define ELK_SCRATCH_SPACE_SIZE_128K 7 843 #define ELK_SCRATCH_SPACE_SIZE_256K 8 844 #define ELK_SCRATCH_SPACE_SIZE_512K 9 845 #define ELK_SCRATCH_SPACE_SIZE_1M 10 846 #define ELK_SCRATCH_SPACE_SIZE_2M 11 847 848 #define ELK_MESSAGE_GATEWAY_SFID_OPEN_GATEWAY 0 849 #define ELK_MESSAGE_GATEWAY_SFID_CLOSE_GATEWAY 1 850 #define ELK_MESSAGE_GATEWAY_SFID_FORWARD_MSG 2 851 #define ELK_MESSAGE_GATEWAY_SFID_GET_TIMESTAMP 3 852 #define ELK_MESSAGE_GATEWAY_SFID_BARRIER_MSG 4 853 #define ELK_MESSAGE_GATEWAY_SFID_UPDATE_GATEWAY_STATE 5 854 #define ELK_MESSAGE_GATEWAY_SFID_MMIO_READ_WRITE 6 855 856 857 /* Gfx7 "GS URB Entry Allocation Size" is a U9-1 field, so the maximum gs_size 858 * is 2^9, or 512. It's counted in multiples of 64 bytes. 859 * 860 * Identical for VS, DS, and HS. 861 */ 862 #define GFX7_MAX_GS_URB_ENTRY_SIZE_BYTES (512*64) 863 #define GFX7_MAX_DS_URB_ENTRY_SIZE_BYTES (512*64) 864 #define GFX7_MAX_HS_URB_ENTRY_SIZE_BYTES (512*64) 865 #define GFX7_MAX_VS_URB_ENTRY_SIZE_BYTES (512*64) 866 867 #define ELK_GS_EDGE_INDICATOR_0 (1 << 8) 868 #define ELK_GS_EDGE_INDICATOR_1 (1 << 9) 869 870 /* Gfx6 "GS URB Entry Allocation Size" is defined as a number of 1024-bit 871 * (128 bytes) URB rows and the maximum allowed value is 5 rows. 872 */ 873 #define GFX6_MAX_GS_URB_ENTRY_SIZE_BYTES (5*128) 874 875 /* GS Thread Payload 876 */ 877 878 /* 3DSTATE_GS "Output Vertex Size" has an effective maximum of 62. It's 879 * counted in multiples of 16 bytes. 880 */ 881 #define GFX7_MAX_GS_OUTPUT_VERTEX_SIZE_BYTES (62*16) 882 883 884 /* R0 */ 885 # define GFX7_GS_PAYLOAD_INSTANCE_ID_SHIFT 27 886 887 /* CR0.0[5:4] Floating-Point Rounding Modes 888 * Skylake PRM, Volume 7 Part 1, "Control Register", page 756 889 */ 890 891 #define ELK_CR0_RND_MODE_MASK 0x30 892 #define ELK_CR0_RND_MODE_SHIFT 4 893 894 enum ENUM_PACKED elk_rnd_mode { 895 ELK_RND_MODE_RTNE = 0, /* Round to Nearest or Even */ 896 ELK_RND_MODE_RU = 1, /* Round Up, toward +inf */ 897 ELK_RND_MODE_RD = 2, /* Round Down, toward -inf */ 898 ELK_RND_MODE_RTZ = 3, /* Round Toward Zero */ 899 ELK_RND_MODE_UNSPECIFIED, /* Unspecified rounding mode */ 900 }; 901 902 #define ELK_CR0_FP64_DENORM_PRESERVE (1 << 6) 903 #define ELK_CR0_FP32_DENORM_PRESERVE (1 << 7) 904 #define ELK_CR0_FP16_DENORM_PRESERVE (1 << 10) 905 906 #define ELK_CR0_FP_MODE_MASK (ELK_CR0_FP64_DENORM_PRESERVE | \ 907 ELK_CR0_FP32_DENORM_PRESERVE | \ 908 ELK_CR0_FP16_DENORM_PRESERVE | \ 909 ELK_CR0_RND_MODE_MASK) 910 911 /* MDC_DS - Data Size Message Descriptor Control Field 912 * Skylake PRM, Volume 2d, page 129 913 * 914 * Specifies the number of Bytes to be read or written per Dword used at 915 * byte_scattered read/write and byte_scaled read/write messages. 916 */ 917 #define GFX7_BYTE_SCATTERED_DATA_ELEMENT_BYTE 0 918 #define GFX7_BYTE_SCATTERED_DATA_ELEMENT_WORD 1 919 #define GFX7_BYTE_SCATTERED_DATA_ELEMENT_DWORD 2 920 921 /* Starting with Xe-HPG, the old dataport was massively reworked dataport. 922 * The new thing, called Load/Store Cache or LSC, has a significantly improved 923 * interface. Instead of bespoke messages for every case, there's basically 924 * one or two messages with different bits to control things like address 925 * size, how much data is read/written, etc. It's way nicer but also means we 926 * get to rewrite all our dataport encoding/decoding code. This patch kicks 927 * off the party with all of the new enums. 928 */ 929 enum elk_lsc_opcode { 930 LSC_OP_LOAD = 0, 931 LSC_OP_LOAD_CMASK = 2, 932 LSC_OP_STORE = 4, 933 LSC_OP_STORE_CMASK = 6, 934 LSC_OP_ATOMIC_INC = 8, 935 LSC_OP_ATOMIC_DEC = 9, 936 LSC_OP_ATOMIC_LOAD = 10, 937 LSC_OP_ATOMIC_STORE = 11, 938 LSC_OP_ATOMIC_ADD = 12, 939 LSC_OP_ATOMIC_SUB = 13, 940 LSC_OP_ATOMIC_MIN = 14, 941 LSC_OP_ATOMIC_MAX = 15, 942 LSC_OP_ATOMIC_UMIN = 16, 943 LSC_OP_ATOMIC_UMAX = 17, 944 LSC_OP_ATOMIC_CMPXCHG = 18, 945 LSC_OP_ATOMIC_FADD = 19, 946 LSC_OP_ATOMIC_FSUB = 20, 947 LSC_OP_ATOMIC_FMIN = 21, 948 LSC_OP_ATOMIC_FMAX = 22, 949 LSC_OP_ATOMIC_FCMPXCHG = 23, 950 LSC_OP_ATOMIC_AND = 24, 951 LSC_OP_ATOMIC_OR = 25, 952 LSC_OP_ATOMIC_XOR = 26, 953 LSC_OP_FENCE = 31 954 }; 955 956 /* 957 * Specifies the size of the dataport address payload in registers. 958 */ 959 enum ENUM_PACKED lsc_addr_reg_size { 960 LSC_ADDR_REG_SIZE_1 = 1, 961 LSC_ADDR_REG_SIZE_2 = 2, 962 LSC_ADDR_REG_SIZE_3 = 3, 963 LSC_ADDR_REG_SIZE_4 = 4, 964 LSC_ADDR_REG_SIZE_6 = 6, 965 LSC_ADDR_REG_SIZE_8 = 8, 966 }; 967 968 /* 969 * Specifies the size of the address payload item in a dataport message. 970 */ 971 enum ENUM_PACKED lsc_addr_size { 972 LSC_ADDR_SIZE_A16 = 1, /* 16-bit address offset */ 973 LSC_ADDR_SIZE_A32 = 2, /* 32-bit address offset */ 974 LSC_ADDR_SIZE_A64 = 3, /* 64-bit address offset */ 975 }; 976 977 /* 978 * Specifies the type of the address payload item in a dataport message. The 979 * address type specifies how the dataport message decodes the Extended 980 * Descriptor for the surface attributes and address calculation. 981 */ 982 enum ENUM_PACKED lsc_addr_surface_type { 983 LSC_ADDR_SURFTYPE_FLAT = 0, /* Flat */ 984 LSC_ADDR_SURFTYPE_BSS = 1, /* Bindless surface state */ 985 LSC_ADDR_SURFTYPE_SS = 2, /* Surface state */ 986 LSC_ADDR_SURFTYPE_BTI = 3, /* Binding table index */ 987 }; 988 989 /* 990 * Specifies the dataport message override to the default L1 and L3 memory 991 * cache policies. Dataport L1 cache policies are uncached (UC), cached (C), 992 * cache streaming (S) and invalidate-after-read (IAR). Dataport L3 cache 993 * policies are uncached (UC) and cached (C). 994 */ 995 enum lsc_cache_load { 996 /* No override. Use the non-pipelined state or surface state cache settings 997 * for L1 and L3. 998 */ 999 LSC_CACHE_LOAD_L1STATE_L3MOCS = 0, 1000 /* Override to L1 uncached and L3 uncached */ 1001 LSC_CACHE_LOAD_L1UC_L3UC = 1, 1002 /* Override to L1 uncached and L3 cached */ 1003 LSC_CACHE_LOAD_L1UC_L3C = 2, 1004 /* Override to L1 cached and L3 uncached */ 1005 LSC_CACHE_LOAD_L1C_L3UC = 3, 1006 /* Override to cache at both L1 and L3 */ 1007 LSC_CACHE_LOAD_L1C_L3C = 4, 1008 /* Override to L1 streaming load and L3 uncached */ 1009 LSC_CACHE_LOAD_L1S_L3UC = 5, 1010 /* Override to L1 streaming load and L3 cached */ 1011 LSC_CACHE_LOAD_L1S_L3C = 6, 1012 /* For load messages, override to L1 invalidate-after-read, and L3 cached. */ 1013 LSC_CACHE_LOAD_L1IAR_L3C = 7, 1014 }; 1015 1016 /* 1017 * Specifies the dataport message override to the default L1 and L3 memory 1018 * cache policies. Dataport L1 cache policies are uncached (UC), cached (C), 1019 * streaming (S) and invalidate-after-read (IAR). Dataport L3 cache policies 1020 * are uncached (UC), cached (C), cached-as-a-constand (CC) and 1021 * invalidate-after-read (IAR). 1022 */ 1023 enum PACKED xe2_lsc_cache_load { 1024 /* No override. Use the non-pipelined or surface state cache settings for L1 1025 * and L3. 1026 */ 1027 XE2_LSC_CACHE_LOAD_L1STATE_L3MOCS = 0, 1028 /* Override to L1 uncached and L3 uncached */ 1029 XE2_LSC_CACHE_LOAD_L1UC_L3UC = 2, 1030 /* Override to L1 uncached and L3 cached */ 1031 XE2_LSC_CACHE_LOAD_L1UC_L3C = 4, 1032 /* Override to L1 uncached and L3 cached as a constant */ 1033 XE2_LSC_CACHE_LOAD_L1UC_L3CC = 5, 1034 /* Override to L1 cached and L3 uncached */ 1035 XE2_LSC_CACHE_LOAD_L1C_L3UC = 6, 1036 /* Override to L1 cached and L3 cached */ 1037 XE2_LSC_CACHE_LOAD_L1C_L3C = 8, 1038 /* Override to L1 cached and L3 cached as a constant */ 1039 XE2_LSC_CACHE_LOAD_L1C_L3CC = 9, 1040 /* Override to L1 cached as streaming load and L3 uncached */ 1041 XE2_LSC_CACHE_LOAD_L1S_L3UC = 10, 1042 /* Override to L1 cached as streaming load and L3 cached */ 1043 XE2_LSC_CACHE_LOAD_L1S_L3C = 12, 1044 /* Override to L1 and L3 invalidate after read */ 1045 XE2_LSC_CACHE_LOAD_L1IAR_L3IAR = 14, 1046 1047 }; 1048 1049 /* 1050 * Specifies the dataport message override to the default L1 and L3 memory 1051 * cache policies. Dataport L1 cache policies are uncached (UC), write-through 1052 * (WT), write-back (WB) and streaming (S). Dataport L3 cache policies are 1053 * uncached (UC) and cached (WB). 1054 */ 1055 enum ENUM_PACKED lsc_cache_store { 1056 /* No override. Use the non-pipelined or surface state cache settings for L1 1057 * and L3. 1058 */ 1059 LSC_CACHE_STORE_L1STATE_L3MOCS = 0, 1060 /* Override to L1 uncached and L3 uncached */ 1061 LSC_CACHE_STORE_L1UC_L3UC = 1, 1062 /* Override to L1 uncached and L3 cached */ 1063 LSC_CACHE_STORE_L1UC_L3WB = 2, 1064 /* Override to L1 write-through and L3 uncached */ 1065 LSC_CACHE_STORE_L1WT_L3UC = 3, 1066 /* Override to L1 write-through and L3 cached */ 1067 LSC_CACHE_STORE_L1WT_L3WB = 4, 1068 /* Override to L1 streaming and L3 uncached */ 1069 LSC_CACHE_STORE_L1S_L3UC = 5, 1070 /* Override to L1 streaming and L3 cached */ 1071 LSC_CACHE_STORE_L1S_L3WB = 6, 1072 /* Override to L1 write-back, and L3 cached */ 1073 LSC_CACHE_STORE_L1WB_L3WB = 7, 1074 1075 }; 1076 1077 /* 1078 * Specifies the dataport message override to the default L1 and L3 memory 1079 * cache policies. Dataport L1 cache policies are uncached (UC), write-through 1080 * (WT), write-back (WB) and streaming (S). Dataport L3 cache policies are 1081 * uncached (UC) and cached (WB). 1082 */ 1083 enum PACKED xe2_lsc_cache_store { 1084 /* No override. Use the non-pipelined or surface state cache settings for L1 1085 * and L3. 1086 */ 1087 XE2_LSC_CACHE_STORE_L1STATE_L3MOCS = 0, 1088 /* Override to L1 uncached and L3 uncached */ 1089 XE2_LSC_CACHE_STORE_L1UC_L3UC = 2, 1090 /* Override to L1 uncached and L3 cached */ 1091 XE2_LSC_CACHE_STORE_L1UC_L3WB = 4, 1092 /* Override to L1 write-through and L3 uncached */ 1093 XE2_LSC_CACHE_STORE_L1WT_L3UC = 6, 1094 /* Override to L1 write-through and L3 cached */ 1095 XE2_LSC_CACHE_STORE_L1WT_L3WB = 8, 1096 /* Override to L1 streaming and L3 uncached */ 1097 XE2_LSC_CACHE_STORE_L1S_L3UC = 10, 1098 /* Override to L1 streaming and L3 cached */ 1099 XE2_LSC_CACHE_STORE_L1S_L3WB = 12, 1100 /* Override to L1 write-back and L3 cached */ 1101 XE2_LSC_CACHE_STORE_L1WB_L3WB = 14, 1102 1103 }; 1104 1105 #define LSC_CACHE(devinfo, l_or_s, cc) \ 1106 ((devinfo)->ver < 20 ? (unsigned)LSC_CACHE_ ## l_or_s ## _ ## cc : \ 1107 (unsigned)XE2_LSC_CACHE_ ## l_or_s ## _ ## cc) 1108 1109 /* 1110 * Specifies which components of the data payload 4-element vector (X,Y,Z,W) is 1111 * packed into the register payload. 1112 */ 1113 enum ENUM_PACKED lsc_cmask { 1114 LSC_CMASK_X = 0x1, 1115 LSC_CMASK_Y = 0x2, 1116 LSC_CMASK_XY = 0x3, 1117 LSC_CMASK_Z = 0x4, 1118 LSC_CMASK_XZ = 0x5, 1119 LSC_CMASK_YZ = 0x6, 1120 LSC_CMASK_XYZ = 0x7, 1121 LSC_CMASK_W = 0x8, 1122 LSC_CMASK_XW = 0x9, 1123 LSC_CMASK_YW = 0xa, 1124 LSC_CMASK_XYW = 0xb, 1125 LSC_CMASK_ZW = 0xc, 1126 LSC_CMASK_XZW = 0xd, 1127 LSC_CMASK_YZW = 0xe, 1128 LSC_CMASK_XYZW = 0xf, 1129 }; 1130 1131 /* 1132 * Specifies the size of the data payload item in a dataport message. 1133 */ 1134 enum ENUM_PACKED lsc_data_size { 1135 /* 8-bit scalar data value in memory, packed into a 8-bit data value in 1136 * register. 1137 */ 1138 LSC_DATA_SIZE_D8 = 0, 1139 /* 16-bit scalar data value in memory, packed into a 16-bit data value in 1140 * register. 1141 */ 1142 LSC_DATA_SIZE_D16 = 1, 1143 /* 32-bit scalar data value in memory, packed into 32-bit data value in 1144 * register. 1145 */ 1146 LSC_DATA_SIZE_D32 = 2, 1147 /* 64-bit scalar data value in memory, packed into 64-bit data value in 1148 * register. 1149 */ 1150 LSC_DATA_SIZE_D64 = 3, 1151 /* 8-bit scalar data value in memory, packed into 32-bit unsigned data value 1152 * in register. 1153 */ 1154 LSC_DATA_SIZE_D8U32 = 4, 1155 /* 16-bit scalar data value in memory, packed into 32-bit unsigned data 1156 * value in register. 1157 */ 1158 LSC_DATA_SIZE_D16U32 = 5, 1159 /* 16-bit scalar BigFloat data value in memory, packed into 32-bit float 1160 * value in register. 1161 */ 1162 LSC_DATA_SIZE_D16BF32 = 6, 1163 }; 1164 1165 /* 1166 * Enum specifies the scope of the fence. 1167 */ 1168 enum ENUM_PACKED lsc_fence_scope { 1169 /* Wait until all previous memory transactions from this thread are observed 1170 * within the local thread-group. 1171 */ 1172 LSC_FENCE_THREADGROUP = 0, 1173 /* Wait until all previous memory transactions from this thread are observed 1174 * within the local sub-slice. 1175 */ 1176 LSC_FENCE_LOCAL = 1, 1177 /* Wait until all previous memory transactions from this thread are observed 1178 * in the local tile. 1179 */ 1180 LSC_FENCE_TILE = 2, 1181 /* Wait until all previous memory transactions from this thread are observed 1182 * in the local GPU. 1183 */ 1184 LSC_FENCE_GPU = 3, 1185 /* Wait until all previous memory transactions from this thread are observed 1186 * across all GPUs in the system. 1187 */ 1188 LSC_FENCE_ALL_GPU = 4, 1189 /* Wait until all previous memory transactions from this thread are observed 1190 * at the "system" level. 1191 */ 1192 LSC_FENCE_SYSTEM_RELEASE = 5, 1193 /* For GPUs that do not follow PCIe Write ordering for downstream writes 1194 * targeting device memory, a fence message with scope=System_Acquire will 1195 * commit to device memory all downstream and peer writes that have reached 1196 * the device. 1197 */ 1198 LSC_FENCE_SYSTEM_ACQUIRE = 6, 1199 }; 1200 1201 /* 1202 * Specifies the type of cache flush operation to perform after a fence is 1203 * complete. 1204 */ 1205 enum ENUM_PACKED lsc_flush_type { 1206 LSC_FLUSH_TYPE_NONE = 0, 1207 /* 1208 * For a R/W cache, evict dirty lines (M to I state) and invalidate clean 1209 * lines. For a RO cache, invalidate clean lines. 1210 */ 1211 LSC_FLUSH_TYPE_EVICT = 1, 1212 /* 1213 * For both R/W and RO cache, invalidate clean lines in the cache. 1214 */ 1215 LSC_FLUSH_TYPE_INVALIDATE = 2, 1216 /* 1217 * For a R/W cache, invalidate dirty lines (M to I state), without 1218 * write-back to next level. This opcode does nothing for a RO cache. 1219 */ 1220 LSC_FLUSH_TYPE_DISCARD = 3, 1221 /* 1222 * For a R/W cache, write-back dirty lines to the next level, but kept in 1223 * the cache as "clean" (M to V state). This opcode does nothing for a RO 1224 * cache. 1225 */ 1226 LSC_FLUSH_TYPE_CLEAN = 4, 1227 /* 1228 * Flush "RW" section of the L3 cache, but leave L1 and L2 caches untouched. 1229 */ 1230 LSC_FLUSH_TYPE_L3ONLY = 5, 1231 /* 1232 * HW maps this flush type internally to NONE. 1233 */ 1234 LSC_FLUSH_TYPE_NONE_6 = 6, 1235 1236 }; 1237 1238 enum ENUM_PACKED lsc_backup_fence_routing { 1239 /* Normal routing: UGM fence is routed to UGM pipeline. */ 1240 LSC_NORMAL_ROUTING, 1241 /* Route UGM fence to LSC unit. */ 1242 LSC_ROUTE_TO_LSC, 1243 }; 1244 1245 /* 1246 * Specifies the size of the vector in a dataport message. 1247 */ 1248 enum ENUM_PACKED lsc_vect_size { 1249 LSC_VECT_SIZE_V1 = 0, /* vector length 1 */ 1250 LSC_VECT_SIZE_V2 = 1, /* vector length 2 */ 1251 LSC_VECT_SIZE_V3 = 2, /* Vector length 3 */ 1252 LSC_VECT_SIZE_V4 = 3, /* Vector length 4 */ 1253 LSC_VECT_SIZE_V8 = 4, /* Vector length 8 */ 1254 LSC_VECT_SIZE_V16 = 5, /* Vector length 16 */ 1255 LSC_VECT_SIZE_V32 = 6, /* Vector length 32 */ 1256 LSC_VECT_SIZE_V64 = 7, /* Vector length 64 */ 1257 }; 1258 1259 #define LSC_ONE_ADDR_REG 1 1260 1261 #endif /* ELK_EU_DEFINES_H */ 1262