1 /*
2 * Copyright © 2014 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 /**
25 * @file
26 *
27 * A representation of i965 EU assembly instructions, with helper methods to
28 * get and set various fields. This is the actual hardware format.
29 */
30
31 #ifndef BRW_INST_H
32 #define BRW_INST_H
33
34 #include <assert.h>
35 #include <stdint.h>
36
37 #include "brw_eu_defines.h"
38 #include "brw_isa_info.h"
39 #include "brw_reg_type.h"
40 #include "dev/intel_device_info.h"
41
42 #ifdef __cplusplus
43 extern "C" {
44 #endif
45
46 /* brw_context.h has a forward declaration of brw_inst, so name the struct. */
47 typedef struct brw_inst {
48 uint64_t data[2];
49 } brw_inst;
50
51 static inline uint64_t brw_inst_bits(const brw_inst *inst,
52 unsigned high, unsigned low);
53 static inline void brw_inst_set_bits(brw_inst *inst,
54 unsigned high, unsigned low,
55 uint64_t value);
56
57 #define FC(name, hi9, lo9, hi12, lo12, assertions) \
58 static inline void \
59 brw_inst_set_##name(const struct intel_device_info *devinfo, \
60 brw_inst *inst, uint64_t v) \
61 { \
62 assert(assertions); \
63 if (devinfo->ver >= 12) \
64 brw_inst_set_bits(inst, hi12, lo12, v); \
65 else \
66 brw_inst_set_bits(inst, hi9, lo9, v); \
67 } \
68 static inline uint64_t \
69 brw_inst_##name(const struct intel_device_info *devinfo, \
70 const brw_inst *inst) \
71 { \
72 assert(assertions); \
73 if (devinfo->ver >= 12) \
74 return brw_inst_bits(inst, hi12, lo12); \
75 else \
76 return brw_inst_bits(inst, hi9, lo9); \
77 }
78
79 /* A simple macro for fields which stay in the same place on all generations,
80 * except for Gfx12!
81 */
82 #define F(name, hi9, lo9, hi12, lo12) FC(name, hi9, lo9, hi12, lo12, true)
83
84 /* A simple macro for fields which stay in the same place on all generations,
85 * except for Gfx12 and Gfx20.
86 */
87 #define F20(name, hi9, lo9, hi12, lo12, hi20, lo20) \
88 static inline void \
89 brw_inst_set_##name(const struct intel_device_info *devinfo, \
90 brw_inst *inst, uint64_t v) \
91 { \
92 if (devinfo->ver >= 20) \
93 brw_inst_set_bits(inst, hi20, lo20, v); \
94 else if (devinfo->ver >= 12) \
95 brw_inst_set_bits(inst, hi12, lo12, v); \
96 else \
97 brw_inst_set_bits(inst, hi9, lo9, v); \
98 } \
99 static inline uint64_t \
100 brw_inst_##name(const struct intel_device_info *devinfo, \
101 const brw_inst *inst) \
102 { \
103 if (devinfo->ver >= 20) \
104 return brw_inst_bits(inst, hi20, lo20); \
105 else if (devinfo->ver >= 12) \
106 return brw_inst_bits(inst, hi12, lo12); \
107 else \
108 return brw_inst_bits(inst, hi9, lo9); \
109 }
110
111 #define FV20(name, hi9, lo9, hi12, lo12, hi20, lo20) \
112 static inline void \
113 brw_inst_set_##name(const struct intel_device_info *devinfo, \
114 brw_inst *inst, uint64_t v) \
115 { \
116 if (devinfo->ver >= 20) \
117 brw_inst_set_bits(inst, hi20, lo20, v & 0x7); \
118 else if (devinfo->ver >= 12) \
119 brw_inst_set_bits(inst, hi12, lo12, v); \
120 else \
121 brw_inst_set_bits(inst, hi9, lo9, v); \
122 } \
123 static inline uint64_t \
124 brw_inst_##name(const struct intel_device_info *devinfo, \
125 const brw_inst *inst) \
126 { \
127 if (devinfo->ver >= 20) \
128 return brw_inst_bits(inst, hi20, lo20) == 0x7 ? 0xF : \
129 brw_inst_bits(inst, hi20, lo20); \
130 else if (devinfo->ver >= 12) \
131 return brw_inst_bits(inst, hi12, lo12); \
132 else \
133 return brw_inst_bits(inst, hi9, lo9); \
134 }
135
136 #define FD20(name, hi9, lo9, hi12, lo12, hi20, lo20, zero20) \
137 static inline void \
138 brw_inst_set_##name(const struct intel_device_info *devinfo, \
139 brw_inst *inst, uint64_t v) \
140 { \
141 if (devinfo->ver >= 20) { \
142 brw_inst_set_bits(inst, hi20, lo20, v >> 1); \
143 if (zero20 == -1) \
144 assert((v & 1) == 0); \
145 else \
146 brw_inst_set_bits(inst, zero20, zero20, v & 1); \
147 } else if (devinfo->ver >= 12) \
148 brw_inst_set_bits(inst, hi12, lo12, v); \
149 else \
150 brw_inst_set_bits(inst, hi9, lo9, v); \
151 } \
152 static inline uint64_t \
153 brw_inst_##name(const struct intel_device_info *devinfo, \
154 const brw_inst *inst) \
155 { \
156 if (devinfo->ver >= 20) \
157 return (brw_inst_bits(inst, hi20, lo20) << 1) | \
158 (zero20 == -1 ? 0 : \
159 brw_inst_bits(inst, zero20, zero20)); \
160 else if (devinfo->ver >= 12) \
161 return brw_inst_bits(inst, hi12, lo12); \
162 else \
163 return brw_inst_bits(inst, hi9, lo9); \
164 }
165
166 /* Macro for fields that gained extra discontiguous MSBs in Gfx12 (specified
167 * by hi12ex-lo12ex).
168 */
169 #define FFDC(name, hi9, lo9, hi12ex, lo12ex, hi12, lo12, assertions) \
170 static inline void \
171 brw_inst_set_##name(const struct intel_device_info *devinfo, \
172 brw_inst *inst, uint64_t value) \
173 { \
174 assert(assertions); \
175 if (devinfo->ver >= 12) { \
176 const unsigned k = hi12 - lo12 + 1; \
177 if (hi12ex != -1 && lo12ex != -1) \
178 brw_inst_set_bits(inst, hi12ex, lo12ex, value >> k); \
179 brw_inst_set_bits(inst, hi12, lo12, value & ((1ull << k) - 1)); \
180 } else { \
181 brw_inst_set_bits(inst, hi9, lo9, value); \
182 } \
183 } \
184 static inline uint64_t \
185 brw_inst_##name(const struct intel_device_info *devinfo, const brw_inst *inst)\
186 { \
187 assert(assertions); \
188 if (devinfo->ver >= 12) { \
189 const unsigned k = hi12 - lo12 + 1; \
190 return (hi12ex == -1 || lo12ex == -1 ? 0 : \
191 brw_inst_bits(inst, hi12ex, lo12ex) << k) | \
192 brw_inst_bits(inst, hi12, lo12); \
193 } else { \
194 return brw_inst_bits(inst, hi9, lo9); \
195 } \
196 }
197
198 #define FD(name, hi9, lo9, hi12ex, lo12ex, hi12, lo12) \
199 FFDC(name, hi9, lo9, hi12ex, lo12ex, hi12, lo12, true)
200
201 /* Macro for fields that didn't move across generations until Gfx12, and then
202 * gained extra discontiguous bits.
203 */
204 #define FDC(name, hi9, lo9, hi12ex, lo12ex, hi12, lo12, assertions) \
205 FFDC(name, hi9, lo9, hi12ex, lo12ex, hi12, lo12, assertions)
206
207 static inline uint64_t
brw_reg_file_to_hw_reg_file(enum brw_reg_file file)208 brw_reg_file_to_hw_reg_file(enum brw_reg_file file)
209 {
210 switch (file) {
211 case ARF: return 0x0;
212 case FIXED_GRF: return 0x1;
213 default: /* Fallthrough. */
214 case IMM: return 0x3;
215 }
216 }
217
218 static inline enum brw_reg_file
hw_reg_file_to_brw_reg_file(uint64_t v)219 hw_reg_file_to_brw_reg_file(uint64_t v)
220 {
221 switch (v) {
222 case 0x0: return ARF;
223 case 0x1: return FIXED_GRF;
224 default: return IMM;
225 }
226 }
227
228 /* Macro for storing register file field. See variant FF below for no
229 * assertions.
230 *
231 * In Gfx12+, either a single bit is available (ARF or GRF) or two bits are
232 * available. In that case the register file is stored as the variable length
233 * combination of an IsImm (hi12) bit and an additional file (lo12) bit.
234 *
235 * For some instructions in Gfx11, the encoding uses 0 for GRF, and 1 for
236 * either ARF (for accumulator) or IMM.
237 */
238 #define FFC(name, hi9, lo9, hi12, lo12, assertions, ...) \
239 static inline void \
240 brw_inst_set_##name(const struct intel_device_info *devinfo, \
241 brw_inst *inst, enum brw_reg_file file) \
242 { \
243 assert(assertions); \
244 const struct { \
245 bool _; /* Exists to avoid empty initializer. */ \
246 bool grf_or_imm; \
247 bool grf_or_acc; \
248 } args = { ._ = false, __VA_ARGS__ }; \
249 uint64_t value = brw_reg_file_to_hw_reg_file(file); \
250 if (devinfo->ver < 12) { \
251 if (devinfo->ver == 11 && args.grf_or_imm) { \
252 assert(file == FIXED_GRF || file == IMM); \
253 value = file == FIXED_GRF ? 0 : 1; \
254 } else if (devinfo->ver == 11 && args.grf_or_acc) { \
255 assert(file == FIXED_GRF || file == ARF); \
256 value = file == FIXED_GRF ? 0 : 1; \
257 } \
258 brw_inst_set_bits(inst, hi9, lo9, value); \
259 } else if (hi12 == lo12) { \
260 brw_inst_set_bits(inst, hi12, lo12, value); \
261 } else { \
262 brw_inst_set_bits(inst, hi12, hi12, value >> 1); \
263 if ((value >> 1) == 0) \
264 brw_inst_set_bits(inst, lo12, lo12, value & 1); \
265 } \
266 } \
267 static inline uint64_t \
268 brw_inst_##name(const struct intel_device_info *devinfo, const brw_inst *inst)\
269 { \
270 assert(assertions); \
271 const struct { \
272 bool _; /* Exists to avoid empty initializer. */ \
273 bool grf_or_imm; \
274 bool grf_or_acc; \
275 } args = { ._ = false, __VA_ARGS__ }; \
276 uint64_t value; \
277 if (devinfo->ver < 12) { \
278 value = brw_inst_bits(inst, hi9, lo9); \
279 if (devinfo->ver == 11 && args.grf_or_imm) \
280 return value ? IMM : FIXED_GRF; \
281 else if (devinfo->ver == 11 && args.grf_or_acc) \
282 return value ? ARF : FIXED_GRF; \
283 } else if (hi12 == lo12) { \
284 value = brw_inst_bits(inst, hi12, lo12); \
285 } else { \
286 value = (brw_inst_bits(inst, hi12, hi12) << 1) | \
287 (brw_inst_bits(inst, hi12, hi12) == 0 ? \
288 brw_inst_bits(inst, lo12, lo12) : 1); \
289 } \
290 return hw_reg_file_to_brw_reg_file(value); \
291 }
292
293 #define FF(name, hi9, lo9, hi12, lo12, ...) FFC(name, hi9, lo9, hi12, lo12, true, __VA_ARGS__)
294
295 /* Macro for fields that become a constant in Gfx12+ not actually represented
296 * in the instruction.
297 */
298 #define FK(name, hi9, lo9, const12) \
299 static inline void \
300 brw_inst_set_##name(const struct intel_device_info *devinfo, \
301 brw_inst *inst, uint64_t v) \
302 { \
303 if (devinfo->ver >= 12) \
304 assert(v == (const12)); \
305 else \
306 brw_inst_set_bits(inst, hi9, lo9, v); \
307 } \
308 static inline uint64_t \
309 brw_inst_##name(const struct intel_device_info *devinfo, \
310 const brw_inst *inst) \
311 { \
312 if (devinfo->ver >= 12) \
313 return (const12); \
314 else \
315 return brw_inst_bits(inst, hi9, lo9); \
316 }
317
318 FV20(src1_vstride, /* 9+ */ 120, 117, /* 12+ */ 119, 116, /* 20+ */ 118, 116)
319 F(src1_width, /* 9+ */ 116, 114, /* 12+ */ 115, 113)
320 F(src1_da16_swiz_w, /* 9+ */ 115, 114, /* 12+ */ -1, -1)
321 F(src1_da16_swiz_z, /* 9+ */ 113, 112, /* 12+ */ -1, -1)
322 F(src1_hstride, /* 9+ */ 113, 112, /* 12+ */ 97, 96)
323 F(src1_address_mode, /* 9+ */ 111, 111, /* 12+ */ 112, 112)
324 /** Src1.SrcMod @{ */
325 F(src1_negate, /* 9+ */ 110, 110, /* 12+ */ 121, 121)
326 F(src1_abs, /* 9+ */ 109, 109, /* 12+ */ 120, 120)
327 /** @} */
328 F(src1_ia_subreg_nr, /* 9+ */ 108, 105, /* 12+ */ 111, 108)
329 F(src1_da_reg_nr, /* 9+ */ 108, 101, /* 12+ */ 111, 104)
330 F(src1_da16_subreg_nr, /* 9+ */ 100, 100, /* 12+ */ -1, -1)
331 FD20(src1_da1_subreg_nr, /* 9+ */ 100, 96, /* 12+ */ 103, 99, /* 20+ */ 103, 99, -1)
332 F(src1_da16_swiz_y, /* 9+ */ 99, 98, /* 12+ */ -1, -1)
333 F(src1_da16_swiz_x, /* 9+ */ 97, 96, /* 12+ */ -1, -1)
334 F(src1_reg_hw_type, /* 9+ */ 94, 91, /* 12+ */ 91, 88)
335 FF(src1_reg_file, /* 9+ */ 90, 89, /* 12+ */ 47, 98)
336 F(src1_is_imm, /* 9+ */ -1, -1, /* 12+ */ 47, 47)
337 FV20(src0_vstride, /* 9+ */ 88, 85, /* 12+ */ 87, 84, /* 20+ */ 86, 84)
338 F(src0_width, /* 9+ */ 84, 82, /* 12+ */ 83, 81)
339 F(src0_da16_swiz_w, /* 9+ */ 83, 82, /* 12+ */ -1, -1)
340 F(src0_da16_swiz_z, /* 9+ */ 81, 80, /* 12+ */ -1, -1)
341 F(src0_hstride, /* 9+ */ 81, 80, /* 12+ */ 65, 64)
342 F(src0_address_mode, /* 9+ */ 79, 79, /* 12+ */ 80, 80)
343 /** Src0.SrcMod @{ */
344 F(src0_negate, /* 9+ */ 78, 78, /* 12+ */ 45, 45)
345 F(src0_abs, /* 9+ */ 77, 77, /* 12+ */ 44, 44)
346 /** @} */
347 F(src0_ia_subreg_nr, /* 9+ */ 76, 73, /* 12+ */ 79, 76)
348 F(src0_da_reg_nr, /* 9+ */ 76, 69, /* 12+ */ 79, 72)
349 F(src0_da16_subreg_nr, /* 9+ */ 68, 68, /* 12+ */ -1, -1)
350 FD20(src0_da1_subreg_nr, /* 9+ */ 68, 64, /* 12+ */ 71, 67, /* 20+ */ 71, 67, 87)
351 F(src0_da16_swiz_y, /* 9+ */ 67, 66, /* 12+ */ -1, -1)
352 F(src0_da16_swiz_x, /* 9+ */ 65, 64, /* 12+ */ -1, -1)
353 F(dst_address_mode, /* 9+ */ 63, 63, /* 12+ */ 35, 35)
354 F(dst_hstride, /* 9+ */ 62, 61, /* 12+ */ 49, 48)
355 F(dst_ia_subreg_nr, /* 9+ */ 60, 57, /* 12+ */ 63, 60)
356 F(dst_da_reg_nr, /* 9+ */ 60, 53, /* 12+ */ 63, 56)
357 F(dst_da16_subreg_nr, /* 9+ */ 52, 52, /* 12+ */ -1, -1)
358 FD20(dst_da1_subreg_nr, /* 9+ */ 52, 48, /* 12+ */ 55, 51, /* 20+ */ 55, 51, 33)
359 F(da16_writemask, /* 9+ */ 51, 48, /* 12+ */ -1, -1) /* Dst.ChanEn */
360 F(src0_reg_hw_type, /* 9+ */ 46, 43, /* 12+ */ 43, 40)
361 FF(src0_reg_file, /* 9+ */ 42, 41, /* 12+ */ 46, 66)
362 F(src0_is_imm, /* 9+ */ -1, -1, /* 12+ */ 46, 46)
363 F(dst_reg_hw_type, /* 9+ */ 40, 37, /* 12+ */ 39, 36)
364 FF(dst_reg_file, /* 9+ */ 36, 35, /* 12+ */ 50, 50)
365 F(mask_control, /* 9+ */ 34, 34, /* 12+ */ 31, 31)
366 F20(flag_reg_nr, /* 9+ */ 33, 33, /* 12+ */ 23, 23, /* 20+ */ 23, 22)
367 F20(flag_subreg_nr, /* 9+ */ 32, 32, /* 12+ */ 22, 22, /* 20+ */ 21, 21)
368 F(saturate, /* 9+ */ 31, 31, /* 12+ */ 34, 34)
369 F(debug_control, /* 9+ */ 30, 30, /* 12+ */ 30, 30)
370 F(cmpt_control, /* 9+ */ 29, 29, /* 12+ */ 29, 29)
371 F(branch_control, /* 9+ */ 28, 28, /* 12+ */ 33, 33)
372 FC(acc_wr_control, /* 9+ */ 28, 28, /* 12+ */ 33, 33, devinfo->ver < 20)
373 F(cond_modifier, /* 9+ */ 27, 24, /* 12+ */ 95, 92)
374 F(math_function, /* 9+ */ 27, 24, /* 12+ */ 95, 92)
375 F20(exec_size, /* 9+ */ 23, 21, /* 12+ */ 18, 16, /* 20+ */ 20, 18)
376 F(pred_inv, /* 9+ */ 20, 20, /* 12+ */ 28, 28)
377 F20(pred_control, /* 9+ */ 19, 16, /* 12+ */ 27, 24, /* 20+ */ 27, 26)
378 F(thread_control, /* 9+ */ 15, 14, /* 12+ */ -1, -1)
379 F(atomic_control, /* 9+ */ -1, -1, /* 12+ */ 32, 32)
380 F20(qtr_control, /* 9+ */ 13, 12, /* 12+ */ 21, 20, /* 20+ */ 25, 24)
381 F20(nib_control, /* 9+ */ 11, 11, /* 12+ */ 19, 19, /* 20+ */ -1, -1)
382 F(no_dd_check, /* 9+ */ 10, 10, /* 12+ */ -1, -1)
383 F(no_dd_clear, /* 9+ */ 9, 9, /* 12+ */ -1, -1)
384 F20(swsb, /* 9+ */ -1, -1, /* 12+ */ 15, 8, /* 20+ */ 17, 8)
385 FK(access_mode, /* 9+ */ 8, 8, /* 12+ */ BRW_ALIGN_1)
386 /* Bit 7 is Reserved (for future Opcode expansion) */
387 F(hw_opcode, /* 9+ */ 6, 0, /* 12+ */ 6, 0)
388
389 /**
390 * Three-source instructions:
391 * @{
392 */
393 F(3src_src2_reg_nr, /* 9+ */ 125, 118, /* 12+ */ 127, 120) /* same in align1 */
394 F(3src_a16_src2_subreg_nr, /* 9+ */ 117, 115, /* 12+ */ -1, -1) /* Extra discontiguous bit on CHV? */
395 F(3src_a16_src2_swizzle, /* 9+ */ 114, 107, /* 12+ */ -1, -1)
396 F(3src_a16_src2_rep_ctrl, /* 9+ */ 106, 106, /* 12+ */ -1, -1)
397 F(3src_src1_reg_nr, /* 9+ */ 104, 97, /* 12+ */ 111, 104) /* same in align1 */
398 F(3src_a16_src1_subreg_nr, /* 9+ */ 96, 94, /* 12+ */ -1, -1) /* Extra discontiguous bit on CHV? */
399 F(3src_a16_src1_swizzle, /* 9+ */ 93, 86, /* 12+ */ -1, -1)
400 F(3src_a16_src1_rep_ctrl, /* 9+ */ 85, 85, /* 12+ */ -1, -1)
401 F(3src_src0_reg_nr, /* 9+ */ 83, 76, /* 12+ */ 79, 72) /* same in align1 */
402 F(3src_a16_src0_subreg_nr, /* 9+ */ 75, 73, /* 12+ */ -1, -1) /* Extra discontiguous bit on CHV? */
403 F(3src_a16_src0_swizzle, /* 9+ */ 72, 65, /* 12+ */ -1, -1)
404 F(3src_a16_src0_rep_ctrl, /* 9+ */ 64, 64, /* 12+ */ -1, -1)
405 F(3src_dst_reg_nr, /* 9+ */ 63, 56, /* 12+ */ 63, 56) /* same in align1 */
406 F(3src_a16_dst_subreg_nr, /* 9+ */ 55, 53, /* 12+ */ -1, -1)
407 F(3src_a16_dst_writemask, /* 9+ */ 52, 49, /* 12+ */ -1, -1)
408 F(3src_a16_nib_ctrl, /* 9+ */ 11, 11, /* 12+ */ -1, -1) /* only exists on IVB+ */
409 F(3src_a16_dst_hw_type, /* 9+ */ 48, 46, /* 12+ */ -1, -1) /* only exists on IVB+ */
410 F(3src_a16_src_hw_type, /* 9+ */ 45, 43, /* 12+ */ -1, -1)
411 F(3src_src2_negate, /* 9+ */ 42, 42, /* 12+ */ 85, 85)
412 F(3src_src2_abs, /* 9+ */ 41, 41, /* 12+ */ 84, 84)
413 F(3src_src1_negate, /* 9+ */ 40, 40, /* 12+ */ 87, 87)
414 F(3src_src1_abs, /* 9+ */ 39, 39, /* 12+ */ 86, 86)
415 F(3src_src0_negate, /* 9+ */ 38, 38, /* 12+ */ 45, 45)
416 F(3src_src0_abs, /* 9+ */ 37, 37, /* 12+ */ 44, 44)
417 F(3src_a16_src1_type, /* 9+ */ 36, 36, /* 12+ */ -1, -1)
418 F(3src_a16_src2_type, /* 9+ */ 35, 35, /* 12+ */ -1, -1)
419 F(3src_a16_flag_reg_nr, /* 9+ */ 33, 33, /* 12+ */ -1, -1)
420 F(3src_a16_flag_subreg_nr, /* 9+ */ 32, 32, /* 12+ */ -1, -1)
421 F(3src_saturate, /* 9+ */ 31, 31, /* 12+ */ 34, 34)
422 F(3src_debug_control, /* 9+ */ 30, 30, /* 12+ */ 30, 30)
423 F(3src_cmpt_control, /* 9+ */ 29, 29, /* 12+ */ 29, 29)
424 FC(3src_acc_wr_control, /* 9+ */ 28, 28, /* 12+ */ 33, 33, devinfo->ver < 20)
425 F(3src_cond_modifier, /* 9+ */ 27, 24, /* 12+ */ 95, 92)
426 F(3src_exec_size, /* 9+ */ 23, 21, /* 12+ */ 18, 16)
427 F(3src_pred_inv, /* 9+ */ 20, 20, /* 12+ */ 28, 28)
428 F20(3src_pred_control, /* 9+ */ 19, 16, /* 12+ */ 27, 24, /* 20+ */ 27, 26)
429 F(3src_thread_control, /* 9+ */ 15, 14, /* 12+ */ -1, -1)
430 F(3src_atomic_control, /* 9+ */ -1, -1, /* 12+ */ 32, 32)
431 F20(3src_qtr_control, /* 9+ */ 13, 12, /* 12+ */ 21, 20, /* 20+ */ 25, 24)
432 F(3src_no_dd_check, /* 9+ */ 10, 10, /* 12+ */ -1, -1)
433 F(3src_no_dd_clear, /* 9+ */ 9, 9, /* 12+ */ -1, -1)
434 F(3src_mask_control, /* 9+ */ 34, 34, /* 12+ */ 31, 31)
435 FK(3src_access_mode, /* 9+ */ 8, 8, /* 12+ */ BRW_ALIGN_1)
436 F(3src_swsb, /* 9+ */ -1, -1, /* 12+ */ 15, 8)
437 /* Bit 7 is Reserved (for future Opcode expansion) */
438 F(3src_hw_opcode, /* 9+ */ 6, 0, /* 12+ */ 6, 0)
439 /** @} */
440
441 #define REG_TYPE(reg) \
442 static inline void \
443 brw_inst_set_3src_a16_##reg##_type(const struct intel_device_info *devinfo, \
444 brw_inst *inst, enum brw_reg_type type) \
445 { \
446 unsigned hw_type = brw_type_encode_for_3src(devinfo, type); \
447 brw_inst_set_3src_a16_##reg##_hw_type(devinfo, inst, hw_type); \
448 } \
449 \
450 static inline enum brw_reg_type \
451 brw_inst_3src_a16_##reg##_type(const struct intel_device_info *devinfo, \
452 const brw_inst *inst) \
453 { \
454 unsigned hw_type = brw_inst_3src_a16_##reg##_hw_type(devinfo, inst); \
455 return brw_type_decode_for_3src(devinfo, hw_type, 0); \
456 }
457
REG_TYPE(dst)458 REG_TYPE(dst)
459 REG_TYPE(src)
460 #undef REG_TYPE
461
462 /**
463 * Three-source align1 instructions:
464 * @{
465 */
466 /* Reserved 127:126 */
467 /* src2_reg_nr same in align16 */
468 FD20(3src_a1_src2_subreg_nr,/* 9+ */ 117, 113, /* 12+ */ 119, 115, /* 20+ */ 119, 115, -1)
469 FC(3src_a1_src2_hstride, /* 9+ */ 112, 111, /* 12+ */ 113, 112, devinfo->ver >= 10)
470 /* Reserved 110:109. src2 vstride is an implied parameter */
471 FC(3src_a1_src2_hw_type, /* 9+ */ 108, 106, /* 12+ */ 82, 80, devinfo->ver >= 10)
472 /* Reserved 105 */
473 /* src1_reg_nr same in align16 */
474 FD20(3src_a1_src1_subreg_nr, /* 9+ */ 96, 92, /* 12+ */ 103, 99, /* 20+ */ 103, 99, -1)
475 FC(3src_a1_src1_hstride, /* 9+ */ 91, 90, /* 12+ */ 97, 96, devinfo->ver >= 10)
476 FDC(3src_a1_src1_vstride, /* 9+ */ 89, 88, /* 12+ */ 91, 91, 83, 83, devinfo->ver >= 10)
477 FC(3src_a1_src1_hw_type, /* 9+ */ 87, 85, /* 12+ */ 90, 88, devinfo->ver >= 10)
478 /* Reserved 84 */
479 /* src0_reg_nr same in align16 */
480 FD20(3src_a1_src0_subreg_nr, /* 9+ */ 75, 71, /* 12+ */ 71, 67, /* 20+ */ 71, 67, -1)
481 FC(3src_a1_src0_hstride, /* 9+ */ 70, 69, /* 12+ */ 65, 64, devinfo->ver >= 10)
482 FDC(3src_a1_src0_vstride, /* 9+ */ 68, 67, /* 12+ */ 43, 43, 35, 35, devinfo->ver >= 10)
483 FC(3src_a1_src0_hw_type, /* 9+ */ 66, 64, /* 12+ */ 42, 40, devinfo->ver >= 10)
484 /* dst_reg_nr same in align16 */
485 FC(3src_a1_dst_subreg_nr, /* 9+ */ 55, 54, /* 12+ */ 55, 54, devinfo->ver >= 10)
486 FC(3src_a1_special_acc, /* 9+ */ 55, 52, /* 12+ */ 54, 51, devinfo->ver >= 10) /* aliases dst_subreg_nr */
487 /* Reserved 51:50 */
488 FC(3src_a1_dst_hstride, /* 9+ */ 49, 49, /* 12+ */ 48, 48, devinfo->ver >= 10)
489 FC(3src_a1_dst_hw_type, /* 9+ */ 48, 46, /* 12+ */ 38, 36, devinfo->ver >= 10)
490 FF(3src_a1_src2_reg_file, /* 9+ */ 45, 45, /* 12+ */ 47, 114, .grf_or_imm = true)
491 FFC(3src_a1_src1_reg_file, /* 9+ */ 44, 44, /* 12+ */ 98, 98, devinfo->ver >= 10, .grf_or_acc = true)
492 FF(3src_a1_src0_reg_file, /* 9+ */ 43, 43, /* 12+ */ 46, 66, .grf_or_imm = true)
493
494 F(3src_a1_src2_is_imm, /* 9+ */ -1, -1, /* 12+ */ 47, 47)
495 F(3src_a1_src0_is_imm, /* 9+ */ -1, -1, /* 12+ */ 46, 46)
496
497 /* Source Modifier fields same in align16 */
498 FFC(3src_a1_dst_reg_file, /* 9+ */ 36, 36, /* 12+ */ 50, 50, devinfo->ver >= 10, .grf_or_acc = true)
499 FC(3src_a1_exec_type, /* 9+ */ 35, 35, /* 12+ */ 39, 39, devinfo->ver >= 10)
500 /* Fields below this same in align16 */
501 /** @} */
502
503 #define REG_TYPE(reg) \
504 static inline void \
505 brw_inst_set_3src_a1_##reg##_type(const struct intel_device_info *devinfo, \
506 brw_inst *inst, enum brw_reg_type type) \
507 { \
508 UNUSED enum gfx10_align1_3src_exec_type exec_type = \
509 (enum gfx10_align1_3src_exec_type) brw_inst_3src_a1_exec_type(devinfo, \
510 inst); \
511 if (brw_type_is_float(type)) { \
512 assert(exec_type == BRW_ALIGN1_3SRC_EXEC_TYPE_FLOAT); \
513 } else { \
514 assert(exec_type == BRW_ALIGN1_3SRC_EXEC_TYPE_INT); \
515 } \
516 unsigned hw_type = brw_type_encode_for_3src(devinfo, type); \
517 brw_inst_set_3src_a1_##reg##_hw_type(devinfo, inst, hw_type); \
518 } \
519 \
520 static inline enum brw_reg_type \
521 brw_inst_3src_a1_##reg##_type(const struct intel_device_info *devinfo, \
522 const brw_inst *inst) \
523 { \
524 enum gfx10_align1_3src_exec_type exec_type = \
525 (enum gfx10_align1_3src_exec_type) brw_inst_3src_a1_exec_type(devinfo, \
526 inst); \
527 unsigned hw_type = brw_inst_3src_a1_##reg##_hw_type(devinfo, inst); \
528 return brw_type_decode_for_3src(devinfo, hw_type, exec_type); \
529 }
530
531 REG_TYPE(dst)
532 REG_TYPE(src0)
533 REG_TYPE(src1)
534 REG_TYPE(src2)
535 #undef REG_TYPE
536
537 /**
538 * Three-source align1 instruction immediates:
539 * @{
540 */
541 static inline uint16_t
542 brw_inst_3src_a1_src0_imm(ASSERTED const struct intel_device_info *devinfo,
543 const brw_inst *insn)
544 {
545 assert(devinfo->ver >= 10);
546 if (devinfo->ver >= 12)
547 return brw_inst_bits(insn, 79, 64);
548 else
549 return brw_inst_bits(insn, 82, 67);
550 }
551
552 static inline uint16_t
brw_inst_3src_a1_src2_imm(ASSERTED const struct intel_device_info * devinfo,const brw_inst * insn)553 brw_inst_3src_a1_src2_imm(ASSERTED const struct intel_device_info *devinfo,
554 const brw_inst *insn)
555 {
556 assert(devinfo->ver >= 10);
557 if (devinfo->ver >= 12)
558 return brw_inst_bits(insn, 127, 112);
559 else
560 return brw_inst_bits(insn, 124, 109);
561 }
562
563 static inline void
brw_inst_set_3src_a1_src0_imm(ASSERTED const struct intel_device_info * devinfo,brw_inst * insn,uint16_t value)564 brw_inst_set_3src_a1_src0_imm(ASSERTED const struct intel_device_info *devinfo,
565 brw_inst *insn, uint16_t value)
566 {
567 assert(devinfo->ver >= 10);
568 if (devinfo->ver >= 12)
569 brw_inst_set_bits(insn, 79, 64, value);
570 else
571 brw_inst_set_bits(insn, 82, 67, value);
572 }
573
574 static inline void
brw_inst_set_3src_a1_src2_imm(ASSERTED const struct intel_device_info * devinfo,brw_inst * insn,uint16_t value)575 brw_inst_set_3src_a1_src2_imm(ASSERTED const struct intel_device_info *devinfo,
576 brw_inst *insn, uint16_t value)
577 {
578 assert(devinfo->ver >= 10);
579 if (devinfo->ver >= 12)
580 brw_inst_set_bits(insn, 127, 112, value);
581 else
582 brw_inst_set_bits(insn, 124, 109, value);
583 }
584 /** @} */
585
586 /**
587 * Three-source systolic instructions:
588 * @{
589 */
590 F(dpas_3src_src2_reg_nr, /* 9+ */ -1, -1, /* 12+ */ 127, 120)
591 F(dpas_3src_src2_subreg_nr, /* 9+ */ -1, -1, /* 12+ */ 119, 115)
592 FF(dpas_3src_src2_reg_file, /* 9+ */ -1, -1, /* 12+ */ 114, 114)
593 F(dpas_3src_src1_reg_nr, /* 9+ */ -1, -1, /* 12+ */ 111, 104)
594 F(dpas_3src_src1_subreg_nr, /* 9+ */ -1, -1, /* 12+ */ 103, 99)
595 FF(dpas_3src_src1_reg_file, /* 9+ */ -1, -1, /* 12+ */ 98, 98)
596 F(dpas_3src_src1_hw_type, /* 9+ */ -1, -1, /* 12+ */ 90, 88)
597 F(dpas_3src_src1_subbyte, /* 9+ */ -1, -1, /* 12+ */ 87, 86)
598 F(dpas_3src_src2_subbyte, /* 9+ */ -1, -1, /* 12+ */ 85, 84)
599 F(dpas_3src_src2_hw_type, /* 9+ */ -1, -1, /* 12+ */ 82, 80)
600 F(dpas_3src_src0_reg_nr, /* 9+ */ -1, -1, /* 12+ */ 79, 72)
601 F(dpas_3src_src0_subreg_nr, /* 9+ */ -1, -1, /* 12+ */ 71, 67)
602 FF(dpas_3src_src0_reg_file, /* 9+ */ -1, -1, /* 12+ */ 66, 66)
603 F(dpas_3src_dst_reg_nr, /* 9+ */ -1, -1, /* 12+ */ 63, 56)
604 F(dpas_3src_dst_subreg_nr, /* 9+ */ -1, -1, /* 12+ */ 55, 51)
605 FF(dpas_3src_dst_reg_file, /* 9+ */ -1, -1, /* 12+ */ 50, 50)
606 F(dpas_3src_sdepth, /* 9+ */ -1, -1, /* 12+ */ 49, 48)
607 F(dpas_3src_rcount, /* 9+ */ -1, -1, /* 12+ */ 45, 43)
608 F(dpas_3src_src0_hw_type, /* 9+ */ -1, -1, /* 12+ */ 42, 40)
609 F(dpas_3src_exec_type, /* 9+ */ -1, -1, /* 12+ */ 39, 39)
610 F(dpas_3src_dst_hw_type, /* 9+ */ -1, -1, /* 12+ */ 38, 36)
611 /** @} */
612
613 #define REG_TYPE(reg) \
614 static inline void \
615 brw_inst_set_dpas_3src_##reg##_type(const struct intel_device_info *devinfo, \
616 brw_inst *inst, enum brw_reg_type type) \
617 { \
618 UNUSED enum gfx10_align1_3src_exec_type exec_type = \
619 (enum gfx10_align1_3src_exec_type) brw_inst_dpas_3src_exec_type(devinfo,\
620 inst); \
621 if (brw_type_is_float(type)) { \
622 assert(exec_type == BRW_ALIGN1_3SRC_EXEC_TYPE_FLOAT); \
623 } else { \
624 assert(exec_type == BRW_ALIGN1_3SRC_EXEC_TYPE_INT); \
625 } \
626 unsigned hw_type = brw_type_encode_for_3src(devinfo, type); \
627 brw_inst_set_dpas_3src_##reg##_hw_type(devinfo, inst, hw_type); \
628 } \
629 \
630 static inline enum brw_reg_type \
631 brw_inst_dpas_3src_##reg##_type(const struct intel_device_info *devinfo, \
632 const brw_inst *inst) \
633 { \
634 enum gfx10_align1_3src_exec_type exec_type = \
635 (enum gfx10_align1_3src_exec_type) brw_inst_dpas_3src_exec_type(devinfo,\
636 inst); \
637 unsigned hw_type = brw_inst_dpas_3src_##reg##_hw_type(devinfo, inst); \
638 return brw_type_decode_for_3src(devinfo, hw_type, exec_type); \
639 }
640
REG_TYPE(dst)641 REG_TYPE(dst)
642 REG_TYPE(src0)
643 REG_TYPE(src1)
644 REG_TYPE(src2)
645 #undef REG_TYPE
646
647 /**
648 * Flow control instruction bits:
649 * @{
650 */
651 static inline void
652 brw_inst_set_uip(const struct intel_device_info *devinfo,
653 brw_inst *inst, int32_t value)
654 {
655 if (devinfo->ver >= 12)
656 brw_inst_set_src1_is_imm(devinfo, inst, 1);
657
658 brw_inst_set_bits(inst, 95, 64, (uint32_t)value);
659 }
660
661 static inline int32_t
brw_inst_uip(const struct intel_device_info * devinfo,const brw_inst * inst)662 brw_inst_uip(const struct intel_device_info *devinfo, const brw_inst *inst)
663 {
664 return brw_inst_bits(inst, 95, 64);
665 }
666
667 static inline void
brw_inst_set_jip(const struct intel_device_info * devinfo,brw_inst * inst,int32_t value)668 brw_inst_set_jip(const struct intel_device_info *devinfo,
669 brw_inst *inst, int32_t value)
670 {
671 if (devinfo->ver >= 12)
672 brw_inst_set_src0_is_imm(devinfo, inst, 1);
673
674 brw_inst_set_bits(inst, 127, 96, (uint32_t)value);
675 }
676
677 static inline int32_t
brw_inst_jip(const struct intel_device_info * devinfo,const brw_inst * inst)678 brw_inst_jip(const struct intel_device_info *devinfo, const brw_inst *inst)
679 {
680 return brw_inst_bits(inst, 127, 96);
681 }
682 /** @} */
683
684 /**
685 * SEND instructions:
686 * @{
687 */
688 F(send_ex_desc_ia_subreg_nr, /* 9+ */ 82, 80, /* 12+ */ 42, 40)
689 F(send_src0_address_mode, /* 9+ */ 79, 79, /* 12+ */ -1, -1)
690 F(send_sel_reg32_desc, /* 9+ */ 77, 77, /* 12+ */ 48, 48)
691 F(send_sel_reg32_ex_desc, /* 9+ */ 61, 61, /* 12+ */ 49, 49)
692 FF(send_src0_reg_file, /* 9+ */ 42, 41, /* 12+ */ 66, 66)
693 F(send_src1_reg_nr, /* 9+ */ 51, 44, /* 12+ */ 111, 104)
694 FC(send_src1_len, /* 9+ */ -1, -1, /* 12+ */ 103, 99, devinfo->verx10 >= 125)
695 FF(send_src1_reg_file, /* 9+ */ 36, 36, /* 12+ */ 98, 98)
696 FF(send_dst_reg_file, /* 9+ */ 35, 35, /* 12+ */ 50, 50)
697 FC(send_ex_bso, /* 9+ */ -1, -1, /* 12+ */ 39, 39, devinfo->verx10 >= 125)
698 /** @} */
699
700 /* Message descriptor bits */
701 #define MD(x) ((x) + 96)
702 #define MD12(x) ((x) >= 30 ? (x) - 30 + 122 : \
703 (x) >= 25 ? (x) - 25 + 67 : \
704 (x) >= 20 ? (x) - 20 + 51 : \
705 (x) >= 11 ? (x) - 11 + 113 : \
706 (x) - 0 + 81)
707
708 /**
709 * Set the SEND(C) message descriptor immediate.
710 *
711 * This doesn't include the SFID nor the EOT field that were considered to be
712 * part of the message descriptor by ancient versions of the BSpec, because
713 * they are present in the instruction even if the message descriptor is
714 * provided indirectly in the address register, so we want to specify them
715 * separately.
716 */
717 static inline void
brw_inst_set_send_desc(const struct intel_device_info * devinfo,brw_inst * inst,uint32_t value)718 brw_inst_set_send_desc(const struct intel_device_info *devinfo,
719 brw_inst *inst, uint32_t value)
720 {
721 if (devinfo->ver >= 12) {
722 brw_inst_set_bits(inst, 123, 122, GET_BITS(value, 31, 30));
723 brw_inst_set_bits(inst, 71, 67, GET_BITS(value, 29, 25));
724 brw_inst_set_bits(inst, 55, 51, GET_BITS(value, 24, 20));
725 brw_inst_set_bits(inst, 121, 113, GET_BITS(value, 19, 11));
726 brw_inst_set_bits(inst, 91, 81, GET_BITS(value, 10, 0));
727 } else {
728 brw_inst_set_bits(inst, 126, 96, value);
729 assert(value >> 31 == 0);
730 }
731 }
732
733 /**
734 * Get the SEND(C) message descriptor immediate.
735 *
736 * \sa brw_inst_set_send_desc().
737 */
738 static inline uint32_t
brw_inst_send_desc(const struct intel_device_info * devinfo,const brw_inst * inst)739 brw_inst_send_desc(const struct intel_device_info *devinfo,
740 const brw_inst *inst)
741 {
742 if (devinfo->ver >= 12) {
743 return (brw_inst_bits(inst, 123, 122) << 30 |
744 brw_inst_bits(inst, 71, 67) << 25 |
745 brw_inst_bits(inst, 55, 51) << 20 |
746 brw_inst_bits(inst, 121, 113) << 11 |
747 brw_inst_bits(inst, 91, 81));
748 } else {
749 return brw_inst_bits(inst, 126, 96);
750 }
751 }
752
753 /**
754 * Set the SEND(C) message extended descriptor immediate.
755 *
756 * This doesn't include the SFID nor the EOT field that were considered to be
757 * part of the extended message descriptor by some versions of the BSpec,
758 * because they are present in the instruction even if the extended message
759 * descriptor is provided indirectly in a register, so we want to specify them
760 * separately.
761 */
762 static inline void
brw_inst_set_send_ex_desc(const struct intel_device_info * devinfo,brw_inst * inst,uint32_t value)763 brw_inst_set_send_ex_desc(const struct intel_device_info *devinfo,
764 brw_inst *inst, uint32_t value)
765 {
766 if (devinfo->ver >= 12) {
767 brw_inst_set_bits(inst, 127, 124, GET_BITS(value, 31, 28));
768 brw_inst_set_bits(inst, 97, 96, GET_BITS(value, 27, 26));
769 brw_inst_set_bits(inst, 65, 64, GET_BITS(value, 25, 24));
770 brw_inst_set_bits(inst, 47, 35, GET_BITS(value, 23, 11));
771 brw_inst_set_bits(inst, 103, 99, GET_BITS(value, 10, 6));
772 assert(GET_BITS(value, 5, 0) == 0);
773 } else {
774 assert(devinfo->ver >= 9);
775 brw_inst_set_bits(inst, 94, 91, GET_BITS(value, 31, 28));
776 brw_inst_set_bits(inst, 88, 85, GET_BITS(value, 27, 24));
777 brw_inst_set_bits(inst, 83, 80, GET_BITS(value, 23, 20));
778 brw_inst_set_bits(inst, 67, 64, GET_BITS(value, 19, 16));
779 assert(GET_BITS(value, 15, 0) == 0);
780 }
781 }
782
783 /**
784 * Set the SENDS(C) message extended descriptor immediate.
785 *
786 * This doesn't include the SFID nor the EOT field that were considered to be
787 * part of the extended message descriptor by some versions of the BSpec,
788 * because they are present in the instruction even if the extended message
789 * descriptor is provided indirectly in a register, so we want to specify them
790 * separately.
791 */
792 static inline void
brw_inst_set_sends_ex_desc(const struct intel_device_info * devinfo,brw_inst * inst,uint32_t value)793 brw_inst_set_sends_ex_desc(const struct intel_device_info *devinfo,
794 brw_inst *inst, uint32_t value)
795 {
796 if (devinfo->ver >= 12) {
797 brw_inst_set_send_ex_desc(devinfo, inst, value);
798 } else {
799 brw_inst_set_bits(inst, 95, 80, GET_BITS(value, 31, 16));
800 assert(GET_BITS(value, 15, 10) == 0);
801 brw_inst_set_bits(inst, 67, 64, GET_BITS(value, 9, 6));
802 assert(GET_BITS(value, 5, 0) == 0);
803 }
804 }
805
806 /**
807 * Get the SEND(C) message extended descriptor immediate.
808 *
809 * \sa brw_inst_set_send_ex_desc().
810 */
811 static inline uint32_t
brw_inst_send_ex_desc(const struct intel_device_info * devinfo,const brw_inst * inst)812 brw_inst_send_ex_desc(const struct intel_device_info *devinfo,
813 const brw_inst *inst)
814 {
815 if (devinfo->ver >= 12) {
816 return (brw_inst_bits(inst, 127, 124) << 28 |
817 brw_inst_bits(inst, 97, 96) << 26 |
818 brw_inst_bits(inst, 65, 64) << 24 |
819 brw_inst_bits(inst, 47, 35) << 11 |
820 brw_inst_bits(inst, 103, 99) << 6);
821 } else {
822 assert(devinfo->ver >= 9);
823 return (brw_inst_bits(inst, 94, 91) << 28 |
824 brw_inst_bits(inst, 88, 85) << 24 |
825 brw_inst_bits(inst, 83, 80) << 20 |
826 brw_inst_bits(inst, 67, 64) << 16);
827 }
828 }
829
830 /**
831 * Get the SENDS(C) message extended descriptor immediate.
832 *
833 * \sa brw_inst_set_send_ex_desc().
834 */
835 static inline uint32_t
brw_inst_sends_ex_desc(const struct intel_device_info * devinfo,const brw_inst * inst)836 brw_inst_sends_ex_desc(const struct intel_device_info *devinfo,
837 const brw_inst *inst)
838 {
839 if (devinfo->ver >= 12) {
840 return brw_inst_send_ex_desc(devinfo, inst);
841 } else {
842 return (brw_inst_bits(inst, 95, 80) << 16 |
843 brw_inst_bits(inst, 67, 64) << 6);
844 }
845 }
846
847 /**
848 * Fields for SEND messages:
849 * @{
850 */
851 F(eot, /* 9+ */ 127, 127, /* 12+ */ 34, 34)
852 F(mlen, /* 9+ */ 124, 121, /* 12+ */ MD12(28), MD12(25))
853 F(rlen, /* 9+ */ 120, 116, /* 12+ */ MD12(24), MD12(20))
854 F(header_present, /* 9+ */ 115, 115, /* 12+ */ MD12(19), MD12(19))
855 F(gateway_notify, /* 9+ */ MD(16), MD(15), /* 12+ */ -1, -1)
856 FD(function_control, /* 9+ */ 114, 96, /* 12+ */ MD12(18), MD12(11), MD12(10), MD12(0))
857 F(gateway_subfuncid, /* 9+ */ MD(2), MD(0), /* 12+ */ MD12(2), MD12(0))
858 F(sfid, /* 9+ */ 27, 24, /* 12+ */ 95, 92)
859 F(null_rt, /* 9+ */ 80, 80, /* 12+ */ 44, 44) /* actually only Gfx11+ */
860 F(send_rta_index, /* 9+ */ -1, -1, /* 12+ */ 38, 36)
861 /** @} */
862
863 /**
864 * URB message function control bits:
865 * @{
866 */
867 F(urb_per_slot_offset, /* 9+ */ MD(17), MD(17), /* 12+ */ MD12(17), MD12(17))
868 F(urb_channel_mask_present, /* 9+ */ MD(15), MD(15), /* 12+ */ MD12(15), MD12(15))
869 F(urb_swizzle_control, /* 9+ */ MD(15), MD(15), /* 12+ */ -1, -1)
870 FD(urb_global_offset, /* 9+ */ MD(14), MD(4), /* 12+ */ MD12(14), MD12(11), MD12(10), MD12(4))
871 F(urb_opcode, /* 9+ */ MD( 3), MD(0), /* 12+ */ MD12(3), MD12(0))
872 /** @} */
873
874 /**
875 * Sampler message function control bits:
876 * @{
877 */
878 F(sampler_simd_mode, /* 9+ */ MD(18), MD(17), /* 12+ */ MD12(18), MD12(17))
879 F(sampler_msg_type, /* 9+ */ MD(16), MD(12), /* 12+ */ MD12(16), MD12(12))
880 FD(sampler, /* 9+ */ MD(11), MD(8), /* 12+ */ MD12(11), MD12(11), MD12(10), MD12(8))
881 F(binding_table_index, /* 9+ */ MD(7), MD(0), /* 12+ */ MD12(7), MD12(0)) /* also used by other messages */
882 /** @} */
883
884 /**
885 * Data port message function control bits:
886 * @{
887 */
888 F(dp_category, /* 9+ */ MD(18), MD(18), /* 12+ */ MD12(18), MD12(18))
889
890 F(dp_read_msg_type, /* 9+ */ MD(17), MD(14), /* 12+ */ MD12(17), MD12(14))
891 F(dp_write_msg_type, /* 9+ */ MD(17), MD(14), /* 12+ */ MD12(17), MD12(14))
892 FD(dp_read_msg_control, /* 9+ */ MD(13), MD( 8), /* 12+ */ MD12(13), MD12(11), MD12(10), MD12(8))
893 FD(dp_write_msg_control, /* 9+ */ MD(13), MD( 8), /* 12+ */ MD12(13), MD12(11), MD12(10), MD12(8))
894
895 F(dp_msg_type, /* 9+ */ MD(18), MD(14), /* 12+ */ MD12(18), MD12(14))
896 FD(dp_msg_control, /* 9+ */ MD(13), MD( 8), /* 12+ */ MD12(13), MD12(11), MD12(10), MD12(8))
897 /** @} */
898
899 /**
900 * Scratch message bits:
901 * @{
902 */
903 F(scratch_read_write, /* 9+ */ MD(17), MD(17), /* 12+ */ MD12(17), MD12(17)) /* 0 = read, 1 = write */
904 F(scratch_type, /* 9+ */ MD(16), MD(16), /* 12+ */ -1, -1) /* 0 = OWord, 1 = DWord */
905 F(scratch_invalidate_after_read, /* 9+ */ MD(15), MD(15), /* 12+ */ MD12(15), MD12(15))
906 F(scratch_block_size, /* 9+ */ MD(13), MD(12), /* 12+ */ MD12(13), MD12(12))
907 FD(scratch_addr_offset,
908 /* 9: */ MD(11), MD(0),
909 /* 12: */ MD12(11), MD12(11), MD12(10), MD12(0))
910 /** @} */
911
912 /**
913 * Render Target message function control bits:
914 * @{
915 */
916 F(rt_last, /* 9+ */ MD(12), MD(12), /* 12+ */ MD12(12), MD12(12))
917 F(rt_slot_group, /* 9+ */ MD(11), MD(11), /* 12+ */ MD12(11), MD12(11))
918 F(rt_message_type, /* 9+ */ MD(10), MD( 8), /* 12+ */ MD12(10), MD12(8))
919 /** @} */
920
921 /**
922 * Pixel Interpolator message function control bits:
923 * @{
924 */
925 F(pi_simd_mode, /* 9+ */ MD(16), MD(16), /* 12+ */ MD12(16), MD12(16))
926 F(pi_nopersp, /* 9+ */ MD(14), MD(14), /* 12+ */ MD12(14), MD12(14))
927 F(pi_message_type, /* 9+ */ MD(13), MD(12), /* 12+ */ MD12(13), MD12(12))
928 F(pi_slot_group, /* 9+ */ MD(11), MD(11), /* 12+ */ MD12(11), MD12(11))
929 F(pi_message_data, /* 9+ */ MD(7), MD(0), /* 12+ */ MD12(7), MD12(0))
930 /** @} */
931
932 /**
933 * Immediates:
934 * @{
935 */
936 static inline int
brw_inst_imm_d(const struct intel_device_info * devinfo,const brw_inst * insn)937 brw_inst_imm_d(const struct intel_device_info *devinfo, const brw_inst *insn)
938 {
939 (void) devinfo;
940 return brw_inst_bits(insn, 127, 96);
941 }
942
943 static inline unsigned
brw_inst_imm_ud(const struct intel_device_info * devinfo,const brw_inst * insn)944 brw_inst_imm_ud(const struct intel_device_info *devinfo, const brw_inst *insn)
945 {
946 (void) devinfo;
947 return brw_inst_bits(insn, 127, 96);
948 }
949
950 static inline uint64_t
brw_inst_imm_uq(const struct intel_device_info * devinfo,const brw_inst * insn)951 brw_inst_imm_uq(const struct intel_device_info *devinfo,
952 const brw_inst *insn)
953 {
954 if (devinfo->ver >= 12) {
955 return brw_inst_bits(insn, 95, 64) << 32 |
956 brw_inst_bits(insn, 127, 96);
957 } else {
958 return brw_inst_bits(insn, 127, 64);
959 }
960 }
961
962 static inline float
brw_inst_imm_f(const struct intel_device_info * devinfo,const brw_inst * insn)963 brw_inst_imm_f(const struct intel_device_info *devinfo, const brw_inst *insn)
964 {
965 union {
966 float f;
967 uint32_t u;
968 } ft;
969 (void) devinfo;
970 ft.u = brw_inst_bits(insn, 127, 96);
971 return ft.f;
972 }
973
974 static inline double
brw_inst_imm_df(const struct intel_device_info * devinfo,const brw_inst * insn)975 brw_inst_imm_df(const struct intel_device_info *devinfo, const brw_inst *insn)
976 {
977 union {
978 double d;
979 uint64_t u;
980 } dt;
981 dt.u = brw_inst_imm_uq(devinfo, insn);
982 return dt.d;
983 }
984
985 static inline void
brw_inst_set_imm_d(const struct intel_device_info * devinfo,brw_inst * insn,int value)986 brw_inst_set_imm_d(const struct intel_device_info *devinfo,
987 brw_inst *insn, int value)
988 {
989 (void) devinfo;
990 return brw_inst_set_bits(insn, 127, 96, value);
991 }
992
993 static inline void
brw_inst_set_imm_ud(const struct intel_device_info * devinfo,brw_inst * insn,unsigned value)994 brw_inst_set_imm_ud(const struct intel_device_info *devinfo,
995 brw_inst *insn, unsigned value)
996 {
997 (void) devinfo;
998 return brw_inst_set_bits(insn, 127, 96, value);
999 }
1000
1001 static inline void
brw_inst_set_imm_f(const struct intel_device_info * devinfo,brw_inst * insn,float value)1002 brw_inst_set_imm_f(const struct intel_device_info *devinfo,
1003 brw_inst *insn, float value)
1004 {
1005 union {
1006 float f;
1007 uint32_t u;
1008 } ft;
1009 (void) devinfo;
1010 ft.f = value;
1011 brw_inst_set_bits(insn, 127, 96, ft.u);
1012 }
1013
1014 static inline void
brw_inst_set_imm_df(const struct intel_device_info * devinfo,brw_inst * insn,double value)1015 brw_inst_set_imm_df(const struct intel_device_info *devinfo,
1016 brw_inst *insn, double value)
1017 {
1018 union {
1019 double d;
1020 uint64_t u;
1021 } dt;
1022 (void) devinfo;
1023 dt.d = value;
1024
1025 if (devinfo->ver >= 12) {
1026 brw_inst_set_bits(insn, 95, 64, dt.u >> 32);
1027 brw_inst_set_bits(insn, 127, 96, dt.u & 0xFFFFFFFF);
1028 } else {
1029 brw_inst_set_bits(insn, 127, 64, dt.u);
1030 }
1031 }
1032
1033 static inline void
brw_inst_set_imm_uq(const struct intel_device_info * devinfo,brw_inst * insn,uint64_t value)1034 brw_inst_set_imm_uq(const struct intel_device_info *devinfo,
1035 brw_inst *insn, uint64_t value)
1036 {
1037 (void) devinfo;
1038 if (devinfo->ver >= 12) {
1039 brw_inst_set_bits(insn, 95, 64, value >> 32);
1040 brw_inst_set_bits(insn, 127, 96, value & 0xFFFFFFFF);
1041 } else {
1042 brw_inst_set_bits(insn, 127, 64, value);
1043 }
1044 }
1045
1046 /** @} */
1047
1048 #define REG_TYPE(reg) \
1049 static inline void \
1050 brw_inst_set_##reg##_file_type(const struct intel_device_info *devinfo, \
1051 brw_inst *inst, enum brw_reg_file file, \
1052 enum brw_reg_type type) \
1053 { \
1054 assert(file <= IMM); \
1055 unsigned hw_type = brw_type_encode(devinfo, file, type); \
1056 brw_inst_set_##reg##_reg_file(devinfo, inst, file); \
1057 brw_inst_set_##reg##_reg_hw_type(devinfo, inst, hw_type); \
1058 } \
1059 \
1060 static inline enum brw_reg_type \
1061 brw_inst_##reg##_type(const struct intel_device_info *devinfo, \
1062 const brw_inst *inst) \
1063 { \
1064 unsigned file = __builtin_strcmp("dst", #reg) == 0 ? \
1065 (unsigned) FIXED_GRF : \
1066 brw_inst_##reg##_reg_file(devinfo, inst); \
1067 unsigned hw_type = brw_inst_##reg##_reg_hw_type(devinfo, inst); \
1068 return brw_type_decode(devinfo, (enum brw_reg_file)file, hw_type); \
1069 }
1070
1071 REG_TYPE(dst)
REG_TYPE(src0)1072 REG_TYPE(src0)
1073 REG_TYPE(src1)
1074 #undef REG_TYPE
1075
1076
1077 /* The AddrImm fields are split into two discontiguous sections on Gfx9+ */
1078 #define BRW_IA1_ADDR_IMM(reg, g9_nine, g9_high, g9_low, \
1079 g12_high, g12_low, g20_high, g20_low, g20_zero) \
1080 static inline void \
1081 brw_inst_set_##reg##_ia1_addr_imm(const struct \
1082 intel_device_info *devinfo, \
1083 brw_inst *inst, \
1084 unsigned value) \
1085 { \
1086 if (devinfo->ver >= 20) { \
1087 assert((value & ~0x7ff) == 0); \
1088 brw_inst_set_bits(inst, g20_high, g20_low, value >> 1); \
1089 if (g20_zero == -1) \
1090 assert((value & 1) == 0); \
1091 else \
1092 brw_inst_set_bits(inst, g20_zero, g20_zero, value & 1); \
1093 } else if (devinfo->ver >= 12) { \
1094 assert((value & ~0x3ff) == 0); \
1095 brw_inst_set_bits(inst, g12_high, g12_low, value); \
1096 } else { \
1097 assert((value & ~0x3ff) == 0); \
1098 brw_inst_set_bits(inst, g9_high, g9_low, value & 0x1ff); \
1099 brw_inst_set_bits(inst, g9_nine, g9_nine, value >> 9); \
1100 } \
1101 } \
1102 static inline unsigned \
1103 brw_inst_##reg##_ia1_addr_imm(const struct intel_device_info *devinfo, \
1104 const brw_inst *inst) \
1105 { \
1106 if (devinfo->ver >= 20) { \
1107 return brw_inst_bits(inst, g20_high, g20_low) << 1 | \
1108 (g20_zero == -1 ? 0 : \
1109 brw_inst_bits(inst, g20_zero, g20_zero)); \
1110 } else if (devinfo->ver >= 12) { \
1111 return brw_inst_bits(inst, g12_high, g12_low); \
1112 } else { \
1113 return brw_inst_bits(inst, g9_high, g9_low) | \
1114 (brw_inst_bits(inst, g9_nine, g9_nine) << 9); \
1115 } \
1116 }
1117
1118 /* AddrImm for Align1 Indirect Addressing */
1119 /* ----Gfx9---- -Gfx12- ---Gfx20--- */
1120 BRW_IA1_ADDR_IMM(src1, 121, 104, 96, 107, 98, 107, 98, -1)
1121 BRW_IA1_ADDR_IMM(src0, 95, 72, 64, 75, 66, 75, 66, 87)
1122 BRW_IA1_ADDR_IMM(dst, 47, 56, 48, 59, 50, 59, 50, 33)
1123
1124 #define BRW_IA16_ADDR_IMM(reg, g9_nine, g9_high, g9_low) \
1125 static inline void \
1126 brw_inst_set_##reg##_ia16_addr_imm(const struct \
1127 intel_device_info *devinfo, \
1128 brw_inst *inst, unsigned value) \
1129 { \
1130 assert(devinfo->ver < 12); \
1131 assert((value & ~0x3ff) == 0); \
1132 assert(GET_BITS(value, 3, 0) == 0); \
1133 brw_inst_set_bits(inst, g9_high, g9_low, GET_BITS(value, 8, 4)); \
1134 brw_inst_set_bits(inst, g9_nine, g9_nine, GET_BITS(value, 9, 9)); \
1135 } \
1136 static inline unsigned \
1137 brw_inst_##reg##_ia16_addr_imm(const struct intel_device_info *devinfo, \
1138 const brw_inst *inst) \
1139 { \
1140 assert(devinfo->ver < 12); \
1141 return (brw_inst_bits(inst, g9_high, g9_low) << 4) | \
1142 (brw_inst_bits(inst, g9_nine, g9_nine) << 9); \
1143 }
1144
1145 /* AddrImm[9:0] for Align16 Indirect Addressing:
1146 * Compared to Align1, these are missing the low 4 bits.
1147 * ----Gfx9----
1148 */
1149 BRW_IA16_ADDR_IMM(src1, 121, 104, 100)
1150 BRW_IA16_ADDR_IMM(src0, 95, 72, 68)
1151 BRW_IA16_ADDR_IMM(dst, 47, 56, 52)
1152 BRW_IA16_ADDR_IMM(send_src0, 78, 72, 68)
1153 BRW_IA16_ADDR_IMM(send_dst, 62, 56, 52)
1154
1155 /**
1156 * Fetch a set of contiguous bits from the instruction.
1157 *
1158 * Bits indices range from 0..127; fields may not cross 64-bit boundaries.
1159 */
1160 static inline uint64_t
1161 brw_inst_bits(const brw_inst *inst, unsigned high, unsigned low)
1162 {
1163 assume(high < 128);
1164 assume(high >= low);
1165 /* We assume the field doesn't cross 64-bit boundaries. */
1166 const unsigned word = high / 64;
1167 assert(word == low / 64);
1168
1169 high %= 64;
1170 low %= 64;
1171
1172 const uint64_t mask = (~0ull >> (64 - (high - low + 1)));
1173
1174 return (inst->data[word] >> low) & mask;
1175 }
1176
1177 /**
1178 * Set bits in the instruction, with proper shifting and masking.
1179 *
1180 * Bits indices range from 0..127; fields may not cross 64-bit boundaries.
1181 */
1182 static inline void
brw_inst_set_bits(brw_inst * inst,unsigned high,unsigned low,uint64_t value)1183 brw_inst_set_bits(brw_inst *inst, unsigned high, unsigned low, uint64_t value)
1184 {
1185 assume(high < 128);
1186 assume(high >= low);
1187 const unsigned word = high / 64;
1188 assert(word == low / 64);
1189
1190 high %= 64;
1191 low %= 64;
1192
1193 const uint64_t mask = (~0ull >> (64 - (high - low + 1))) << low;
1194
1195 /* Make sure the supplied value actually fits in the given bitfield. */
1196 assert((value & (mask >> low)) == value);
1197
1198 inst->data[word] = (inst->data[word] & ~mask) | (value << low);
1199 }
1200
1201 #undef BRW_IA16_ADDR_IMM
1202 #undef BRW_IA1_ADDR_IMM
1203 #undef MD
1204 #undef F
1205 #undef FC
1206 #undef F20
1207 #undef FD20
1208
1209 typedef struct {
1210 uint64_t data;
1211 } brw_compact_inst;
1212
1213 /**
1214 * Fetch a set of contiguous bits from the compacted instruction.
1215 *
1216 * Bits indices range from 0..63.
1217 */
1218 static inline unsigned
brw_compact_inst_bits(const brw_compact_inst * inst,unsigned high,unsigned low)1219 brw_compact_inst_bits(const brw_compact_inst *inst, unsigned high, unsigned low)
1220 {
1221 assume(high < 64);
1222 assume(high >= low);
1223 const uint64_t mask = (1ull << (high - low + 1)) - 1;
1224
1225 return (inst->data >> low) & mask;
1226 }
1227
1228 /**
1229 * Set bits in the compacted instruction.
1230 *
1231 * Bits indices range from 0..63.
1232 */
1233 static inline void
brw_compact_inst_set_bits(brw_compact_inst * inst,unsigned high,unsigned low,uint64_t value)1234 brw_compact_inst_set_bits(brw_compact_inst *inst, unsigned high, unsigned low,
1235 uint64_t value)
1236 {
1237 assume(high < 64);
1238 assume(high >= low);
1239 const uint64_t mask = ((1ull << (high - low + 1)) - 1) << low;
1240
1241 /* Make sure the supplied value actually fits in the given bitfield. */
1242 assert((value & (mask >> low)) == value);
1243
1244 inst->data = (inst->data & ~mask) | (value << low);
1245 }
1246
1247 #define FC(name, hi9, lo9, hi12, lo12, assertions) \
1248 static inline void \
1249 brw_compact_inst_set_##name(const struct \
1250 intel_device_info *devinfo, \
1251 brw_compact_inst *inst, unsigned v) \
1252 { \
1253 assert(assertions); \
1254 if (devinfo->ver >= 12) \
1255 brw_compact_inst_set_bits(inst, hi12, lo12, v); \
1256 else \
1257 brw_compact_inst_set_bits(inst, hi9, lo9, v); \
1258 } \
1259 static inline unsigned \
1260 brw_compact_inst_##name(const struct intel_device_info *devinfo, \
1261 const brw_compact_inst *inst) \
1262 { \
1263 assert(assertions); \
1264 if (devinfo->ver >= 12) \
1265 return brw_compact_inst_bits(inst, hi12, lo12); \
1266 else \
1267 return brw_compact_inst_bits(inst, hi9, lo9); \
1268 }
1269
1270 /* A simple macro for fields which stay in the same place on all generations
1271 * except for Gfx12.
1272 */
1273 #define F(name, hi9, lo9, hi12, lo12) FC(name, hi9, lo9, hi12, lo12, true)
1274
1275 /* A macro for fields which moved to several different locations
1276 * across generations.
1277 */
1278 #define F20(name, hi9, lo9, hi12, lo12, hi20, lo20) \
1279 static inline void \
1280 brw_compact_inst_set_##name(const struct \
1281 intel_device_info *devinfo, \
1282 brw_compact_inst *inst, unsigned v) \
1283 { \
1284 if (devinfo->ver >= 20) \
1285 brw_compact_inst_set_bits(inst, hi20, lo20, v); \
1286 else if (devinfo->ver >= 12) \
1287 brw_compact_inst_set_bits(inst, hi12, lo12, v); \
1288 else \
1289 brw_compact_inst_set_bits(inst, hi9, lo9, v); \
1290 } \
1291 static inline unsigned \
1292 brw_compact_inst_##name(const struct intel_device_info *devinfo, \
1293 const brw_compact_inst *inst) \
1294 { \
1295 if (devinfo->ver >= 20) \
1296 return brw_compact_inst_bits(inst, hi20, lo20); \
1297 else if (devinfo->ver >= 12) \
1298 return brw_compact_inst_bits(inst, hi12, lo12); \
1299 else \
1300 return brw_compact_inst_bits(inst, hi9, lo9); \
1301 }
1302
1303 /* A macro for fields which gained extra discontiguous bits in Gfx20
1304 * (specified by hi20ex-lo20ex).
1305 */
1306 #define FD20(name, hi9, lo9, hi12, lo12, \
1307 hi20, lo20, hi20ex, lo20ex) \
1308 static inline void \
1309 brw_compact_inst_set_##name(const struct \
1310 intel_device_info *devinfo, \
1311 brw_compact_inst *inst, unsigned v) \
1312 { \
1313 if (devinfo->ver >= 20) { \
1314 const unsigned k = hi20 - lo20 + 1; \
1315 brw_compact_inst_set_bits(inst, hi20ex, lo20ex, v >> k); \
1316 brw_compact_inst_set_bits(inst, hi20, lo20, v & ((1u << k) - 1)); \
1317 } else if (devinfo->ver >= 12) { \
1318 brw_compact_inst_set_bits(inst, hi12, lo12, v); \
1319 } else { \
1320 brw_compact_inst_set_bits(inst, hi9, lo9, v); \
1321 } \
1322 } \
1323 static inline unsigned \
1324 brw_compact_inst_##name(const struct intel_device_info *devinfo, \
1325 const brw_compact_inst *inst) \
1326 { \
1327 if (devinfo->ver >= 20) { \
1328 const unsigned k = hi20 - lo20 + 1; \
1329 return (brw_compact_inst_bits(inst, hi20ex, lo20ex) << k | \
1330 brw_compact_inst_bits(inst, hi20, lo20)); \
1331 } else if (devinfo->ver >= 12) { \
1332 return brw_compact_inst_bits(inst, hi12, lo12); \
1333 } else { \
1334 return brw_compact_inst_bits(inst, hi9, lo9); \
1335 } \
1336 }
1337
1338 F(src1_reg_nr, /* 9+ */ 63, 56, /* 12+ */ 63, 56)
1339 F(src0_reg_nr, /* 9+ */ 55, 48, /* 12+ */ 47, 40)
1340 F20(dst_reg_nr, /* 9+ */ 47, 40, /* 12+ */ 23, 16, /* 20+ */ 39, 32)
1341 F(src1_index, /* 9+ */ 39, 35, /* 12+ */ 55, 52)
1342 F20(src0_index, /* 9+ */ 34, 30, /* 12+ */ 51, 48, /* 20+ */ 25, 23)
1343 F(cmpt_control, /* 9+ */ 29, 29, /* 12+ */ 29, 29) /* Same location as brw_inst */
1344 F(cond_modifier, /* 9+ */ 27, 24, /* 12+ */ -1, -1) /* Same location as brw_inst */
1345 F(acc_wr_control, /* 9+ */ 23, 23, /* 12+ */ -1, -1)
1346 F20(subreg_index, /* 9+ */ 22, 18, /* 12+ */ 39, 35, /* 20+ */ 51, 48)
1347 FD20(datatype_index, /* 9+ */ 17, 13, /* 12+ */ 34, 30, /* 20+ */ 28, 26, 31, 30)
1348 F20(control_index, /* 9+ */ 12, 8, /* 12+ */ 28, 24, /* 20+ */ 22, 18)
1349 F20(swsb, /* 9+ */ -1, -1, /* 12+ */ 15, 8, /* 20+ */ 17, 8)
1350 F(debug_control, /* 9+ */ 7, 7, /* 12+ */ 7, 7)
1351 F(hw_opcode, /* 9+ */ 6, 0, /* 12+ */ 6, 0) /* Same location as brw_inst */
1352
1353 static inline unsigned
brw_compact_inst_imm(const struct intel_device_info * devinfo,const brw_compact_inst * inst)1354 brw_compact_inst_imm(const struct intel_device_info *devinfo,
1355 const brw_compact_inst *inst)
1356 {
1357 if (devinfo->ver >= 12) {
1358 return brw_compact_inst_bits(inst, 63, 52);
1359 } else {
1360 return (brw_compact_inst_bits(inst, 39, 35) << 8) |
1361 (brw_compact_inst_bits(inst, 63, 56));
1362 }
1363 }
1364
1365 /**
1366 * Compacted three-source instructions:
1367 * @{
1368 */
1369 F(3src_src2_reg_nr, /* 9+ */ 63, 57, /* 12+ */ 55, 48)
1370 F(3src_src1_reg_nr, /* 9+ */ 56, 50, /* 12+ */ 63, 56)
1371 F(3src_src0_reg_nr, /* 9+ */ 49, 43, /* 12+ */ 47, 40)
1372 F(3src_src2_subreg_nr, /* 9+ */ 42, 40, /* 12+ */ -1, -1)
1373 F(3src_src1_subreg_nr, /* 9+ */ 39, 37, /* 12+ */ -1, -1)
1374 F(3src_src0_subreg_nr, /* 9+ */ 36, 34, /* 12+ */ -1, -1)
1375 F(3src_src2_rep_ctrl, /* 9+ */ 33, 33, /* 12+ */ -1, -1)
1376 F(3src_src1_rep_ctrl, /* 9+ */ 32, 32, /* 12+ */ -1, -1)
1377 F(3src_saturate, /* 9+ */ 31, 31, /* 12+ */ -1, -1)
1378 F(3src_debug_control, /* 9+ */ 30, 30, /* 12+ */ 7, 7)
1379 F(3src_cmpt_control, /* 9+ */ 29, 29, /* 12+ */ 29, 29)
1380 F(3src_src0_rep_ctrl, /* 9+ */ 28, 28, /* 12+ */ -1, -1)
1381 /* Reserved */
1382 F20(3src_dst_reg_nr, /* 9+ */ 18, 12, /* 12+ */ 23, 16, /* 20+ */ 39, 32)
1383 F20(3src_source_index, /* 9+ */ 11, 10, /* 12+ */ 34, 30, /* 20+ */ 25, 22)
1384 FD20(3src_subreg_index, /* 9+ */ -1, -1, /* 12+ */ 39, 35, /* 20+ */ 28, 26, 31, 30)
1385 F20(3src_control_index, /* 9+ */ 9, 8, /* 12+ */ 28, 24, /* 20+ */ 21, 18)
1386 F20(3src_swsb, /* 9+ */ -1, -1, /* 12+ */ 15, 8, /* 20+ */ 17, 8)
1387 /* Bit 7 is Reserved (for future Opcode expansion) */
1388 F(3src_hw_opcode, /* 9+ */ 6, 0, /* 12+ */ 6, 0)
1389 /** @} */
1390
1391 #undef F
1392
1393 static inline void
brw_inst_set_opcode(const struct brw_isa_info * isa,struct brw_inst * inst,enum opcode opcode)1394 brw_inst_set_opcode(const struct brw_isa_info *isa,
1395 struct brw_inst *inst, enum opcode opcode)
1396 {
1397 brw_inst_set_hw_opcode(isa->devinfo, inst, brw_opcode_encode(isa, opcode));
1398 }
1399
1400 static inline enum opcode
brw_inst_opcode(const struct brw_isa_info * isa,const struct brw_inst * inst)1401 brw_inst_opcode(const struct brw_isa_info *isa,
1402 const struct brw_inst *inst)
1403 {
1404 return brw_opcode_decode(isa, brw_inst_hw_opcode(isa->devinfo, inst));
1405 }
1406
1407 #ifdef __cplusplus
1408 }
1409 #endif
1410
1411 #endif
1412