1 /*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 /** @file
25 *
26 * Support for global copy propagation in two passes: A local pass that does
27 * intra-block copy (and constant) propagation, and a global pass that uses
28 * dataflow analysis on the copies available at the end of each block to re-do
29 * local copy propagation with more copies available.
30 *
31 * See Muchnick's Advanced Compiler Design and Implementation, section
32 * 12.5 (p356).
33 */
34
35 #include "util/bitset.h"
36 #include "util/u_math.h"
37 #include "util/rb_tree.h"
38 #include "brw_fs.h"
39 #include "brw_fs_live_variables.h"
40 #include "brw_cfg.h"
41 #include "brw_eu.h"
42
43 using namespace brw;
44
45 namespace { /* avoid conflict with opt_copy_propagation_elements */
46 struct acp_entry {
47 struct rb_node by_dst;
48 struct rb_node by_src;
49 brw_reg dst;
50 brw_reg src;
51 unsigned global_idx;
52 unsigned size_written;
53 unsigned size_read;
54 enum opcode opcode;
55 bool is_partial_write;
56 bool force_writemask_all;
57 };
58
59 /**
60 * Compare two acp_entry::src.nr
61 *
62 * This is intended to be used as the comparison function for rb_tree.
63 */
64 static int
cmp_entry_dst_entry_dst(const struct rb_node * a_node,const struct rb_node * b_node)65 cmp_entry_dst_entry_dst(const struct rb_node *a_node, const struct rb_node *b_node)
66 {
67 const struct acp_entry *a_entry =
68 rb_node_data(struct acp_entry, a_node, by_dst);
69
70 const struct acp_entry *b_entry =
71 rb_node_data(struct acp_entry, b_node, by_dst);
72
73 return a_entry->dst.nr - b_entry->dst.nr;
74 }
75
76 static int
cmp_entry_dst_nr(const struct rb_node * a_node,const void * b_key)77 cmp_entry_dst_nr(const struct rb_node *a_node, const void *b_key)
78 {
79 const struct acp_entry *a_entry =
80 rb_node_data(struct acp_entry, a_node, by_dst);
81
82 return a_entry->dst.nr - (uintptr_t) b_key;
83 }
84
85 static int
cmp_entry_src_entry_src(const struct rb_node * a_node,const struct rb_node * b_node)86 cmp_entry_src_entry_src(const struct rb_node *a_node, const struct rb_node *b_node)
87 {
88 const struct acp_entry *a_entry =
89 rb_node_data(struct acp_entry, a_node, by_src);
90
91 const struct acp_entry *b_entry =
92 rb_node_data(struct acp_entry, b_node, by_src);
93
94 return a_entry->src.nr - b_entry->src.nr;
95 }
96
97 /**
98 * Compare an acp_entry::src.nr with a raw nr.
99 *
100 * This is intended to be used as the comparison function for rb_tree.
101 */
102 static int
cmp_entry_src_nr(const struct rb_node * a_node,const void * b_key)103 cmp_entry_src_nr(const struct rb_node *a_node, const void *b_key)
104 {
105 const struct acp_entry *a_entry =
106 rb_node_data(struct acp_entry, a_node, by_src);
107
108 return a_entry->src.nr - (uintptr_t) b_key;
109 }
110
111 class acp_forward_iterator {
112 public:
acp_forward_iterator(struct rb_node * n,unsigned offset)113 acp_forward_iterator(struct rb_node *n, unsigned offset)
114 : curr(n), next(nullptr), offset(offset)
115 {
116 next = rb_node_next_or_null(curr);
117 }
118
operator ++()119 acp_forward_iterator &operator++()
120 {
121 curr = next;
122 next = rb_node_next_or_null(curr);
123
124 return *this;
125 }
126
operator !=(const acp_forward_iterator & other) const127 bool operator!=(const acp_forward_iterator &other) const
128 {
129 return curr != other.curr;
130 }
131
operator *() const132 struct acp_entry *operator*() const
133 {
134 /* This open-codes part of rb_node_data. */
135 return curr != NULL ? (struct acp_entry *)(((char *)curr) - offset)
136 : NULL;
137 }
138
139 private:
140 struct rb_node *curr;
141 struct rb_node *next;
142 unsigned offset;
143 };
144
145 struct acp {
146 struct rb_tree by_dst;
147 struct rb_tree by_src;
148
acp__anon439490700111::acp149 acp()
150 {
151 rb_tree_init(&by_dst);
152 rb_tree_init(&by_src);
153 }
154
begin__anon439490700111::acp155 acp_forward_iterator begin()
156 {
157 return acp_forward_iterator(rb_tree_first(&by_src),
158 rb_tree_offsetof(struct acp_entry, by_src, 0));
159 }
160
end__anon439490700111::acp161 const acp_forward_iterator end() const
162 {
163 return acp_forward_iterator(nullptr, 0);
164 }
165
length__anon439490700111::acp166 unsigned length()
167 {
168 unsigned l = 0;
169
170 for (rb_node *iter = rb_tree_first(&by_src);
171 iter != NULL; iter = rb_node_next(iter))
172 l++;
173
174 return l;
175 }
176
add__anon439490700111::acp177 void add(acp_entry *entry)
178 {
179 rb_tree_insert(&by_dst, &entry->by_dst, cmp_entry_dst_entry_dst);
180 rb_tree_insert(&by_src, &entry->by_src, cmp_entry_src_entry_src);
181 }
182
remove__anon439490700111::acp183 void remove(acp_entry *entry)
184 {
185 rb_tree_remove(&by_dst, &entry->by_dst);
186 rb_tree_remove(&by_src, &entry->by_src);
187 }
188
find_by_src__anon439490700111::acp189 acp_forward_iterator find_by_src(unsigned nr)
190 {
191 struct rb_node *rbn = rb_tree_search(&by_src,
192 (void *)(uintptr_t) nr,
193 cmp_entry_src_nr);
194
195 return acp_forward_iterator(rbn, rb_tree_offsetof(struct acp_entry,
196 by_src, rbn));
197 }
198
find_by_dst__anon439490700111::acp199 acp_forward_iterator find_by_dst(unsigned nr)
200 {
201 struct rb_node *rbn = rb_tree_search(&by_dst,
202 (void *)(uintptr_t) nr,
203 cmp_entry_dst_nr);
204
205 return acp_forward_iterator(rbn, rb_tree_offsetof(struct acp_entry,
206 by_dst, rbn));
207 }
208 };
209
210 struct block_data {
211 /**
212 * Which entries in the fs_copy_prop_dataflow acp table are live at the
213 * start of this block. This is the useful output of the analysis, since
214 * it lets us plug those into the local copy propagation on the second
215 * pass.
216 */
217 BITSET_WORD *livein;
218
219 /**
220 * Which entries in the fs_copy_prop_dataflow acp table are live at the end
221 * of this block. This is done in initial setup from the per-block acps
222 * returned by the first local copy prop pass.
223 */
224 BITSET_WORD *liveout;
225
226 /**
227 * Which entries in the fs_copy_prop_dataflow acp table are generated by
228 * instructions in this block which reach the end of the block without
229 * being killed.
230 */
231 BITSET_WORD *copy;
232
233 /**
234 * Which entries in the fs_copy_prop_dataflow acp table are killed over the
235 * course of this block.
236 */
237 BITSET_WORD *kill;
238
239 /**
240 * Which entries in the fs_copy_prop_dataflow acp table are guaranteed to
241 * have a fully uninitialized destination at the end of this block.
242 */
243 BITSET_WORD *undef;
244
245 /**
246 * Which entries in the fs_copy_prop_dataflow acp table can the
247 * start of this block be reached from. Note that this is a weaker
248 * condition than livein.
249 */
250 BITSET_WORD *reachin;
251
252 /**
253 * Which entries in the fs_copy_prop_dataflow acp table are
254 * overwritten by an instruction with channel masks inconsistent
255 * with the copy instruction (e.g. due to force_writemask_all).
256 * Such an overwrite can cause the copy entry to become invalid
257 * even if the copy instruction is subsequently re-executed for any
258 * given channel i, since the execution of the overwrite for
259 * channel i may corrupt other channels j!=i inactive for the
260 * subsequent copy.
261 */
262 BITSET_WORD *exec_mismatch;
263 };
264
265 class fs_copy_prop_dataflow
266 {
267 public:
268 fs_copy_prop_dataflow(linear_ctx *lin_ctx, cfg_t *cfg,
269 const fs_live_variables &live,
270 struct acp *out_acp);
271
272 void setup_initial_values();
273 void run();
274
275 void dump_block_data() const UNUSED;
276
277 cfg_t *cfg;
278 const fs_live_variables &live;
279
280 acp_entry **acp;
281 int num_acp;
282 int bitset_words;
283
284 struct block_data *bd;
285 };
286 } /* anonymous namespace */
287
fs_copy_prop_dataflow(linear_ctx * lin_ctx,cfg_t * cfg,const fs_live_variables & live,struct acp * out_acp)288 fs_copy_prop_dataflow::fs_copy_prop_dataflow(linear_ctx *lin_ctx, cfg_t *cfg,
289 const fs_live_variables &live,
290 struct acp *out_acp)
291 : cfg(cfg), live(live)
292 {
293 bd = linear_zalloc_array(lin_ctx, struct block_data, cfg->num_blocks);
294
295 num_acp = 0;
296 foreach_block (block, cfg)
297 num_acp += out_acp[block->num].length();
298
299 bitset_words = BITSET_WORDS(num_acp);
300
301 foreach_block (block, cfg) {
302 bd[block->num].livein = linear_zalloc_array(lin_ctx, BITSET_WORD, bitset_words);
303 bd[block->num].liveout = linear_zalloc_array(lin_ctx, BITSET_WORD, bitset_words);
304 bd[block->num].copy = linear_zalloc_array(lin_ctx, BITSET_WORD, bitset_words);
305 bd[block->num].kill = linear_zalloc_array(lin_ctx, BITSET_WORD, bitset_words);
306 bd[block->num].undef = linear_zalloc_array(lin_ctx, BITSET_WORD, bitset_words);
307 bd[block->num].reachin = linear_zalloc_array(lin_ctx, BITSET_WORD, bitset_words);
308 bd[block->num].exec_mismatch = linear_zalloc_array(lin_ctx, BITSET_WORD, bitset_words);
309 }
310
311 acp = linear_zalloc_array(lin_ctx, struct acp_entry *, num_acp);
312
313 int next_acp = 0;
314 foreach_block (block, cfg) {
315 for (auto iter = out_acp[block->num].begin();
316 iter != out_acp[block->num].end(); ++iter) {
317 acp[next_acp] = *iter;
318
319 (*iter)->global_idx = next_acp;
320
321 /* opt_copy_propagation_local populates out_acp with copies created
322 * in a block which are still live at the end of the block. This
323 * is exactly what we want in the COPY set.
324 */
325 BITSET_SET(bd[block->num].copy, next_acp);
326
327 next_acp++;
328 }
329 }
330
331 assert(next_acp == num_acp);
332
333 setup_initial_values();
334 run();
335 }
336
337 /**
338 * Like reg_offset, but register must be VGRF or FIXED_GRF.
339 */
340 static inline unsigned
grf_reg_offset(const brw_reg & r)341 grf_reg_offset(const brw_reg &r)
342 {
343 return (r.file == VGRF ? 0 : r.nr) * REG_SIZE +
344 r.offset +
345 (r.file == FIXED_GRF ? r.subnr : 0);
346 }
347
348 /**
349 * Like regions_overlap, but register must be VGRF or FIXED_GRF.
350 */
351 static inline bool
grf_regions_overlap(const brw_reg & r,unsigned dr,const brw_reg & s,unsigned ds)352 grf_regions_overlap(const brw_reg &r, unsigned dr, const brw_reg &s, unsigned ds)
353 {
354 return reg_space(r) == reg_space(s) &&
355 !(grf_reg_offset(r) + dr <= grf_reg_offset(s) ||
356 grf_reg_offset(s) + ds <= grf_reg_offset(r));
357 }
358
359 /**
360 * Set up initial values for each of the data flow sets, prior to running
361 * the fixed-point algorithm.
362 */
363 void
setup_initial_values()364 fs_copy_prop_dataflow::setup_initial_values()
365 {
366 /* Initialize the COPY and KILL sets. */
367 {
368 struct acp acp_table;
369
370 /* First, get all the KILLs for instructions which overwrite ACP
371 * destinations.
372 */
373 for (int i = 0; i < num_acp; i++)
374 acp_table.add(acp[i]);
375
376 foreach_block (block, cfg) {
377 foreach_inst_in_block(fs_inst, inst, block) {
378 if (inst->dst.file != VGRF &&
379 inst->dst.file != FIXED_GRF)
380 continue;
381
382 for (auto iter = acp_table.find_by_src(inst->dst.nr);
383 iter != acp_table.end() && (*iter)->src.nr == inst->dst.nr;
384 ++iter) {
385 if (grf_regions_overlap(inst->dst, inst->size_written,
386 (*iter)->src, (*iter)->size_read)) {
387 BITSET_SET(bd[block->num].kill, (*iter)->global_idx);
388 if (inst->force_writemask_all && !(*iter)->force_writemask_all)
389 BITSET_SET(bd[block->num].exec_mismatch, (*iter)->global_idx);
390 }
391 }
392
393 if (inst->dst.file != VGRF)
394 continue;
395
396 for (auto iter = acp_table.find_by_dst(inst->dst.nr);
397 iter != acp_table.end() && (*iter)->dst.nr == inst->dst.nr;
398 ++iter) {
399 if (grf_regions_overlap(inst->dst, inst->size_written,
400 (*iter)->dst, (*iter)->size_written)) {
401 BITSET_SET(bd[block->num].kill, (*iter)->global_idx);
402 if (inst->force_writemask_all && !(*iter)->force_writemask_all)
403 BITSET_SET(bd[block->num].exec_mismatch, (*iter)->global_idx);
404 }
405 }
406 }
407 }
408 }
409
410 /* Populate the initial values for the livein and liveout sets. For the
411 * block at the start of the program, livein = 0 and liveout = copy.
412 * For the others, set liveout and livein to ~0 (the universal set).
413 */
414 foreach_block (block, cfg) {
415 if (block->parents.is_empty()) {
416 for (int i = 0; i < bitset_words; i++) {
417 bd[block->num].livein[i] = 0u;
418 bd[block->num].liveout[i] = bd[block->num].copy[i];
419 }
420 } else {
421 for (int i = 0; i < bitset_words; i++) {
422 bd[block->num].liveout[i] = ~0u;
423 bd[block->num].livein[i] = ~0u;
424 }
425 }
426 }
427
428 /* Initialize the undef set. */
429 foreach_block (block, cfg) {
430 for (int i = 0; i < num_acp; i++) {
431 BITSET_SET(bd[block->num].undef, i);
432 for (unsigned off = 0; off < acp[i]->size_written; off += REG_SIZE) {
433 if (BITSET_TEST(live.block_data[block->num].defout,
434 live.var_from_reg(byte_offset(acp[i]->dst, off))))
435 BITSET_CLEAR(bd[block->num].undef, i);
436 }
437 }
438 }
439 }
440
441 /**
442 * Walk the set of instructions in the block, marking which entries in the acp
443 * are killed by the block.
444 */
445 void
run()446 fs_copy_prop_dataflow::run()
447 {
448 bool progress;
449
450 do {
451 progress = false;
452
453 foreach_block (block, cfg) {
454 if (block->parents.is_empty())
455 continue;
456
457 for (int i = 0; i < bitset_words; i++) {
458 const BITSET_WORD old_liveout = bd[block->num].liveout[i];
459 const BITSET_WORD old_reachin = bd[block->num].reachin[i];
460 BITSET_WORD livein_from_any_block = 0;
461
462 /* Update livein for this block. If a copy is live out of all
463 * parent blocks, it's live coming in to this block.
464 */
465 bd[block->num].livein[i] = ~0u;
466 foreach_list_typed(bblock_link, parent_link, link, &block->parents) {
467 bblock_t *parent = parent_link->block;
468 /* Consider ACP entries with a known-undefined destination to
469 * be available from the parent. This is valid because we're
470 * free to set the undefined variable equal to the source of
471 * the ACP entry without breaking the application's
472 * expectations, since the variable is undefined.
473 */
474 bd[block->num].livein[i] &= (bd[parent->num].liveout[i] |
475 bd[parent->num].undef[i]);
476 livein_from_any_block |= bd[parent->num].liveout[i];
477
478 /* Update reachin for this block. If the end of any
479 * parent block is reachable from the copy, the start
480 * of this block is reachable from it as well.
481 */
482 bd[block->num].reachin[i] |= (bd[parent->num].reachin[i] |
483 bd[parent->num].copy[i]);
484 }
485
486 /* Limit to the set of ACP entries that can possibly be available
487 * at the start of the block, since propagating from a variable
488 * which is guaranteed to be undefined (rather than potentially
489 * undefined for some dynamic control-flow paths) doesn't seem
490 * particularly useful.
491 */
492 bd[block->num].livein[i] &= livein_from_any_block;
493
494 /* Update liveout for this block. */
495 bd[block->num].liveout[i] =
496 bd[block->num].copy[i] | (bd[block->num].livein[i] &
497 ~bd[block->num].kill[i]);
498
499 if (old_liveout != bd[block->num].liveout[i] ||
500 old_reachin != bd[block->num].reachin[i])
501 progress = true;
502 }
503 }
504 } while (progress);
505
506 /* Perform a second fixed-point pass in order to propagate the
507 * exec_mismatch bitsets. Note that this requires an accurate
508 * value of the reachin bitsets as input, which isn't available
509 * until the end of the first propagation pass, so this loop cannot
510 * be folded into the previous one.
511 */
512 do {
513 progress = false;
514
515 foreach_block (block, cfg) {
516 for (int i = 0; i < bitset_words; i++) {
517 const BITSET_WORD old_exec_mismatch = bd[block->num].exec_mismatch[i];
518
519 /* Update exec_mismatch for this block. If the end of a
520 * parent block is reachable by an overwrite with
521 * inconsistent execution masking, the start of this block
522 * is reachable by such an overwrite as well.
523 */
524 foreach_list_typed(bblock_link, parent_link, link, &block->parents) {
525 bblock_t *parent = parent_link->block;
526 bd[block->num].exec_mismatch[i] |= (bd[parent->num].exec_mismatch[i] &
527 bd[parent->num].reachin[i]);
528 }
529
530 /* Only consider overwrites with inconsistent execution
531 * masking if they are reachable from the copy, since
532 * overwrites unreachable from a copy are harmless to that
533 * copy.
534 */
535 bd[block->num].exec_mismatch[i] &= bd[block->num].reachin[i];
536 if (old_exec_mismatch != bd[block->num].exec_mismatch[i])
537 progress = true;
538 }
539 }
540 } while (progress);
541 }
542
543 void
dump_block_data() const544 fs_copy_prop_dataflow::dump_block_data() const
545 {
546 foreach_block (block, cfg) {
547 fprintf(stderr, "Block %d [%d, %d] (parents ", block->num,
548 block->start_ip, block->end_ip);
549 foreach_list_typed(bblock_link, link, link, &block->parents) {
550 bblock_t *parent = link->block;
551 fprintf(stderr, "%d ", parent->num);
552 }
553 fprintf(stderr, "):\n");
554 fprintf(stderr, " livein = 0x");
555 for (int i = 0; i < bitset_words; i++)
556 fprintf(stderr, "%08x", bd[block->num].livein[i]);
557 fprintf(stderr, ", liveout = 0x");
558 for (int i = 0; i < bitset_words; i++)
559 fprintf(stderr, "%08x", bd[block->num].liveout[i]);
560 fprintf(stderr, ",\n copy = 0x");
561 for (int i = 0; i < bitset_words; i++)
562 fprintf(stderr, "%08x", bd[block->num].copy[i]);
563 fprintf(stderr, ", kill = 0x");
564 for (int i = 0; i < bitset_words; i++)
565 fprintf(stderr, "%08x", bd[block->num].kill[i]);
566 fprintf(stderr, "\n");
567 }
568 }
569
570 static bool
is_logic_op(enum opcode opcode)571 is_logic_op(enum opcode opcode)
572 {
573 return (opcode == BRW_OPCODE_AND ||
574 opcode == BRW_OPCODE_OR ||
575 opcode == BRW_OPCODE_XOR ||
576 opcode == BRW_OPCODE_NOT);
577 }
578
579 static bool
can_take_stride(fs_inst * inst,brw_reg_type dst_type,unsigned arg,unsigned stride,const struct brw_compiler * compiler)580 can_take_stride(fs_inst *inst, brw_reg_type dst_type,
581 unsigned arg, unsigned stride,
582 const struct brw_compiler *compiler)
583 {
584 const struct intel_device_info *devinfo = compiler->devinfo;
585
586 if (stride > 4)
587 return false;
588
589 /* Bail if the channels of the source need to be aligned to the byte offset
590 * of the corresponding channel of the destination, and the provided stride
591 * would break this restriction.
592 */
593 if (has_dst_aligned_region_restriction(devinfo, inst, dst_type) &&
594 !(brw_type_size_bytes(inst->src[arg].type) * stride ==
595 brw_type_size_bytes(dst_type) * inst->dst.stride ||
596 stride == 0))
597 return false;
598
599 /* 3-source instructions can only be Align16, which restricts what strides
600 * they can take. They can only take a stride of 1 (the usual case), or 0
601 * with a special "repctrl" bit. But the repctrl bit doesn't work for
602 * 64-bit datatypes, so if the source type is 64-bit then only a stride of
603 * 1 is allowed. From the Broadwell PRM, Volume 7 "3D Media GPGPU", page
604 * 944:
605 *
606 * This is applicable to 32b datatypes and 16b datatype. 64b datatypes
607 * cannot use the replicate control.
608 */
609 if (inst->is_3src(compiler)) {
610 if (brw_type_size_bytes(inst->src[arg].type) > 4)
611 return stride == 1;
612 else
613 return stride == 1 || stride == 0;
614 }
615
616 if (inst->is_math()) {
617 /* Wa_22016140776:
618 *
619 * Scalar broadcast on HF math (packed or unpacked) must not be used.
620 * Compiler must use a mov instruction to expand the scalar value to
621 * a vector before using in a HF (packed or unpacked) math operation.
622 *
623 * Prevent copy propagating a scalar value into a math instruction.
624 */
625 if (intel_needs_workaround(devinfo, 22016140776) &&
626 stride == 0 && inst->src[arg].type == BRW_TYPE_HF) {
627 return false;
628 }
629
630 /* From the Broadwell PRM, Volume 2a "Command Reference - Instructions",
631 * page 391 ("Extended Math Function"):
632 *
633 * The following restrictions apply for align1 mode: Scalar source
634 * is supported. Source and destination horizontal stride must be
635 * the same.
636 */
637 return stride == inst->dst.stride || stride == 0;
638 }
639
640 return true;
641 }
642
643 static bool
instruction_requires_packed_data(fs_inst * inst)644 instruction_requires_packed_data(fs_inst *inst)
645 {
646 switch (inst->opcode) {
647 case FS_OPCODE_DDX_FINE:
648 case FS_OPCODE_DDX_COARSE:
649 case FS_OPCODE_DDY_FINE:
650 case FS_OPCODE_DDY_COARSE:
651 case SHADER_OPCODE_QUAD_SWIZZLE:
652 return true;
653 default:
654 return false;
655 }
656 }
657
658 static bool
try_copy_propagate(const brw_compiler * compiler,fs_inst * inst,acp_entry * entry,int arg,const brw::simple_allocator & alloc,uint8_t max_polygons)659 try_copy_propagate(const brw_compiler *compiler, fs_inst *inst,
660 acp_entry *entry, int arg,
661 const brw::simple_allocator &alloc,
662 uint8_t max_polygons)
663 {
664 if (inst->src[arg].file != VGRF)
665 return false;
666
667 const struct intel_device_info *devinfo = compiler->devinfo;
668
669 assert(entry->src.file == VGRF || entry->src.file == UNIFORM ||
670 entry->src.file == ATTR || entry->src.file == FIXED_GRF);
671
672 /* Avoid propagating a LOAD_PAYLOAD instruction into another if there is a
673 * good chance that we'll be able to eliminate the latter through register
674 * coalescing. If only part of the sources of the second LOAD_PAYLOAD can
675 * be simplified through copy propagation we would be making register
676 * coalescing impossible, ending up with unnecessary copies in the program.
677 * This is also the case for is_multi_copy_payload() copies that can only
678 * be coalesced when the instruction is lowered into a sequence of MOVs.
679 *
680 * Worse -- In cases where the ACP entry was the result of CSE combining
681 * multiple LOAD_PAYLOAD subexpressions, propagating the first LOAD_PAYLOAD
682 * into the second would undo the work of CSE, leading to an infinite
683 * optimization loop. Avoid this by detecting LOAD_PAYLOAD copies from CSE
684 * temporaries which should match is_coalescing_payload().
685 */
686 if (entry->opcode == SHADER_OPCODE_LOAD_PAYLOAD &&
687 (is_coalescing_payload(alloc, inst) || is_multi_copy_payload(inst)))
688 return false;
689
690 assert(entry->dst.file == VGRF);
691 if (inst->src[arg].nr != entry->dst.nr)
692 return false;
693
694 /* Bail if inst is reading a range that isn't contained in the range
695 * that entry is writing.
696 */
697 if (!region_contained_in(inst->src[arg], inst->size_read(arg),
698 entry->dst, entry->size_written))
699 return false;
700
701 /* Send messages with EOT set are restricted to use g112-g127 (and we
702 * sometimes need g127 for other purposes), so avoid copy propagating
703 * anything that would make it impossible to satisfy that restriction.
704 */
705 if (inst->eot) {
706 /* Don't propagate things that are already pinned. */
707 if (entry->src.file != VGRF)
708 return false;
709
710 /* We might be propagating from a large register, while the SEND only
711 * is reading a portion of it (say the .A channel in an RGBA value).
712 * We need to pin both split SEND sources in g112-g126/127, so only
713 * allow this if the registers aren't too large.
714 */
715 if (inst->opcode == SHADER_OPCODE_SEND && inst->sources >= 4 &&
716 entry->src.file == VGRF) {
717 int other_src = arg == 2 ? 3 : 2;
718 unsigned other_size = inst->src[other_src].file == VGRF ?
719 alloc.sizes[inst->src[other_src].nr] :
720 inst->size_read(other_src);
721 unsigned prop_src_size = alloc.sizes[entry->src.nr];
722 if (other_size + prop_src_size > 15)
723 return false;
724 }
725 }
726
727 /* we can't generally copy-propagate UD negations because we
728 * can end up accessing the resulting values as signed integers
729 * instead. See also resolve_ud_negate() and comment in
730 * fs_generator::generate_code.
731 */
732 if (entry->src.type == BRW_TYPE_UD &&
733 entry->src.negate)
734 return false;
735
736 bool has_source_modifiers = entry->src.abs || entry->src.negate;
737
738 if (has_source_modifiers && !inst->can_do_source_mods(devinfo))
739 return false;
740
741 /* Reject cases that would violate register regioning restrictions. */
742 if ((entry->src.file == UNIFORM || !entry->src.is_contiguous()) &&
743 (inst->is_send_from_grf() ||
744 inst->uses_indirect_addressing())) {
745 return false;
746 }
747
748 /* Some instructions implemented in the generator backend, such as
749 * derivatives, assume that their operands are packed so we can't
750 * generally propagate strided regions to them.
751 */
752 const unsigned entry_stride = (entry->src.file == FIXED_GRF ? 1 :
753 entry->src.stride);
754 if (instruction_requires_packed_data(inst) && entry_stride != 1)
755 return false;
756
757 const brw_reg_type dst_type = (has_source_modifiers &&
758 entry->dst.type != inst->src[arg].type) ?
759 entry->dst.type : inst->dst.type;
760
761 /* Bail if the result of composing both strides would exceed the
762 * hardware limit.
763 */
764 if (!can_take_stride(inst, dst_type, arg,
765 entry_stride * inst->src[arg].stride,
766 compiler))
767 return false;
768
769 /* From the Cherry Trail/Braswell PRMs, Volume 7: 3D Media GPGPU:
770 * EU Overview
771 * Register Region Restrictions
772 * Special Requirements for Handling Double Precision Data Types :
773 *
774 * "When source or destination datatype is 64b or operation is integer
775 * DWord multiply, regioning in Align1 must follow these rules:
776 *
777 * 1. Source and Destination horizontal stride must be aligned to the
778 * same qword.
779 * 2. Regioning must ensure Src.Vstride = Src.Width * Src.Hstride.
780 * 3. Source and Destination offset must be the same, except the case
781 * of scalar source."
782 *
783 * Most of this is already checked in can_take_stride(), we're only left
784 * with checking 3.
785 */
786 if (has_dst_aligned_region_restriction(devinfo, inst, dst_type) &&
787 entry_stride != 0 &&
788 (reg_offset(inst->dst) % (REG_SIZE * reg_unit(devinfo))) != (reg_offset(entry->src) % (REG_SIZE * reg_unit(devinfo))))
789 return false;
790
791 /*
792 * Bail if the composition of both regions would be affected by the Xe2+
793 * regioning restrictions that apply to integer types smaller than a dword.
794 * See BSpec #56640 for details.
795 */
796 const brw_reg tmp = horiz_stride(entry->src, inst->src[arg].stride);
797 if (has_subdword_integer_region_restriction(devinfo, inst, &tmp, 1))
798 return false;
799
800 /* The <8;8,0> regions used for FS attributes in multipolygon
801 * dispatch mode could violate regioning restrictions, don't copy
802 * propagate them in such cases.
803 */
804 if (entry->src.file == ATTR && max_polygons > 1 &&
805 (has_dst_aligned_region_restriction(devinfo, inst, dst_type) ||
806 instruction_requires_packed_data(inst) ||
807 (inst->is_3src(compiler) && arg == 2) ||
808 entry->dst.type != inst->src[arg].type))
809 return false;
810
811 /* Bail if the source FIXED_GRF region of the copy cannot be trivially
812 * composed with the source region of the instruction -- E.g. because the
813 * copy uses some extended stride greater than 4 not supported natively by
814 * the hardware as a horizontal stride, or because instruction compression
815 * could require us to use a vertical stride shorter than a GRF.
816 */
817 if (entry->src.file == FIXED_GRF &&
818 (inst->src[arg].stride > 4 ||
819 inst->dst.component_size(inst->exec_size) >
820 inst->src[arg].component_size(inst->exec_size)))
821 return false;
822
823 /* Bail if the instruction type is larger than the execution type of the
824 * copy, what implies that each channel is reading multiple channels of the
825 * destination of the copy, and simply replacing the sources would give a
826 * program with different semantics.
827 */
828 if ((brw_type_size_bits(entry->dst.type) < brw_type_size_bits(inst->src[arg].type) ||
829 entry->is_partial_write) &&
830 inst->opcode != BRW_OPCODE_MOV) {
831 return false;
832 }
833
834 /* Bail if the result of composing both strides cannot be expressed
835 * as another stride. This avoids, for example, trying to transform
836 * this:
837 *
838 * MOV (8) rX<1>UD rY<0;1,0>UD
839 * FOO (8) ... rX<8;8,1>UW
840 *
841 * into this:
842 *
843 * FOO (8) ... rY<0;1,0>UW
844 *
845 * Which would have different semantics.
846 */
847 if (entry_stride != 1 &&
848 (inst->src[arg].stride *
849 brw_type_size_bytes(inst->src[arg].type)) % brw_type_size_bytes(entry->src.type) != 0)
850 return false;
851
852 /* Since semantics of source modifiers are type-dependent we need to
853 * ensure that the meaning of the instruction remains the same if we
854 * change the type. If the sizes of the types are different the new
855 * instruction will read a different amount of data than the original
856 * and the semantics will always be different.
857 */
858 if (has_source_modifiers &&
859 entry->dst.type != inst->src[arg].type &&
860 (!inst->can_change_types() ||
861 brw_type_size_bits(entry->dst.type) != brw_type_size_bits(inst->src[arg].type)))
862 return false;
863
864 if ((entry->src.negate || entry->src.abs) &&
865 is_logic_op(inst->opcode)) {
866 return false;
867 }
868
869 /* Save the offset of inst->src[arg] relative to entry->dst for it to be
870 * applied later.
871 */
872 const unsigned rel_offset = inst->src[arg].offset - entry->dst.offset;
873
874 /* Fold the copy into the instruction consuming it. */
875 inst->src[arg].file = entry->src.file;
876 inst->src[arg].nr = entry->src.nr;
877 inst->src[arg].subnr = entry->src.subnr;
878 inst->src[arg].offset = entry->src.offset;
879
880 /* Compose the strides of both regions. */
881 if (entry->src.file == FIXED_GRF) {
882 if (inst->src[arg].stride) {
883 const unsigned orig_width = 1 << entry->src.width;
884 const unsigned reg_width =
885 REG_SIZE / (brw_type_size_bytes(inst->src[arg].type) *
886 inst->src[arg].stride);
887 inst->src[arg].width = cvt(MIN2(orig_width, reg_width)) - 1;
888 inst->src[arg].hstride = cvt(inst->src[arg].stride);
889 inst->src[arg].vstride = inst->src[arg].hstride + inst->src[arg].width;
890 } else {
891 inst->src[arg].vstride = inst->src[arg].hstride =
892 inst->src[arg].width = 0;
893 }
894
895 inst->src[arg].stride = 1;
896
897 /* Hopefully no Align16 around here... */
898 assert(entry->src.swizzle == BRW_SWIZZLE_XYZW);
899 inst->src[arg].swizzle = entry->src.swizzle;
900 } else {
901 inst->src[arg].stride *= entry->src.stride;
902 }
903
904 /* Compute the first component of the copy that the instruction is
905 * reading, and the base byte offset within that component.
906 */
907 assert(entry->dst.stride == 1);
908 const unsigned component = rel_offset / brw_type_size_bytes(entry->dst.type);
909 const unsigned suboffset = rel_offset % brw_type_size_bytes(entry->dst.type);
910
911 /* Calculate the byte offset at the origin of the copy of the given
912 * component and suboffset.
913 */
914 inst->src[arg] = byte_offset(inst->src[arg],
915 component * entry_stride * brw_type_size_bytes(entry->src.type) + suboffset);
916
917 if (has_source_modifiers) {
918 if (entry->dst.type != inst->src[arg].type) {
919 /* We are propagating source modifiers from a MOV with a different
920 * type. If we got here, then we can just change the source and
921 * destination types of the instruction and keep going.
922 */
923 for (int i = 0; i < inst->sources; i++) {
924 inst->src[i].type = entry->dst.type;
925 }
926 inst->dst.type = entry->dst.type;
927 }
928
929 if (!inst->src[arg].abs) {
930 inst->src[arg].abs = entry->src.abs;
931 inst->src[arg].negate ^= entry->src.negate;
932 }
933 }
934
935 return true;
936 }
937
938 static bool
try_constant_propagate_value(brw_reg val,brw_reg_type dst_type,fs_inst * inst,int arg)939 try_constant_propagate_value(brw_reg val, brw_reg_type dst_type,
940 fs_inst *inst, int arg)
941 {
942 bool progress = false;
943
944 if (brw_type_size_bytes(val.type) > 4)
945 return false;
946
947 /* If the size of the use type is smaller than the size of the entry,
948 * clamp the value to the range of the use type. This enables constant
949 * copy propagation in cases like
950 *
951 *
952 * mov(8) g12<1>UD 0x0000000cUD
953 * ...
954 * mul(8) g47<1>D g86<8,8,1>D g12<16,8,2>W
955 */
956 if (brw_type_size_bits(inst->src[arg].type) <
957 brw_type_size_bits(dst_type)) {
958 if (brw_type_size_bytes(inst->src[arg].type) != 2 ||
959 brw_type_size_bytes(dst_type) != 4)
960 return false;
961
962 assert(inst->src[arg].subnr == 0 || inst->src[arg].subnr == 2);
963
964 /* When subnr is 0, we want the lower 16-bits, and when it's 2, we
965 * want the upper 16-bits. No other values of subnr are valid for a
966 * UD source.
967 */
968 const uint16_t v = inst->src[arg].subnr == 2 ? val.ud >> 16 : val.ud;
969
970 val.ud = v | (uint32_t(v) << 16);
971 }
972
973 val.type = inst->src[arg].type;
974
975 if (inst->src[arg].abs) {
976 if (is_logic_op(inst->opcode) ||
977 !brw_reg_abs_immediate(&val)) {
978 return false;
979 }
980 }
981
982 if (inst->src[arg].negate) {
983 if (is_logic_op(inst->opcode) ||
984 !brw_reg_negate_immediate(&val)) {
985 return false;
986 }
987 }
988
989 switch (inst->opcode) {
990 case BRW_OPCODE_MOV:
991 case SHADER_OPCODE_LOAD_PAYLOAD:
992 case SHADER_OPCODE_POW:
993 case FS_OPCODE_PACK:
994 inst->src[arg] = val;
995 progress = true;
996 break;
997
998 case BRW_OPCODE_SUBB:
999 if (arg == 1) {
1000 inst->src[arg] = val;
1001 progress = true;
1002 }
1003 break;
1004
1005 case BRW_OPCODE_MACH:
1006 case BRW_OPCODE_MUL:
1007 case SHADER_OPCODE_MULH:
1008 case BRW_OPCODE_ADD:
1009 case BRW_OPCODE_XOR:
1010 case BRW_OPCODE_ADDC:
1011 if (arg == 1) {
1012 inst->src[arg] = val;
1013 progress = true;
1014 } else if (arg == 0 && inst->src[1].file != IMM) {
1015 /* We used to not copy propagate the constant in situations like
1016 *
1017 * mov(8) g8<1>D 0x7fffffffD
1018 * mul(8) g16<1>D g8<8,8,1>D g15<16,8,2>W
1019 *
1020 * On platforms that only have a 32x16 multiplier, this would
1021 * result in lowering the multiply to
1022 *
1023 * mul(8) g15<1>D g14<8,8,1>D 0xffffUW
1024 * mul(8) g16<1>D g14<8,8,1>D 0x7fffUW
1025 * add(8) g15.1<2>UW g15.1<16,8,2>UW g16<16,8,2>UW
1026 *
1027 * On Gfx8 and Gfx9, which have the full 32x32 multiplier, it
1028 * would results in
1029 *
1030 * mul(8) g16<1>D g15<16,8,2>W 0x7fffffffD
1031 *
1032 * Volume 2a of the Skylake PRM says:
1033 *
1034 * When multiplying a DW and any lower precision integer, the
1035 * DW operand must on src0.
1036 *
1037 * So it would have been invalid. However, brw_fs_combine_constants
1038 * will now "fix" the constant.
1039 */
1040 if (inst->opcode == BRW_OPCODE_MUL &&
1041 brw_type_size_bytes(inst->src[1].type) < 4 &&
1042 (inst->src[0].type == BRW_TYPE_D ||
1043 inst->src[0].type == BRW_TYPE_UD)) {
1044 inst->src[0] = val;
1045 inst->src[0].type = BRW_TYPE_D;
1046 progress = true;
1047 break;
1048 }
1049
1050 /* Fit this constant in by commuting the operands.
1051 * Exception: we can't do this for 32-bit integer MUL/MACH
1052 * because it's asymmetric.
1053 *
1054 * The BSpec says for Broadwell that
1055 *
1056 * "When multiplying DW x DW, the dst cannot be accumulator."
1057 *
1058 * Integer MUL with a non-accumulator destination will be lowered
1059 * by lower_integer_multiplication(), so don't restrict it.
1060 */
1061 if (((inst->opcode == BRW_OPCODE_MUL &&
1062 inst->dst.is_accumulator()) ||
1063 inst->opcode == BRW_OPCODE_MACH) &&
1064 (inst->src[1].type == BRW_TYPE_D ||
1065 inst->src[1].type == BRW_TYPE_UD))
1066 break;
1067 inst->src[0] = inst->src[1];
1068 inst->src[1] = val;
1069 progress = true;
1070 }
1071 break;
1072
1073 case BRW_OPCODE_ADD3:
1074 /* add3 can have a single imm16 source. Proceed if the source type is
1075 * already W or UW or the value can be coerced to one of those types.
1076 */
1077 if (val.type == BRW_TYPE_W || val.type == BRW_TYPE_UW)
1078 ; /* Nothing to do. */
1079 else if (val.ud <= 0xffff)
1080 val = brw_imm_uw(val.ud);
1081 else if (val.d >= -0x8000 && val.d <= 0x7fff)
1082 val = brw_imm_w(val.d);
1083 else
1084 break;
1085
1086 if (arg == 2) {
1087 inst->src[arg] = val;
1088 progress = true;
1089 } else if (inst->src[2].file != IMM) {
1090 inst->src[arg] = inst->src[2];
1091 inst->src[2] = val;
1092 progress = true;
1093 }
1094
1095 break;
1096
1097 case BRW_OPCODE_CMP:
1098 if (arg == 1) {
1099 inst->src[arg] = val;
1100 progress = true;
1101 } else if (arg == 0 && inst->src[1].file != IMM) {
1102 enum brw_conditional_mod new_cmod;
1103
1104 new_cmod = brw_swap_cmod(inst->conditional_mod);
1105 if (new_cmod != BRW_CONDITIONAL_NONE) {
1106 /* Fit this constant in by swapping the operands and
1107 * flipping the test
1108 */
1109 inst->src[0] = inst->src[1];
1110 inst->src[1] = val;
1111 inst->conditional_mod = new_cmod;
1112 progress = true;
1113 }
1114 }
1115 break;
1116
1117 case BRW_OPCODE_SEL:
1118 if (arg == 1) {
1119 inst->src[arg] = val;
1120 progress = true;
1121 } else if (arg == 0) {
1122 if (inst->src[1].file != IMM &&
1123 (inst->conditional_mod == BRW_CONDITIONAL_NONE ||
1124 /* Only GE and L are commutative. */
1125 inst->conditional_mod == BRW_CONDITIONAL_GE ||
1126 inst->conditional_mod == BRW_CONDITIONAL_L)) {
1127 inst->src[0] = inst->src[1];
1128 inst->src[1] = val;
1129
1130 /* If this was predicated, flipping operands means
1131 * we also need to flip the predicate.
1132 */
1133 if (inst->conditional_mod == BRW_CONDITIONAL_NONE) {
1134 inst->predicate_inverse =
1135 !inst->predicate_inverse;
1136 }
1137 } else {
1138 inst->src[0] = val;
1139 }
1140
1141 progress = true;
1142 }
1143 break;
1144
1145 case BRW_OPCODE_CSEL:
1146 assert(inst->conditional_mod != BRW_CONDITIONAL_NONE);
1147
1148 if (arg == 0 &&
1149 inst->src[1].file != IMM &&
1150 (!brw_type_is_float(inst->src[1].type) ||
1151 inst->conditional_mod == BRW_CONDITIONAL_NZ ||
1152 inst->conditional_mod == BRW_CONDITIONAL_Z)) {
1153 /* Only EQ and NE are commutative due to NaN issues. */
1154 inst->src[0] = inst->src[1];
1155 inst->src[1] = val;
1156 inst->conditional_mod = brw_negate_cmod(inst->conditional_mod);
1157 } else {
1158 /* While CSEL is a 3-source instruction, the last source should never
1159 * be a constant. We'll support that, but should it ever happen, we
1160 * should add support to the constant folding pass.
1161 */
1162 inst->src[arg] = val;
1163 }
1164
1165 progress = true;
1166 break;
1167
1168 case FS_OPCODE_FB_WRITE_LOGICAL:
1169 /* The stencil and omask sources of FS_OPCODE_FB_WRITE_LOGICAL are
1170 * bit-cast using a strided region so they cannot be immediates.
1171 */
1172 if (arg != FB_WRITE_LOGICAL_SRC_SRC_STENCIL &&
1173 arg != FB_WRITE_LOGICAL_SRC_OMASK) {
1174 inst->src[arg] = val;
1175 progress = true;
1176 }
1177 break;
1178
1179 case SHADER_OPCODE_INT_QUOTIENT:
1180 case SHADER_OPCODE_INT_REMAINDER:
1181 case BRW_OPCODE_AND:
1182 case BRW_OPCODE_ASR:
1183 case BRW_OPCODE_BFE:
1184 case BRW_OPCODE_BFI1:
1185 case BRW_OPCODE_BFI2:
1186 case BRW_OPCODE_ROL:
1187 case BRW_OPCODE_ROR:
1188 case BRW_OPCODE_SHL:
1189 case BRW_OPCODE_SHR:
1190 case BRW_OPCODE_OR:
1191 case SHADER_OPCODE_TEX_LOGICAL:
1192 case SHADER_OPCODE_TXD_LOGICAL:
1193 case SHADER_OPCODE_TXF_LOGICAL:
1194 case SHADER_OPCODE_TXL_LOGICAL:
1195 case SHADER_OPCODE_TXS_LOGICAL:
1196 case FS_OPCODE_TXB_LOGICAL:
1197 case SHADER_OPCODE_TXF_CMS_W_LOGICAL:
1198 case SHADER_OPCODE_TXF_CMS_W_GFX12_LOGICAL:
1199 case SHADER_OPCODE_TXF_MCS_LOGICAL:
1200 case SHADER_OPCODE_LOD_LOGICAL:
1201 case SHADER_OPCODE_TG4_BIAS_LOGICAL:
1202 case SHADER_OPCODE_TG4_EXPLICIT_LOD_LOGICAL:
1203 case SHADER_OPCODE_TG4_IMPLICIT_LOD_LOGICAL:
1204 case SHADER_OPCODE_TG4_LOGICAL:
1205 case SHADER_OPCODE_TG4_OFFSET_LOGICAL:
1206 case SHADER_OPCODE_TG4_OFFSET_LOD_LOGICAL:
1207 case SHADER_OPCODE_TG4_OFFSET_BIAS_LOGICAL:
1208 case SHADER_OPCODE_SAMPLEINFO_LOGICAL:
1209 case SHADER_OPCODE_IMAGE_SIZE_LOGICAL:
1210 case SHADER_OPCODE_MEMORY_LOAD_LOGICAL:
1211 case SHADER_OPCODE_MEMORY_STORE_LOGICAL:
1212 case SHADER_OPCODE_MEMORY_ATOMIC_LOGICAL:
1213 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
1214 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL:
1215 case SHADER_OPCODE_BROADCAST:
1216 case BRW_OPCODE_MAD:
1217 case BRW_OPCODE_LRP:
1218 case FS_OPCODE_PACK_HALF_2x16_SPLIT:
1219 case SHADER_OPCODE_SHUFFLE:
1220 inst->src[arg] = val;
1221 progress = true;
1222 break;
1223
1224 default:
1225 break;
1226 }
1227
1228 return progress;
1229 }
1230
1231
1232 static bool
try_constant_propagate(fs_inst * inst,acp_entry * entry,int arg)1233 try_constant_propagate(fs_inst *inst, acp_entry *entry, int arg)
1234 {
1235 if (inst->src[arg].file != VGRF)
1236 return false;
1237
1238 assert(entry->dst.file == VGRF);
1239 if (inst->src[arg].nr != entry->dst.nr)
1240 return false;
1241
1242 /* Bail if inst is reading a range that isn't contained in the range
1243 * that entry is writing.
1244 */
1245 if (!region_contained_in(inst->src[arg], inst->size_read(arg),
1246 entry->dst, entry->size_written))
1247 return false;
1248
1249 /* If the size of the use type is larger than the size of the entry
1250 * type, the entry doesn't contain all of the data that the user is
1251 * trying to use.
1252 */
1253 if (brw_type_size_bits(inst->src[arg].type) >
1254 brw_type_size_bits(entry->dst.type))
1255 return false;
1256
1257 return try_constant_propagate_value(entry->src, entry->dst.type, inst, arg);
1258 }
1259
1260 static bool
can_propagate_from(fs_inst * inst)1261 can_propagate_from(fs_inst *inst)
1262 {
1263 return (inst->opcode == BRW_OPCODE_MOV &&
1264 inst->dst.file == VGRF &&
1265 ((inst->src[0].file == VGRF &&
1266 !grf_regions_overlap(inst->dst, inst->size_written,
1267 inst->src[0], inst->size_read(0))) ||
1268 inst->src[0].file == ATTR ||
1269 inst->src[0].file == UNIFORM ||
1270 inst->src[0].file == IMM ||
1271 (inst->src[0].file == FIXED_GRF &&
1272 inst->src[0].is_contiguous())) &&
1273 /* is_raw_move also rejects source modifiers, but copy propagation
1274 * can handle that if the types are the same.
1275 */
1276 ((inst->src[0].type == inst->dst.type &&
1277 !inst->saturate) ||
1278 inst->is_raw_move()) &&
1279 /* Subset of !is_partial_write() conditions. */
1280 !inst->predicate && inst->dst.is_contiguous()) ||
1281 is_identity_payload(FIXED_GRF, inst);
1282 }
1283
1284 static void
commute_immediates(fs_inst * inst)1285 commute_immediates(fs_inst *inst)
1286 {
1287 /* ADD3 can only have the immediate as src0. */
1288 if (inst->opcode == BRW_OPCODE_ADD3) {
1289 if (inst->src[2].file == IMM) {
1290 const auto src0 = inst->src[0];
1291 inst->src[0] = inst->src[2];
1292 inst->src[2] = src0;
1293 }
1294 }
1295
1296 /* If only one of the sources of a 2-source, commutative instruction (e.g.,
1297 * AND) is immediate, it must be src1. If both are immediate, opt_algebraic
1298 * should fold it away.
1299 */
1300 if (inst->sources == 2 && inst->is_commutative() &&
1301 inst->src[0].file == IMM && inst->src[1].file != IMM) {
1302 const auto src1 = inst->src[1];
1303 inst->src[1] = inst->src[0];
1304 inst->src[0] = src1;
1305 }
1306 }
1307
1308 /* Walks a basic block and does copy propagation on it using the acp
1309 * list.
1310 */
1311 static bool
opt_copy_propagation_local(const brw_compiler * compiler,linear_ctx * lin_ctx,bblock_t * block,struct acp & acp,const brw::simple_allocator & alloc,uint8_t max_polygons)1312 opt_copy_propagation_local(const brw_compiler *compiler, linear_ctx *lin_ctx,
1313 bblock_t *block, struct acp &acp,
1314 const brw::simple_allocator &alloc,
1315 uint8_t max_polygons)
1316 {
1317 bool progress = false;
1318
1319 foreach_inst_in_block(fs_inst, inst, block) {
1320 /* Try propagating into this instruction. */
1321 bool instruction_progress = false;
1322 for (int i = inst->sources - 1; i >= 0; i--) {
1323 if (inst->src[i].file != VGRF)
1324 continue;
1325
1326 for (auto iter = acp.find_by_dst(inst->src[i].nr);
1327 iter != acp.end() && (*iter)->dst.nr == inst->src[i].nr;
1328 ++iter) {
1329 if ((*iter)->src.file == IMM) {
1330 if (try_constant_propagate(inst, *iter, i)) {
1331 instruction_progress = true;
1332 break;
1333 }
1334 } else {
1335 if (try_copy_propagate(compiler, inst, *iter, i, alloc,
1336 max_polygons)) {
1337 instruction_progress = true;
1338 break;
1339 }
1340 }
1341 }
1342 }
1343
1344 if (instruction_progress) {
1345 progress = true;
1346 commute_immediates(inst);
1347 }
1348
1349 /* kill the destination from the ACP */
1350 if (inst->dst.file == VGRF || inst->dst.file == FIXED_GRF) {
1351 for (auto iter = acp.find_by_dst(inst->dst.nr);
1352 iter != acp.end() && (*iter)->dst.nr == inst->dst.nr;
1353 ++iter) {
1354 if (grf_regions_overlap((*iter)->dst, (*iter)->size_written,
1355 inst->dst, inst->size_written))
1356 acp.remove(*iter);
1357 }
1358
1359 for (auto iter = acp.find_by_src(inst->dst.nr);
1360 iter != acp.end() && (*iter)->src.nr == inst->dst.nr;
1361 ++iter) {
1362 /* Make sure we kill the entry if this instruction overwrites
1363 * _any_ of the registers that it reads
1364 */
1365 if (grf_regions_overlap((*iter)->src, (*iter)->size_read,
1366 inst->dst, inst->size_written))
1367 acp.remove(*iter);
1368 }
1369 }
1370
1371 /* If this instruction's source could potentially be folded into the
1372 * operand of another instruction, add it to the ACP.
1373 */
1374 if (can_propagate_from(inst)) {
1375 acp_entry *entry = linear_zalloc(lin_ctx, acp_entry);
1376 entry->dst = inst->dst;
1377 entry->src = inst->src[0];
1378 entry->size_written = inst->size_written;
1379 for (unsigned i = 0; i < inst->sources; i++)
1380 entry->size_read += inst->size_read(i);
1381 entry->opcode = inst->opcode;
1382 entry->is_partial_write = inst->is_partial_write();
1383 entry->force_writemask_all = inst->force_writemask_all;
1384 acp.add(entry);
1385 } else if (inst->opcode == SHADER_OPCODE_LOAD_PAYLOAD &&
1386 inst->dst.file == VGRF) {
1387 int offset = 0;
1388 for (int i = 0; i < inst->sources; i++) {
1389 int effective_width = i < inst->header_size ? 8 : inst->exec_size;
1390 const unsigned size_written =
1391 effective_width * brw_type_size_bytes(inst->src[i].type);
1392 if (inst->src[i].file == VGRF ||
1393 (inst->src[i].file == FIXED_GRF &&
1394 inst->src[i].is_contiguous())) {
1395 const brw_reg_type t = i < inst->header_size ?
1396 BRW_TYPE_UD : inst->src[i].type;
1397 brw_reg dst = byte_offset(retype(inst->dst, t), offset);
1398 if (!dst.equals(inst->src[i])) {
1399 acp_entry *entry = linear_zalloc(lin_ctx, acp_entry);
1400 entry->dst = dst;
1401 entry->src = retype(inst->src[i], t);
1402 entry->size_written = size_written;
1403 entry->size_read = inst->size_read(i);
1404 entry->opcode = inst->opcode;
1405 entry->force_writemask_all = inst->force_writemask_all;
1406 acp.add(entry);
1407 }
1408 }
1409 offset += size_written;
1410 }
1411 }
1412 }
1413
1414 return progress;
1415 }
1416
1417 bool
brw_fs_opt_copy_propagation(fs_visitor & s)1418 brw_fs_opt_copy_propagation(fs_visitor &s)
1419 {
1420 bool progress = false;
1421 void *copy_prop_ctx = ralloc_context(NULL);
1422 linear_ctx *lin_ctx = linear_context(copy_prop_ctx);
1423 struct acp out_acp[s.cfg->num_blocks];
1424
1425 const fs_live_variables &live = s.live_analysis.require();
1426
1427 /* First, walk through each block doing local copy propagation and getting
1428 * the set of copies available at the end of the block.
1429 */
1430 foreach_block (block, s.cfg) {
1431 progress = opt_copy_propagation_local(s.compiler, lin_ctx, block,
1432 out_acp[block->num], s.alloc,
1433 s.max_polygons) || progress;
1434
1435 /* If the destination of an ACP entry exists only within this block,
1436 * then there's no need to keep it for dataflow analysis. We can delete
1437 * it from the out_acp table and avoid growing the bitsets any bigger
1438 * than we absolutely have to.
1439 *
1440 * Because nothing in opt_copy_propagation_local touches the block
1441 * start/end IPs and opt_copy_propagation_local is incapable of
1442 * extending the live range of an ACP destination beyond the block,
1443 * it's safe to use the liveness information in this way.
1444 */
1445 for (auto iter = out_acp[block->num].begin();
1446 iter != out_acp[block->num].end(); ++iter) {
1447 assert((*iter)->dst.file == VGRF);
1448 if (block->start_ip <= live.vgrf_start[(*iter)->dst.nr] &&
1449 live.vgrf_end[(*iter)->dst.nr] <= block->end_ip) {
1450 out_acp[block->num].remove(*iter);
1451 }
1452 }
1453 }
1454
1455 /* Do dataflow analysis for those available copies. */
1456 fs_copy_prop_dataflow dataflow(lin_ctx, s.cfg, live, out_acp);
1457
1458 /* Next, re-run local copy propagation, this time with the set of copies
1459 * provided by the dataflow analysis available at the start of a block.
1460 */
1461 foreach_block (block, s.cfg) {
1462 struct acp in_acp;
1463
1464 for (int i = 0; i < dataflow.num_acp; i++) {
1465 if (BITSET_TEST(dataflow.bd[block->num].livein, i) &&
1466 !BITSET_TEST(dataflow.bd[block->num].exec_mismatch, i)) {
1467 struct acp_entry *entry = dataflow.acp[i];
1468 in_acp.add(entry);
1469 }
1470 }
1471
1472 progress = opt_copy_propagation_local(s.compiler, lin_ctx, block,
1473 in_acp, s.alloc, s.max_polygons) ||
1474 progress;
1475 }
1476
1477 ralloc_free(copy_prop_ctx);
1478
1479 if (progress)
1480 s.invalidate_analysis(DEPENDENCY_INSTRUCTION_DATA_FLOW |
1481 DEPENDENCY_INSTRUCTION_DETAIL);
1482
1483 return progress;
1484 }
1485
1486 static bool
try_copy_propagate_def(const brw_compiler * compiler,const brw::simple_allocator & alloc,fs_inst * def,const brw_reg & val,fs_inst * inst,int arg,uint8_t max_polygons)1487 try_copy_propagate_def(const brw_compiler *compiler,
1488 const brw::simple_allocator &alloc,
1489 fs_inst *def, const brw_reg &val,
1490 fs_inst *inst, int arg,
1491 uint8_t max_polygons)
1492 {
1493 const struct intel_device_info *devinfo = compiler->devinfo;
1494
1495 assert(val.file != BAD_FILE);
1496
1497 /* We can't generally copy-propagate UD negations because we can end up
1498 * accessing the resulting values as signed integers instead.
1499 */
1500 if (val.negate && val.type == BRW_TYPE_UD)
1501 return false;
1502
1503 /* Bail if the instruction type is larger than the execution type of the
1504 * copy, what implies that each channel is reading multiple channels of the
1505 * destination of the copy, and simply replacing the sources would give a
1506 * program with different semantics.
1507 */
1508 if (inst->opcode != BRW_OPCODE_MOV &&
1509 brw_type_size_bits(def->dst.type) <
1510 brw_type_size_bits(inst->src[arg].type))
1511 return false;
1512
1513 const bool has_source_modifiers = val.abs || val.negate;
1514
1515 if (has_source_modifiers) {
1516 if (is_logic_op(inst->opcode) || !inst->can_do_source_mods(devinfo))
1517 return false;
1518
1519 /* Since semantics of source modifiers are type-dependent we need to
1520 * ensure that the meaning of the instruction remains the same if we
1521 * change the type. If the sizes of the types are different the new
1522 * instruction will read a different amount of data than the original
1523 * and the semantics will always be different.
1524 */
1525 if (def->dst.type != inst->src[arg].type &&
1526 (!inst->can_change_types() ||
1527 brw_type_size_bits(def->dst.type) !=
1528 brw_type_size_bits(inst->src[arg].type)))
1529 return false;
1530 }
1531
1532 /* Send messages with EOT set are restricted to use g112-g127 (and we
1533 * sometimes need g127 for other purposes), so avoid copy propagating
1534 * anything that would make it impossible to satisfy that restriction.
1535 */
1536 if (inst->eot) {
1537 /* Don't propagate things that are already pinned. */
1538 if (val.file != VGRF)
1539 return false;
1540
1541 /* We might be propagating from a large register, while the SEND only
1542 * is reading a portion of it (say the .A channel in an RGBA value).
1543 * We need to pin both split SEND sources in g112-g126/127, so only
1544 * allow this if the registers aren't too large.
1545 */
1546 if (inst->opcode == SHADER_OPCODE_SEND && inst->sources >= 4 &&
1547 val.file == VGRF) {
1548 int other_src = arg == 2 ? 3 : 2;
1549 unsigned other_size = inst->src[other_src].file == VGRF ?
1550 alloc.sizes[inst->src[other_src].nr] :
1551 inst->size_read(other_src);
1552 unsigned prop_src_size = alloc.sizes[val.nr];
1553 if (other_size + prop_src_size > 15)
1554 return false;
1555 }
1556 }
1557
1558 /* Reject cases that would violate register regioning restrictions. */
1559 if ((val.file == UNIFORM || !val.is_contiguous()) &&
1560 (inst->is_send_from_grf() || inst->uses_indirect_addressing())) {
1561 return false;
1562 }
1563
1564 /* Some instructions implemented in the generator backend, such as
1565 * derivatives, assume that their operands are packed so we can't
1566 * generally propagate strided regions to them.
1567 */
1568 const unsigned entry_stride = val.file == FIXED_GRF ? 1 : val.stride;
1569 if (instruction_requires_packed_data(inst) && entry_stride != 1)
1570 return false;
1571
1572 const brw_reg_type dst_type = (has_source_modifiers &&
1573 def->dst.type != inst->src[arg].type) ?
1574 def->dst.type : inst->dst.type;
1575
1576 /* Bail if the result of composing both strides would exceed the
1577 * hardware limit.
1578 */
1579 if (!can_take_stride(inst, dst_type, arg,
1580 entry_stride * inst->src[arg].stride,
1581 compiler))
1582 return false;
1583
1584 /* Bail if the source FIXED_GRF region of the copy cannot be trivially
1585 * composed with the source region of the instruction -- E.g. because the
1586 * copy uses some extended stride greater than 4 not supported natively by
1587 * the hardware as a horizontal stride, or because instruction compression
1588 * could require us to use a vertical stride shorter than a GRF.
1589 */
1590 if (val.file == FIXED_GRF &&
1591 (inst->src[arg].stride > 4 ||
1592 inst->dst.component_size(inst->exec_size) >
1593 inst->src[arg].component_size(inst->exec_size)))
1594 return false;
1595
1596 /* Bail if the result of composing both strides cannot be expressed
1597 * as another stride. This avoids, for example, trying to transform
1598 * this:
1599 *
1600 * MOV (8) rX<1>UD rY<0;1,0>UD
1601 * FOO (8) ... rX<8;8,1>UW
1602 *
1603 * into this:
1604 *
1605 * FOO (8) ... rY<0;1,0>UW
1606 *
1607 * Which would have different semantics.
1608 */
1609 if (entry_stride != 1 &&
1610 (inst->src[arg].stride *
1611 brw_type_size_bytes(inst->src[arg].type)) % brw_type_size_bytes(val.type) != 0)
1612 return false;
1613
1614 /* From the Cherry Trail/Braswell PRMs, Volume 7: 3D Media GPGPU:
1615 * EU Overview
1616 * Register Region Restrictions
1617 * Special Requirements for Handling Double Precision Data Types :
1618 *
1619 * "When source or destination datatype is 64b or operation is integer
1620 * DWord multiply, regioning in Align1 must follow these rules:
1621 *
1622 * 1. Source and Destination horizontal stride must be aligned to the
1623 * same qword.
1624 * 2. Regioning must ensure Src.Vstride = Src.Width * Src.Hstride.
1625 * 3. Source and Destination offset must be the same, except the case
1626 * of scalar source."
1627 *
1628 * Most of this is already checked in can_take_stride(), we're only left
1629 * with checking 3.
1630 */
1631 if (has_dst_aligned_region_restriction(devinfo, inst, dst_type) &&
1632 entry_stride != 0 &&
1633 (reg_offset(inst->dst) % (REG_SIZE * reg_unit(devinfo))) != (reg_offset(val) % (REG_SIZE * reg_unit(devinfo))))
1634 return false;
1635
1636 /* The <8;8,0> regions used for FS attributes in multipolygon
1637 * dispatch mode could violate regioning restrictions, don't copy
1638 * propagate them in such cases.
1639 */
1640 if (max_polygons > 1 && val.file == ATTR &&
1641 (has_dst_aligned_region_restriction(devinfo, inst, dst_type) ||
1642 instruction_requires_packed_data(inst) ||
1643 (inst->is_3src(compiler) && arg == 2) ||
1644 def->dst.type != inst->src[arg].type))
1645 return false;
1646
1647 /* Fold the copy into the instruction consuming it. */
1648 inst->src[arg].file = val.file;
1649 inst->src[arg].nr = val.nr;
1650 inst->src[arg].subnr = val.subnr;
1651 inst->src[arg].offset = val.offset;
1652
1653 /* Compose the strides of both regions. */
1654 if (val.file == FIXED_GRF) {
1655 if (inst->src[arg].stride) {
1656 const unsigned orig_width = 1 << val.width;
1657 const unsigned reg_width =
1658 REG_SIZE / (brw_type_size_bytes(inst->src[arg].type) *
1659 inst->src[arg].stride);
1660 inst->src[arg].width = cvt(MIN2(orig_width, reg_width)) - 1;
1661 inst->src[arg].hstride = cvt(inst->src[arg].stride);
1662 inst->src[arg].vstride = inst->src[arg].hstride + inst->src[arg].width;
1663 } else {
1664 inst->src[arg].vstride = inst->src[arg].hstride =
1665 inst->src[arg].width = 0;
1666 }
1667
1668 inst->src[arg].stride = 1;
1669
1670 /* Hopefully no Align16 around here... */
1671 assert(val.swizzle == BRW_SWIZZLE_XYZW);
1672 inst->src[arg].swizzle = val.swizzle;
1673 } else {
1674 inst->src[arg].stride *= val.stride;
1675 }
1676
1677 /* Handle NoMask cases where the def replicates a small scalar to a number
1678 * of channels, but the use is a lower SIMD width but larger type, so each
1679 * invocation reads multiple channels worth of data, e.g.
1680 *
1681 * mov(16) vgrf1:UW, u0<0>:UW NoMask
1682 * mov(8) vgrf2:UD, vgrf1:UD NoMask group0
1683 *
1684 * In this case, we should just use the scalar's type.
1685 */
1686 if (val.stride == 0 &&
1687 inst->opcode == BRW_OPCODE_MOV &&
1688 inst->force_writemask_all && def->force_writemask_all &&
1689 inst->exec_size < def->exec_size &&
1690 (inst->exec_size * brw_type_size_bytes(inst->src[arg].type) ==
1691 def->exec_size * brw_type_size_bytes(val.type))) {
1692 inst->src[arg].type = val.type;
1693 inst->dst.type = val.type;
1694 inst->exec_size = def->exec_size;
1695 }
1696
1697 if (has_source_modifiers) {
1698 if (def->dst.type != inst->src[arg].type) {
1699 /* We are propagating source modifiers from a MOV with a different
1700 * type. If we got here, then we can just change the source and
1701 * destination types of the instruction and keep going.
1702 */
1703 for (int i = 0; i < inst->sources; i++) {
1704 inst->src[i].type = def->dst.type;
1705 }
1706 inst->dst.type = def->dst.type;
1707 }
1708
1709 if (!inst->src[arg].abs) {
1710 inst->src[arg].abs = val.abs;
1711 inst->src[arg].negate ^= val.negate;
1712 }
1713 }
1714
1715 return true;
1716 }
1717
1718 static bool
try_constant_propagate_def(fs_inst * def,brw_reg val,fs_inst * inst,int arg)1719 try_constant_propagate_def(fs_inst *def, brw_reg val, fs_inst *inst, int arg)
1720 {
1721 /* Bail if inst is reading more than a single vector component of entry */
1722 if (inst->size_read(arg) > def->dst.component_size(inst->exec_size))
1723 return false;
1724
1725 return try_constant_propagate_value(val, def->dst.type, inst, arg);
1726 }
1727
1728 /**
1729 * Handle cases like UW subreads of a UD immediate, with an offset.
1730 */
1731 static brw_reg
extract_imm(brw_reg val,brw_reg_type type,unsigned offset)1732 extract_imm(brw_reg val, brw_reg_type type, unsigned offset)
1733 {
1734 assert(val.file == IMM);
1735
1736 const unsigned bitsize = brw_type_size_bits(type);
1737
1738 if (offset == 0 || bitsize == brw_type_size_bits(val.type))
1739 return val;
1740
1741 assert(bitsize < brw_type_size_bits(val.type));
1742
1743 val.u64 = (val.u64 >> (bitsize * offset)) & ((1ull << bitsize) - 1);
1744
1745 return val;
1746 }
1747
1748 static brw_reg
find_value_for_offset(fs_inst * def,const brw_reg & src,unsigned src_size)1749 find_value_for_offset(fs_inst *def, const brw_reg &src, unsigned src_size)
1750 {
1751 brw_reg val;
1752
1753 switch (def->opcode) {
1754 case BRW_OPCODE_MOV:
1755 /* is_raw_move also rejects source modifiers, but copy propagation
1756 * can handle that if the tyeps are the same.
1757 */
1758 if ((def->dst.type == def->src[0].type || def->is_raw_move()) &&
1759 def->src[0].stride <= 1) {
1760 val = def->src[0];
1761
1762 unsigned rel_offset = src.offset - def->dst.offset;
1763
1764 if (val.stride == 0)
1765 rel_offset %= brw_type_size_bytes(def->dst.type);
1766
1767 if (val.file == IMM)
1768 val = extract_imm(val, src.type, rel_offset);
1769 else
1770 val = byte_offset(def->src[0], rel_offset);
1771 }
1772 break;
1773 case SHADER_OPCODE_LOAD_PAYLOAD: {
1774 unsigned offset = 0;
1775 for (int i = def->header_size; i < def->sources; i++) {
1776 const unsigned splat = def->src[i].stride == 0 ? def->exec_size : 1;
1777 if (offset == src.offset) {
1778 if (def->dst.type == def->src[i].type &&
1779 def->src[i].stride <= 1 &&
1780 def->src[i].component_size(def->exec_size) * splat == src_size)
1781 val = def->src[i];
1782
1783 break;
1784 }
1785
1786 offset += def->exec_size * brw_type_size_bytes(def->src[i].type);
1787 }
1788 break;
1789 }
1790 default:
1791 break;
1792 }
1793
1794 return val;
1795 }
1796
1797 bool
brw_fs_opt_copy_propagation_defs(fs_visitor & s)1798 brw_fs_opt_copy_propagation_defs(fs_visitor &s)
1799 {
1800 const brw::def_analysis &defs = s.def_analysis.require();
1801 unsigned *uses_deleted = new unsigned[defs.count()]();
1802 bool progress = false;
1803
1804 foreach_block_and_inst_safe(block, fs_inst, inst, s.cfg) {
1805 /* Try propagating into this instruction. */
1806 bool instruction_progress = false;
1807
1808 for (int i = inst->sources - 1; i >= 0; i--) {
1809 fs_inst *def = defs.get(inst->src[i]);
1810
1811 if (!def || def->saturate)
1812 continue;
1813
1814 bool source_progress = false;
1815
1816 if (def->opcode == SHADER_OPCODE_LOAD_PAYLOAD) {
1817 if (inst->size_read(i) == def->size_written &&
1818 def->src[0].file != BAD_FILE && def->src[0].file != IMM &&
1819 is_identity_payload(def->src[0].file, def)) {
1820 source_progress =
1821 try_copy_propagate_def(s.compiler, s.alloc, def, def->src[0],
1822 inst, i, s.max_polygons);
1823
1824 if (source_progress) {
1825 instruction_progress = true;
1826 ++uses_deleted[def->dst.nr];
1827 if (defs.get_use_count(def->dst) == uses_deleted[def->dst.nr])
1828 def->remove(defs.get_block(def->dst), true);
1829 }
1830
1831 continue;
1832 }
1833 }
1834
1835 brw_reg val =
1836 find_value_for_offset(def, inst->src[i], inst->size_read(i));
1837
1838 if (val.file == IMM) {
1839 source_progress =
1840 try_constant_propagate_def(def, val, inst, i);
1841 } else if (val.file == VGRF ||
1842 val.file == ATTR || val.file == UNIFORM ||
1843 (val.file == FIXED_GRF && val.is_contiguous())) {
1844 source_progress =
1845 try_copy_propagate_def(s.compiler, s.alloc, def, val, inst, i,
1846 s.max_polygons);
1847 }
1848
1849 if (source_progress) {
1850 instruction_progress = true;
1851 ++uses_deleted[def->dst.nr];
1852 if (defs.get_use_count(def->dst) == uses_deleted[def->dst.nr])
1853 def->remove(defs.get_block(def->dst), true);
1854 }
1855 }
1856
1857 if (instruction_progress) {
1858 progress = true;
1859 commute_immediates(inst);
1860 }
1861 }
1862
1863 if (progress) {
1864 s.cfg->adjust_block_ips();
1865 s.invalidate_analysis(DEPENDENCY_INSTRUCTION_DATA_FLOW |
1866 DEPENDENCY_INSTRUCTION_DETAIL);
1867 }
1868
1869 delete [] uses_deleted;
1870
1871 return progress;
1872 }
1873