1 /*
2 * Copyright © 2015-2016 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "brw_compiler.h"
25 #include "brw_eu.h"
26 #include "brw_nir.h"
27 #include "brw_private.h"
28 #include "dev/intel_debug.h"
29 #include "compiler/nir/nir.h"
30 #include "util/u_debug.h"
31
32 const struct nir_shader_compiler_options brw_scalar_nir_options = {
33 .avoid_ternary_with_two_constants = true,
34 .compact_arrays = true,
35 .discard_is_demote = true,
36 .divergence_analysis_options =
37 (nir_divergence_single_patch_per_tcs_subgroup |
38 nir_divergence_single_patch_per_tes_subgroup |
39 nir_divergence_shader_record_ptr_uniform),
40 .force_indirect_unrolling = nir_var_function_temp,
41 .has_bfe = true,
42 .has_bfi = true,
43 .has_bfm = true,
44 .has_pack_32_4x8 = true,
45 .has_uclz = true,
46 .lower_base_vertex = true,
47 .lower_bitfield_extract = true,
48 .lower_bitfield_insert = true,
49 .lower_device_index_to_zero = true,
50 .lower_fdiv = true,
51 .lower_fisnormal = true,
52 .lower_flrp16 = true,
53 .lower_flrp64 = true,
54 .lower_fmod = true,
55 .lower_hadd64 = true,
56 .lower_insert_byte = true,
57 .lower_insert_word = true,
58 .lower_isign = true,
59 .lower_ldexp = true,
60 .lower_pack_half_2x16 = true,
61 .lower_pack_snorm_2x16 = true,
62 .lower_pack_snorm_4x8 = true,
63 .lower_pack_unorm_2x16 = true,
64 .lower_pack_unorm_4x8 = true,
65 .lower_scmp = true,
66 .lower_to_scalar = true,
67 .lower_uadd_carry = true,
68 .lower_ufind_msb = true,
69 .lower_uniforms_to_ubo = true,
70 .lower_unpack_half_2x16 = true,
71 .lower_unpack_snorm_2x16 = true,
72 .lower_unpack_snorm_4x8 = true,
73 .lower_unpack_unorm_2x16 = true,
74 .lower_unpack_unorm_4x8 = true,
75 .lower_usub_borrow = true,
76 .max_unroll_iterations = 32,
77 .support_16bit_alu = true,
78 .use_interpolated_input_intrinsics = true,
79 .vectorize_io = true,
80 .vectorize_tess_levels = true,
81 .vertex_id_zero_based = true,
82 .has_ddx_intrinsics = true,
83 .scalarize_ddx = true,
84 };
85
86 struct brw_compiler *
brw_compiler_create(void * mem_ctx,const struct intel_device_info * devinfo)87 brw_compiler_create(void *mem_ctx, const struct intel_device_info *devinfo)
88 {
89 struct brw_compiler *compiler = rzalloc(mem_ctx, struct brw_compiler);
90 assert(devinfo->ver >= 9);
91
92 compiler->devinfo = devinfo;
93
94 brw_init_isa_info(&compiler->isa, devinfo);
95
96 brw_fs_alloc_reg_sets(compiler);
97
98 compiler->precise_trig = debug_get_bool_option("INTEL_PRECISE_TRIG", false);
99
100 compiler->use_tcs_multi_patch = devinfo->ver >= 12;
101
102 compiler->indirect_ubos_use_sampler = devinfo->ver < 12;
103
104 compiler->lower_dpas = devinfo->verx10 < 125 ||
105 intel_device_info_is_mtl(devinfo) ||
106 (intel_device_info_is_arl(devinfo) &&
107 devinfo->platform != INTEL_PLATFORM_ARL_H) ||
108 debug_get_bool_option("INTEL_LOWER_DPAS", false);
109
110 nir_lower_int64_options int64_options =
111 nir_lower_imul64 |
112 nir_lower_isign64 |
113 nir_lower_divmod64 |
114 nir_lower_imul_high64 |
115 nir_lower_find_lsb64 |
116 nir_lower_ufind_msb64 |
117 nir_lower_bit_count64 |
118 nir_lower_iadd3_64;
119 nir_lower_doubles_options fp64_options =
120 nir_lower_drcp |
121 nir_lower_dsqrt |
122 nir_lower_drsq |
123 nir_lower_dsign |
124 nir_lower_dtrunc |
125 nir_lower_dfloor |
126 nir_lower_dceil |
127 nir_lower_dfract |
128 nir_lower_dround_even |
129 nir_lower_dmod |
130 nir_lower_dsub |
131 nir_lower_ddiv;
132
133 if (!devinfo->has_64bit_float || INTEL_DEBUG(DEBUG_SOFT64))
134 fp64_options |= nir_lower_fp64_full_software;
135 if (!devinfo->has_64bit_int)
136 int64_options |= (nir_lower_int64_options)~0;
137
138 /* The Bspec's section titled "Instruction_multiply[DevBDW+]" claims that
139 * destination type can be Quadword and source type Doubleword for Gfx8 and
140 * Gfx9. So, lower 64 bit multiply instruction on rest of the platforms.
141 */
142 if (devinfo->ver > 9)
143 int64_options |= nir_lower_imul_2x32_64;
144
145 if (devinfo->ver >= 20)
146 int64_options |= (nir_lower_icmp64 | nir_lower_minmax64 |
147 nir_lower_logic64 | nir_lower_ufind_msb64 |
148 nir_lower_bit_count64 |
149 nir_lower_bcsel64 |
150 nir_lower_extract64 | nir_lower_scan_reduce_bitwise64 |
151 nir_lower_scan_reduce_iadd64 | nir_lower_subgroup_shuffle64 |
152 nir_lower_iadd_sat64 | nir_lower_uadd_sat64);
153
154 /* We want the GLSL compiler to emit code that uses condition codes */
155 for (int i = 0; i < MESA_ALL_SHADER_STAGES; i++) {
156 struct nir_shader_compiler_options *nir_options =
157 rzalloc(compiler, struct nir_shader_compiler_options);
158 *nir_options = brw_scalar_nir_options;
159 int64_options |= nir_lower_usub_sat64;
160
161 /* Gfx11 loses LRP. */
162 nir_options->lower_flrp32 = devinfo->ver >= 11;
163
164 nir_options->lower_fpow = devinfo->ver >= 12;
165
166 nir_options->has_rotate16 = devinfo->ver >= 11;
167 nir_options->has_rotate32 = devinfo->ver >= 11;
168 nir_options->has_iadd3 = devinfo->verx10 >= 125;
169
170 nir_options->has_sdot_4x8 = devinfo->ver >= 12;
171 nir_options->has_udot_4x8 = devinfo->ver >= 12;
172 nir_options->has_sudot_4x8 = devinfo->ver >= 12;
173 nir_options->has_sdot_4x8_sat = devinfo->ver >= 12;
174 nir_options->has_udot_4x8_sat = devinfo->ver >= 12;
175 nir_options->has_sudot_4x8_sat = devinfo->ver >= 12;
176
177 nir_options->lower_int64_options = int64_options;
178 nir_options->lower_doubles_options = fp64_options;
179
180 nir_options->unify_interfaces = i < MESA_SHADER_FRAGMENT;
181
182 nir_options->force_indirect_unrolling |=
183 brw_nir_no_indirect_mask(compiler, i);
184
185 if (compiler->use_tcs_multi_patch) {
186 /* TCS MULTI_PATCH mode has multiple patches per subgroup */
187 nir_options->divergence_analysis_options &=
188 ~nir_divergence_single_patch_per_tcs_subgroup;
189 }
190
191 if (devinfo->ver < 12)
192 nir_options->divergence_analysis_options |=
193 nir_divergence_single_prim_per_subgroup;
194
195 compiler->nir_options[i] = nir_options;
196 }
197
198 compiler->mesh.mue_header_packing =
199 (unsigned)debug_get_num_option("INTEL_MESH_HEADER_PACKING", 3);
200 compiler->mesh.mue_compaction =
201 debug_get_bool_option("INTEL_MESH_COMPACTION", true);
202
203 return compiler;
204 }
205
206 static void
insert_u64_bit(uint64_t * val,bool add)207 insert_u64_bit(uint64_t *val, bool add)
208 {
209 *val = (*val << 1) | !!add;
210 }
211
212 uint64_t
brw_get_compiler_config_value(const struct brw_compiler * compiler)213 brw_get_compiler_config_value(const struct brw_compiler *compiler)
214 {
215 uint64_t config = 0;
216 unsigned bits = 0;
217
218 insert_u64_bit(&config, compiler->precise_trig);
219 bits++;
220 insert_u64_bit(&config, compiler->lower_dpas);
221 bits++;
222 insert_u64_bit(&config, compiler->mesh.mue_compaction);
223 bits++;
224
225 uint64_t mask = DEBUG_DISK_CACHE_MASK;
226 bits += util_bitcount64(mask);
227
228 u_foreach_bit64(bit, mask)
229 insert_u64_bit(&config, INTEL_DEBUG(1ULL << bit));
230
231 mask = SIMD_DISK_CACHE_MASK;
232 bits += util_bitcount64(mask);
233
234 u_foreach_bit64(bit, mask)
235 insert_u64_bit(&config, (intel_simd & (1ULL << bit)) != 0);
236
237 mask = 3;
238 bits += util_bitcount64(mask);
239
240 u_foreach_bit64(bit, mask)
241 insert_u64_bit(&config, (compiler->mesh.mue_header_packing & (1ULL << bit)) != 0);
242
243 assert(bits <= util_bitcount64(UINT64_MAX));
244
245 return config;
246 }
247
248 void
brw_device_sha1(char * hex,const struct intel_device_info * devinfo)249 brw_device_sha1(char *hex,
250 const struct intel_device_info *devinfo) {
251 struct mesa_sha1 ctx;
252 _mesa_sha1_init(&ctx);
253 brw_device_sha1_update(&ctx, devinfo);
254 unsigned char result[20];
255 _mesa_sha1_final(&ctx, result);
256 _mesa_sha1_format(hex, result);
257 }
258
259 unsigned
brw_prog_data_size(gl_shader_stage stage)260 brw_prog_data_size(gl_shader_stage stage)
261 {
262 static const size_t stage_sizes[] = {
263 [MESA_SHADER_VERTEX] = sizeof(struct brw_vs_prog_data),
264 [MESA_SHADER_TESS_CTRL] = sizeof(struct brw_tcs_prog_data),
265 [MESA_SHADER_TESS_EVAL] = sizeof(struct brw_tes_prog_data),
266 [MESA_SHADER_GEOMETRY] = sizeof(struct brw_gs_prog_data),
267 [MESA_SHADER_FRAGMENT] = sizeof(struct brw_wm_prog_data),
268 [MESA_SHADER_COMPUTE] = sizeof(struct brw_cs_prog_data),
269 [MESA_SHADER_TASK] = sizeof(struct brw_task_prog_data),
270 [MESA_SHADER_MESH] = sizeof(struct brw_mesh_prog_data),
271 [MESA_SHADER_RAYGEN] = sizeof(struct brw_bs_prog_data),
272 [MESA_SHADER_ANY_HIT] = sizeof(struct brw_bs_prog_data),
273 [MESA_SHADER_CLOSEST_HIT] = sizeof(struct brw_bs_prog_data),
274 [MESA_SHADER_MISS] = sizeof(struct brw_bs_prog_data),
275 [MESA_SHADER_INTERSECTION] = sizeof(struct brw_bs_prog_data),
276 [MESA_SHADER_CALLABLE] = sizeof(struct brw_bs_prog_data),
277 [MESA_SHADER_KERNEL] = sizeof(struct brw_cs_prog_data),
278 };
279 assert((int)stage >= 0 && stage < ARRAY_SIZE(stage_sizes));
280 return stage_sizes[stage];
281 }
282
283 unsigned
brw_prog_key_size(gl_shader_stage stage)284 brw_prog_key_size(gl_shader_stage stage)
285 {
286 static const size_t stage_sizes[] = {
287 [MESA_SHADER_VERTEX] = sizeof(struct brw_vs_prog_key),
288 [MESA_SHADER_TESS_CTRL] = sizeof(struct brw_tcs_prog_key),
289 [MESA_SHADER_TESS_EVAL] = sizeof(struct brw_tes_prog_key),
290 [MESA_SHADER_GEOMETRY] = sizeof(struct brw_gs_prog_key),
291 [MESA_SHADER_FRAGMENT] = sizeof(struct brw_wm_prog_key),
292 [MESA_SHADER_COMPUTE] = sizeof(struct brw_cs_prog_key),
293 [MESA_SHADER_TASK] = sizeof(struct brw_task_prog_key),
294 [MESA_SHADER_MESH] = sizeof(struct brw_mesh_prog_key),
295 [MESA_SHADER_RAYGEN] = sizeof(struct brw_bs_prog_key),
296 [MESA_SHADER_ANY_HIT] = sizeof(struct brw_bs_prog_key),
297 [MESA_SHADER_CLOSEST_HIT] = sizeof(struct brw_bs_prog_key),
298 [MESA_SHADER_MISS] = sizeof(struct brw_bs_prog_key),
299 [MESA_SHADER_INTERSECTION] = sizeof(struct brw_bs_prog_key),
300 [MESA_SHADER_CALLABLE] = sizeof(struct brw_bs_prog_key),
301 [MESA_SHADER_KERNEL] = sizeof(struct brw_cs_prog_key),
302 };
303 assert((int)stage >= 0 && stage < ARRAY_SIZE(stage_sizes));
304 return stage_sizes[stage];
305 }
306
307 void
brw_write_shader_relocs(const struct brw_isa_info * isa,void * program,const struct brw_stage_prog_data * prog_data,struct brw_shader_reloc_value * values,unsigned num_values)308 brw_write_shader_relocs(const struct brw_isa_info *isa,
309 void *program,
310 const struct brw_stage_prog_data *prog_data,
311 struct brw_shader_reloc_value *values,
312 unsigned num_values)
313 {
314 for (unsigned i = 0; i < prog_data->num_relocs; i++) {
315 assert(prog_data->relocs[i].offset % 8 == 0);
316 void *dst = program + prog_data->relocs[i].offset;
317 for (unsigned j = 0; j < num_values; j++) {
318 if (prog_data->relocs[i].id == values[j].id) {
319 uint32_t value = values[j].value + prog_data->relocs[i].delta;
320 switch (prog_data->relocs[i].type) {
321 case BRW_SHADER_RELOC_TYPE_U32:
322 *(uint32_t *)dst = value;
323 break;
324 case BRW_SHADER_RELOC_TYPE_MOV_IMM:
325 brw_update_reloc_imm(isa, dst, value);
326 break;
327 default:
328 unreachable("Invalid relocation type");
329 }
330 break;
331 }
332 }
333 }
334 }
335
336 void
brw_stage_prog_data_add_printf(struct brw_stage_prog_data * prog_data,void * mem_ctx,const u_printf_info * print)337 brw_stage_prog_data_add_printf(struct brw_stage_prog_data *prog_data,
338 void *mem_ctx,
339 const u_printf_info *print)
340 {
341 prog_data->printf_info_count++;
342 prog_data->printf_info = reralloc(mem_ctx, prog_data->printf_info,
343 u_printf_info,
344 prog_data->printf_info_count);
345
346 prog_data->printf_info[prog_data->printf_info_count - 1] = *print;
347 if (print->string_size > 0) {
348 prog_data->printf_info[prog_data->printf_info_count - 1].strings =
349 ralloc_size(mem_ctx, print->string_size);
350 memcpy(prog_data->printf_info[prog_data->printf_info_count - 1].strings,
351 print->strings, print->string_size);
352 }
353 if (print->num_args > 0) {
354 prog_data->printf_info[prog_data->printf_info_count - 1].arg_sizes =
355 ralloc_array(mem_ctx, __typeof__(*print->arg_sizes), print->num_args);
356 memcpy(prog_data->printf_info[prog_data->printf_info_count - 1].arg_sizes,
357 print->arg_sizes, sizeof(print->arg_sizes[0]) *print->num_args);
358 }
359 }
360