xref: /aosp_15_r20/external/mesa3d/src/intel/common/intel_genX_state_elk.h (revision 6104692788411f58d303aa86923a9ff6ecaded22)
1 /*
2  * Copyright (c) 2022 Intel Corporation
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice (including the next
12  * paragraph) shall be included in all copies or substantial portions of the
13  * Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21  * IN THE SOFTWARE.
22  */
23 
24 #ifndef INTEL_GENX_STATE_ELK_H
25 #define INTEL_GENX_STATE_ELK_H
26 
27 #ifndef GFX_VERx10
28 #error This file should only be included by genX files.
29 #endif
30 
31 #if GFX_VER > 8
32 #error "ELK doesn't support Gfx > 8."
33 #endif
34 
35 #include <stdbool.h>
36 
37 #include "dev/intel_device_info.h"
38 #include "genxml/gen_macros.h"
39 
40 #ifdef __cplusplus
41 extern "C" {
42 #endif
43 
44 #if GFX_VER >= 7
45 
46 static inline void
47 intel_set_ps_dispatch_state(struct GENX(3DSTATE_PS) *ps,
48                             const struct intel_device_info *devinfo,
49                             const struct elk_wm_prog_data *prog_data,
50                             unsigned rasterization_samples,
51                             enum intel_msaa_flags msaa_flags)
52 {
53    assert(rasterization_samples != 0);
54 
55    bool enable_8  = prog_data->dispatch_8;
56    bool enable_16 = prog_data->dispatch_16;
57    bool enable_32 = prog_data->dispatch_32;
58 
59    /* SKL PRMs, Volume 2a: Command Reference: Instructions:
60     *    3DSTATE_PS_BODY::8 Pixel Dispatch Enable:
61     *
62     *    "When Render Target Fast Clear Enable is ENABLED or Render Target
63     *     Resolve Type = RESOLVE_PARTIAL or RESOLVE_FULL, this bit must be
64     *     DISABLED."
65     */
66 #if GFX_VER >= 8
67    /* BDW has the same wording as SKL, except some of the fields mentioned
68     * don't exist...
69     */
70    if (ps->RenderTargetFastClearEnable ||
71        ps->RenderTargetResolveEnable)
72       enable_8 = false;
73 #endif
74 
75    const bool is_persample_dispatch =
76       elk_wm_prog_data_is_persample(prog_data, msaa_flags);
77 
78    if (is_persample_dispatch) {
79       /* Starting with SandyBridge (where we first get MSAA), the different
80        * pixel dispatch combinations are grouped into classifications A
81        * through F (SNB PRM Vol. 2 Part 1 Section 7.7.1).  On most hardware
82        * generations, the only configurations supporting persample dispatch
83        * are those in which only one dispatch width is enabled.
84        */
85       if (enable_32 || enable_16)
86          enable_8 = false;
87       if (enable_32)
88          enable_16 = false;
89    }
90 
91    assert(enable_8 || enable_16 || enable_32);
92 
93    ps->_8PixelDispatchEnable = enable_8;
94    ps->_16PixelDispatchEnable = enable_16;
95    ps->_32PixelDispatchEnable = enable_32;
96 }
97 
98 #endif
99 
100 #ifdef __cplusplus
101 }
102 #endif
103 
104 #endif /* INTEL_GENX_STATE_ELK_H */
105