xref: /aosp_15_r20/external/mesa3d/src/gallium/drivers/virgl/virgl_screen.c (revision 6104692788411f58d303aa86923a9ff6ecaded22)
1 /*
2  * Copyright 2014, 2015 Red Hat.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * on the rights to use, copy, modify, merge, publish, distribute, sub
8  * license, and/or sell copies of the Software, and to permit persons to whom
9  * the Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice (including the next
12  * paragraph) shall be included in all copies or substantial portions of the
13  * Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
22  */
23 #include "util/u_memory.h"
24 #include "util/format/u_format.h"
25 #include "util/format/u_format_s3tc.h"
26 #include "util/u_screen.h"
27 #include "util/u_video.h"
28 #include "util/u_math.h"
29 #include "util/u_inlines.h"
30 #include "util/os_time.h"
31 #include "util/xmlconfig.h"
32 #include "pipe/p_defines.h"
33 #include "pipe/p_screen.h"
34 #include "nir/nir_to_tgsi.h"
35 #include "vl/vl_decoder.h"
36 #include "vl/vl_video_buffer.h"
37 
38 #include "virgl_screen.h"
39 #include "virgl_resource.h"
40 #include "virgl_public.h"
41 #include "virgl_context.h"
42 #include "virgl_encode.h"
43 
44 int virgl_debug = 0;
45 const struct debug_named_value virgl_debug_options[] = {
46    { "verbose",         VIRGL_DEBUG_VERBOSE,                 NULL },
47    { "tgsi",            VIRGL_DEBUG_TGSI,                    NULL },
48    { "noemubgra",       VIRGL_DEBUG_NO_EMULATE_BGRA,         "Disable tweak to emulate BGRA as RGBA on GLES hosts" },
49    { "nobgraswz",       VIRGL_DEBUG_NO_BGRA_DEST_SWIZZLE,    "Disable tweak to swizzle emulated BGRA on GLES hosts" },
50    { "sync",            VIRGL_DEBUG_SYNC,                    "Sync after every flush" },
51    { "xfer",            VIRGL_DEBUG_XFER,                    "Do not optimize for transfers" },
52    { "r8srgb-readback", VIRGL_DEBUG_L8_SRGB_ENABLE_READBACK, "Enable redaback for L8 sRGB textures" },
53    { "nocoherent",      VIRGL_DEBUG_NO_COHERENT,             "Disable coherent memory" },
54    { "video",           VIRGL_DEBUG_VIDEO,                   "Video codec" },
55    { "shader_sync",     VIRGL_DEBUG_SHADER_SYNC,             "Sync after every shader link" },
56    DEBUG_NAMED_VALUE_END
57 };
58 DEBUG_GET_ONCE_FLAGS_OPTION(virgl_debug, "VIRGL_DEBUG", virgl_debug_options, 0)
59 
60 static const char *
virgl_get_vendor(struct pipe_screen * screen)61 virgl_get_vendor(struct pipe_screen *screen)
62 {
63    return "Mesa";
64 }
65 
66 
67 static const char *
virgl_get_name(struct pipe_screen * screen)68 virgl_get_name(struct pipe_screen *screen)
69 {
70    struct virgl_screen *vscreen = virgl_screen(screen);
71    if (vscreen->caps.caps.v2.host_feature_check_version >= 5)
72       return vscreen->caps.caps.v2.renderer;
73 
74    return "virgl";
75 }
76 
77 static int
virgl_get_param(struct pipe_screen * screen,enum pipe_cap param)78 virgl_get_param(struct pipe_screen *screen, enum pipe_cap param)
79 {
80    struct virgl_screen *vscreen = virgl_screen(screen);
81    switch (param) {
82    case PIPE_CAP_NPOT_TEXTURES:
83       return 1;
84    case PIPE_CAP_FRAGMENT_SHADER_TEXTURE_LOD:
85    case PIPE_CAP_FRAGMENT_SHADER_DERIVATIVES:
86       return 1;
87    case PIPE_CAP_ANISOTROPIC_FILTER:
88       return vscreen->caps.caps.v2.max_anisotropy > 1.0;
89    case PIPE_CAP_MAX_RENDER_TARGETS:
90       return vscreen->caps.caps.v1.max_render_targets;
91    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
92       return vscreen->caps.caps.v1.max_dual_source_render_targets;
93    case PIPE_CAP_OCCLUSION_QUERY:
94       return vscreen->caps.caps.v1.bset.occlusion_query;
95    case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE:
96       if (vscreen->caps.caps.v2.host_feature_check_version >= 20)
97          return vscreen->caps.caps.v2.capability_bits_v2 & VIRGL_CAP_V2_MIRROR_CLAMP_TO_EDGE;
98       FALLTHROUGH;
99    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
100       if (vscreen->caps.caps.v2.host_feature_check_version >= 22)
101          return vscreen->caps.caps.v2.capability_bits_v2 & VIRGL_CAP_V2_MIRROR_CLAMP;
102       return vscreen->caps.caps.v1.bset.mirror_clamp &&
103              !(vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_HOST_IS_GLES);
104    case PIPE_CAP_TEXTURE_SWIZZLE:
105       return 1;
106    case PIPE_CAP_MAX_TEXTURE_2D_SIZE:
107       if (vscreen->caps.caps.v2.max_texture_2d_size)
108          return vscreen->caps.caps.v2.max_texture_2d_size;
109       return 16384;
110    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
111       if (vscreen->caps.caps.v2.max_texture_3d_size)
112          return 1 + util_logbase2(vscreen->caps.caps.v2.max_texture_3d_size);
113       return 9; /* 256 x 256 x 256 */
114    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
115       if (vscreen->caps.caps.v2.max_texture_cube_size)
116          return 1 + util_logbase2(vscreen->caps.caps.v2.max_texture_cube_size);
117       return 13; /* 4K x 4K */
118    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
119       return 1;
120    case PIPE_CAP_INDEP_BLEND_ENABLE:
121       return vscreen->caps.caps.v1.bset.indep_blend_enable;
122    case PIPE_CAP_INDEP_BLEND_FUNC:
123       return vscreen->caps.caps.v1.bset.indep_blend_func;
124    case PIPE_CAP_FS_COORD_ORIGIN_UPPER_LEFT:
125    case PIPE_CAP_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
126    case PIPE_CAP_FS_COORD_PIXEL_CENTER_INTEGER:
127       return 1;
128    case PIPE_CAP_FS_COORD_ORIGIN_LOWER_LEFT:
129       return vscreen->caps.caps.v1.bset.fragment_coord_conventions;
130    case PIPE_CAP_DEPTH_CLIP_DISABLE:
131       if (vscreen->caps.caps.v1.bset.depth_clip_disable)
132          return 1;
133       return 0;
134    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
135       return vscreen->caps.caps.v1.max_streamout_buffers;
136    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
137    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
138       return 16*4;
139    case PIPE_CAP_SUPPORTED_PRIM_MODES:
140       return BITFIELD_MASK(MESA_PRIM_COUNT) &
141             ~BITFIELD_BIT(MESA_PRIM_QUADS) &
142             ~BITFIELD_BIT(MESA_PRIM_QUAD_STRIP);
143    case PIPE_CAP_PRIMITIVE_RESTART:
144    case PIPE_CAP_PRIMITIVE_RESTART_FIXED_INDEX:
145       return vscreen->caps.caps.v1.bset.primitive_restart;
146    case PIPE_CAP_SHADER_STENCIL_EXPORT:
147       return vscreen->caps.caps.v1.bset.shader_stencil_export;
148    case PIPE_CAP_VS_INSTANCEID:
149    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
150       return 1;
151    case PIPE_CAP_SEAMLESS_CUBE_MAP:
152       return vscreen->caps.caps.v1.bset.seamless_cube_map;
153    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
154       return vscreen->caps.caps.v1.bset.seamless_cube_map_per_texture;
155    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
156       return vscreen->caps.caps.v1.max_texture_array_layers;
157    case PIPE_CAP_MIN_TEXEL_OFFSET:
158       return vscreen->caps.caps.v2.min_texel_offset;
159    case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
160       return vscreen->caps.caps.v2.min_texture_gather_offset;
161    case PIPE_CAP_MAX_TEXEL_OFFSET:
162       return vscreen->caps.caps.v2.max_texel_offset;
163    case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
164       return vscreen->caps.caps.v2.max_texture_gather_offset;
165    case PIPE_CAP_CONDITIONAL_RENDER:
166       return vscreen->caps.caps.v1.bset.conditional_render;
167    case PIPE_CAP_TEXTURE_BARRIER:
168       return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_TEXTURE_BARRIER;
169    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
170       return 1;
171    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
172    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
173       return vscreen->caps.caps.v1.bset.color_clamping;
174    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
175       return (vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_FBO_MIXED_COLOR_FORMATS) ||
176             (vscreen->caps.caps.v2.host_feature_check_version < 1);
177    case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
178        if (vscreen->caps.caps.v2.host_feature_check_version < 6)
179            return MIN2(vscreen->caps.caps.v1.glsl_level, 140);
180        FALLTHROUGH;
181    case PIPE_CAP_GLSL_FEATURE_LEVEL:
182       return vscreen->caps.caps.v1.glsl_level;
183    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
184       return 1;
185    case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE:
186       return 0;
187    case PIPE_CAP_COMPUTE:
188       return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_COMPUTE_SHADER;
189    case PIPE_CAP_USER_VERTEX_BUFFERS:
190       return 0;
191    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
192       return vscreen->caps.caps.v2.uniform_buffer_offset_alignment;
193    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
194    case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
195       return vscreen->caps.caps.v1.bset.streamout_pause_resume;
196    case PIPE_CAP_START_INSTANCE:
197       return vscreen->caps.caps.v1.bset.start_instance;
198    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
199    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
200    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
201    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
202    case PIPE_CAP_TEXTURE_TRANSFER_MODES:
203    case PIPE_CAP_NIR_IMAGES_AS_DEREF:
204       return 0;
205    case PIPE_CAP_QUERY_TIMESTAMP:
206    case PIPE_CAP_QUERY_TIME_ELAPSED:
207       if (vscreen->caps.caps.v2.host_feature_check_version >= 15)
208          return vscreen->caps.caps.v1.bset.timer_query;
209       return 1; /* older versions had this always enabled */
210    case PIPE_CAP_TGSI_TEXCOORD:
211       return vscreen->caps.caps.v2.host_feature_check_version >= 10;
212    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
213       return VIRGL_MAP_BUFFER_ALIGNMENT;
214    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
215       return vscreen->caps.caps.v1.max_tbo_size > 0;
216    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
217       return vscreen->caps.caps.v2.texture_buffer_offset_alignment;
218    case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
219       return 0;
220    case PIPE_CAP_CUBE_MAP_ARRAY:
221       return vscreen->caps.caps.v1.bset.cube_map_array;
222    case PIPE_CAP_TEXTURE_MULTISAMPLE:
223       return vscreen->caps.caps.v1.bset.texture_multisample;
224    case PIPE_CAP_MAX_VIEWPORTS:
225       return vscreen->caps.caps.v1.max_viewports;
226    case PIPE_CAP_MAX_TEXEL_BUFFER_ELEMENTS_UINT:
227       return vscreen->caps.caps.v1.max_tbo_size;
228    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
229    case PIPE_CAP_ENDIANNESS:
230       return 0;
231    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
232       return !!(vscreen->caps.caps.v2.capability_bits_v2 & VIRGL_CAP_V2_PIPELINE_STATISTICS_QUERY);
233    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
234    case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
235       return 1;
236    case PIPE_CAP_VS_LAYER_VIEWPORT:
237       return (vscreen->caps.caps.v2.capability_bits_v2 & VIRGL_CAP_V2_VS_VERTEX_LAYER) &&
238             (vscreen->caps.caps.v2.capability_bits_v2 & VIRGL_CAP_V2_VS_VIEWPORT_INDEX);
239    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
240       return vscreen->caps.caps.v2.max_geom_output_vertices;
241    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
242       return vscreen->caps.caps.v2.max_geom_total_output_components;
243    case PIPE_CAP_TEXTURE_QUERY_LOD:
244       return vscreen->caps.caps.v1.bset.texture_query_lod;
245    case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
246       return vscreen->caps.caps.v1.max_texture_gather_components;
247    case PIPE_CAP_DRAW_INDIRECT:
248       return vscreen->caps.caps.v1.bset.has_indirect_draw;
249    case PIPE_CAP_SAMPLE_SHADING:
250    case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
251       return vscreen->caps.caps.v1.bset.has_sample_shading;
252    case PIPE_CAP_CULL_DISTANCE:
253       return vscreen->caps.caps.v1.bset.has_cull;
254    case PIPE_CAP_MAX_VERTEX_STREAMS:
255       return ((vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_TRANSFORM_FEEDBACK3) ||
256               (vscreen->caps.caps.v2.host_feature_check_version < 2)) ? 4 : 1;
257    case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
258       return vscreen->caps.caps.v1.bset.conditional_render_inverted;
259    case PIPE_CAP_FS_FINE_DERIVATIVE:
260       return vscreen->caps.caps.v1.bset.derivative_control;
261    case PIPE_CAP_POLYGON_OFFSET_CLAMP:
262       return vscreen->caps.caps.v1.bset.polygon_offset_clamp;
263    case PIPE_CAP_QUERY_SO_OVERFLOW:
264       return vscreen->caps.caps.v1.bset.transform_feedback_overflow_query;
265    case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
266       return vscreen->caps.caps.v2.shader_buffer_offset_alignment;
267    case PIPE_CAP_DOUBLES:
268       return vscreen->caps.caps.v1.bset.has_fp64 ||
269             (vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_HOST_IS_GLES);
270    case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
271       return vscreen->caps.caps.v2.max_shader_patch_varyings;
272    case PIPE_CAP_SAMPLER_VIEW_TARGET:
273       return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_TEXTURE_VIEW;
274    case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
275       return vscreen->caps.caps.v2.max_vertex_attrib_stride;
276    case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
277       return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_COPY_IMAGE;
278    case PIPE_CAP_TEXTURE_QUERY_SAMPLES:
279       return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_TXQS;
280    case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
281       return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_FB_NO_ATTACH;
282    case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
283       return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_ROBUST_BUFFER_ACCESS;
284    case PIPE_CAP_FBFETCH:
285       return (vscreen->caps.caps.v2.capability_bits &
286               VIRGL_CAP_TGSI_FBFETCH) ? 1 : 0;
287    case PIPE_CAP_BLEND_EQUATION_ADVANCED:
288       return vscreen->caps.caps.v2.capability_bits_v2 & VIRGL_CAP_V2_BLEND_EQUATION;
289    case PIPE_CAP_SHADER_CLOCK:
290       return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_SHADER_CLOCK;
291    case PIPE_CAP_SHADER_ARRAY_COMPONENTS:
292       return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_TGSI_COMPONENTS;
293    case PIPE_CAP_MAX_COMBINED_SHADER_BUFFERS:
294       return vscreen->caps.caps.v2.max_combined_shader_buffers;
295    case PIPE_CAP_MAX_COMBINED_HW_ATOMIC_COUNTERS:
296       return vscreen->caps.caps.v2.max_combined_atomic_counters;
297    case PIPE_CAP_MAX_COMBINED_HW_ATOMIC_COUNTER_BUFFERS:
298       return vscreen->caps.caps.v2.max_combined_atomic_counter_buffers;
299    case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
300    case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
301       return 1; /* TODO: need to introduce a hw-cap for this */
302    case PIPE_CAP_QUERY_BUFFER_OBJECT:
303       return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_QBO;
304    case PIPE_CAP_MAX_VARYINGS:
305       if (vscreen->caps.caps.v1.glsl_level < 150)
306          return vscreen->caps.caps.v2.max_vertex_attribs;
307       return 32;
308    case PIPE_CAP_FAKE_SW_MSAA:
309       /* If the host supports only one sample (e.g., if it is using softpipe),
310        * fake multisampling to able to advertise higher GL versions. */
311       return (vscreen->caps.caps.v1.max_samples == 1) ? 1 : 0;
312    case PIPE_CAP_MULTI_DRAW_INDIRECT:
313       return !!(vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_MULTI_DRAW_INDIRECT);
314    case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
315       return !!(vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_INDIRECT_PARAMS);
316    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
317       return (vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_ARB_BUFFER_STORAGE) &&
318              (vscreen->caps.caps.v2.host_feature_check_version >= 4) &&
319               vscreen->vws->supports_coherent && !vscreen->no_coherent;
320    case PIPE_CAP_PCI_GROUP:
321    case PIPE_CAP_PCI_BUS:
322    case PIPE_CAP_PCI_DEVICE:
323    case PIPE_CAP_PCI_FUNCTION:
324    case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
325       return 0;
326    case PIPE_CAP_CLIP_HALFZ:
327       return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_CLIP_HALFZ;
328    case PIPE_CAP_MAX_GS_INVOCATIONS:
329       return 32;
330    case PIPE_CAP_MAX_SHADER_BUFFER_SIZE_UINT:
331       return 1 << 27;
332    case PIPE_CAP_VENDOR_ID:
333       return 0x1af4;
334    case PIPE_CAP_DEVICE_ID:
335       return 0x1010;
336    case PIPE_CAP_ACCELERATED:
337       return -1; /* -1 means unknown */
338    case PIPE_CAP_UMA:
339    case PIPE_CAP_VIDEO_MEMORY:
340       if (vscreen->caps.caps.v2.capability_bits_v2 & VIRGL_CAP_V2_VIDEO_MEMORY)
341          return vscreen->caps.caps.v2.max_video_memory;
342       return 0;
343    case PIPE_CAP_TEXTURE_SHADOW_LOD:
344       return vscreen->caps.caps.v2.capability_bits_v2 & VIRGL_CAP_V2_TEXTURE_SHADOW_LOD;
345    case PIPE_CAP_NATIVE_FENCE_FD:
346       return vscreen->vws->supports_fences;
347    case PIPE_CAP_DEST_SURFACE_SRGB_CONTROL:
348       return (vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_SRGB_WRITE_CONTROL) ||
349             (vscreen->caps.caps.v2.host_feature_check_version < 1);
350    case PIPE_CAP_SHAREABLE_SHADERS:
351       /* Shader creation emits the shader through the context's command buffer
352        * in virgl_encode_shader_state().
353        */
354       return 0;
355    case PIPE_CAP_QUERY_MEMORY_INFO:
356       return vscreen->caps.caps.v2.capability_bits_v2 & VIRGL_CAP_V2_MEMINFO;
357    case PIPE_CAP_STRING_MARKER:
358        return vscreen->caps.caps.v2.capability_bits_v2 & VIRGL_CAP_V2_STRING_MARKER;
359    case PIPE_CAP_SURFACE_SAMPLE_COUNT:
360        return vscreen->caps.caps.v2.capability_bits_v2 & VIRGL_CAP_V2_IMPLICIT_MSAA;
361    case PIPE_CAP_DRAW_PARAMETERS:
362       return !!(vscreen->caps.caps.v2.capability_bits_v2 & VIRGL_CAP_V2_DRAW_PARAMETERS);
363    case PIPE_CAP_SHADER_GROUP_VOTE:
364       return !!(vscreen->caps.caps.v2.capability_bits_v2 & VIRGL_CAP_V2_GROUP_VOTE);
365    case PIPE_CAP_IMAGE_STORE_FORMATTED:
366    case PIPE_CAP_GL_SPIRV:
367       return 1;
368    case PIPE_CAP_MAX_CONSTANT_BUFFER_SIZE_UINT:
369       if (vscreen->caps.caps.v2.host_feature_check_version >= 13)
370          return vscreen->caps.caps.v2.max_uniform_block_size;
371       FALLTHROUGH;
372    default:
373       return u_pipe_screen_get_param_defaults(screen, param);
374    }
375 }
376 
377 #define VIRGL_SHADER_STAGE_CAP_V2(CAP, STAGE) \
378    vscreen->caps.caps.v2. CAP[virgl_shader_stage_convert(STAGE)]
379 
380 static int
virgl_get_shader_param(struct pipe_screen * screen,enum pipe_shader_type shader,enum pipe_shader_cap param)381 virgl_get_shader_param(struct pipe_screen *screen,
382                        enum pipe_shader_type shader,
383                        enum pipe_shader_cap param)
384 {
385    struct virgl_screen *vscreen = virgl_screen(screen);
386 
387    if ((shader == PIPE_SHADER_TESS_CTRL || shader == PIPE_SHADER_TESS_EVAL) &&
388        !vscreen->caps.caps.v1.bset.has_tessellation_shaders)
389       return 0;
390 
391    if (shader == PIPE_SHADER_COMPUTE &&
392        !(vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_COMPUTE_SHADER))
393      return 0;
394 
395    switch(shader)
396    {
397    case PIPE_SHADER_FRAGMENT:
398    case PIPE_SHADER_VERTEX:
399    case PIPE_SHADER_GEOMETRY:
400    case PIPE_SHADER_TESS_CTRL:
401    case PIPE_SHADER_TESS_EVAL:
402    case PIPE_SHADER_COMPUTE:
403       switch (param) {
404       case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
405       case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
406       case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
407       case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
408          return INT_MAX;
409       case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
410       case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
411       case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
412          return 1;
413       case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
414          if ((vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_HOST_IS_GLES) &&
415              (shader == PIPE_SHADER_VERTEX)) {
416             return 0;
417          }
418          FALLTHROUGH;
419       case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
420          return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_INDIRECT_INPUT_ADDR;
421       case PIPE_SHADER_CAP_MAX_INPUTS:
422          if (vscreen->caps.caps.v1.glsl_level < 150)
423             return vscreen->caps.caps.v2.max_vertex_attribs;
424          return (shader == PIPE_SHADER_VERTEX ||
425                  shader == PIPE_SHADER_GEOMETRY) ? vscreen->caps.caps.v2.max_vertex_attribs : 32;
426       case PIPE_SHADER_CAP_MAX_OUTPUTS:
427          switch (shader) {
428          case PIPE_SHADER_FRAGMENT:
429             return vscreen->caps.caps.v1.max_render_targets;
430          case PIPE_SHADER_TESS_CTRL:
431             if (vscreen->caps.caps.v2.host_feature_check_version >= 19)
432                return vscreen->caps.caps.v2.max_tcs_outputs;
433             FALLTHROUGH;
434          case PIPE_SHADER_TESS_EVAL:
435             if (vscreen->caps.caps.v2.host_feature_check_version >= 19)
436                return vscreen->caps.caps.v2.max_tes_outputs;
437             FALLTHROUGH;
438          default:
439             return vscreen->caps.caps.v2.max_vertex_outputs;
440          }
441      // case PIPE_SHADER_CAP_MAX_CONSTS:
442      //    return 4096;
443       case PIPE_SHADER_CAP_MAX_TEMPS:
444          return 256;
445       case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
446          return vscreen->caps.caps.v1.max_uniform_blocks;
447     //  case PIPE_SHADER_CAP_MAX_ADDRS:
448      //    return 1;
449       case PIPE_SHADER_CAP_SUBROUTINES:
450          return 1;
451       case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
452          return MIN2(vscreen->caps.caps.v2.max_shader_sampler_views,
453                      PIPE_MAX_SHADER_SAMPLER_VIEWS);
454       case PIPE_SHADER_CAP_INTEGERS:
455          return vscreen->caps.caps.v1.glsl_level >= 130;
456       case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
457          return 32;
458       case PIPE_SHADER_CAP_MAX_CONST_BUFFER0_SIZE:
459          if (vscreen->caps.caps.v2.host_feature_check_version < 12)
460             return 4096 * sizeof(float[4]);
461          return VIRGL_SHADER_STAGE_CAP_V2(max_const_buffer_size, shader);
462       case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
463          if (shader == PIPE_SHADER_FRAGMENT || shader == PIPE_SHADER_COMPUTE)
464             return vscreen->caps.caps.v2.max_shader_buffer_frag_compute;
465          else
466             return vscreen->caps.caps.v2.max_shader_buffer_other_stages;
467       case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
468          if (shader == PIPE_SHADER_FRAGMENT || shader == PIPE_SHADER_COMPUTE)
469             return vscreen->caps.caps.v2.max_shader_image_frag_compute;
470          else
471             return vscreen->caps.caps.v2.max_shader_image_other_stages;
472       case PIPE_SHADER_CAP_SUPPORTED_IRS:
473          return (1 << PIPE_SHADER_IR_TGSI) | (1 << PIPE_SHADER_IR_NIR);
474       case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
475          return VIRGL_SHADER_STAGE_CAP_V2(max_atomic_counters, shader);
476       case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
477          return VIRGL_SHADER_STAGE_CAP_V2(max_atomic_counter_buffers, shader);
478       case PIPE_SHADER_CAP_INT64_ATOMICS:
479       case PIPE_SHADER_CAP_FP16:
480       case PIPE_SHADER_CAP_FP16_DERIVATIVES:
481       case PIPE_SHADER_CAP_FP16_CONST_BUFFERS:
482       case PIPE_SHADER_CAP_INT16:
483       case PIPE_SHADER_CAP_GLSL_16BIT_CONSTS:
484          return 0;
485       default:
486          return 0;
487       }
488    default:
489       return 0;
490    }
491 }
492 
493 static int
virgl_get_video_param(struct pipe_screen * screen,enum pipe_video_profile profile,enum pipe_video_entrypoint entrypoint,enum pipe_video_cap param)494 virgl_get_video_param(struct pipe_screen *screen,
495                       enum pipe_video_profile profile,
496                       enum pipe_video_entrypoint entrypoint,
497                       enum pipe_video_cap param)
498 {
499    unsigned i;
500    bool drv_supported;
501    struct virgl_video_caps *vcaps = NULL;
502    struct virgl_screen *vscreen;
503 
504    if (!screen)
505        return 0;
506 
507    vscreen = virgl_screen(screen);
508    if (vscreen->caps.caps.v2.num_video_caps > ARRAY_SIZE(vscreen->caps.caps.v2.video_caps))
509        return 0;
510 
511    /* Profiles and entrypoints supported by the driver */
512    switch (u_reduce_video_profile(profile)) {
513    case PIPE_VIDEO_FORMAT_MPEG4_AVC: /* fall through */
514    case PIPE_VIDEO_FORMAT_HEVC:
515        drv_supported = (entrypoint == PIPE_VIDEO_ENTRYPOINT_BITSTREAM ||
516                         entrypoint == PIPE_VIDEO_ENTRYPOINT_ENCODE);
517        break;
518    case PIPE_VIDEO_FORMAT_MPEG12:
519    case PIPE_VIDEO_FORMAT_VC1:
520    case PIPE_VIDEO_FORMAT_JPEG:
521    case PIPE_VIDEO_FORMAT_VP9:
522    case PIPE_VIDEO_FORMAT_AV1:
523       drv_supported = (entrypoint == PIPE_VIDEO_ENTRYPOINT_BITSTREAM);
524       break;
525    default:
526        drv_supported = false;
527        break;
528    }
529 
530    if (drv_supported) {
531        /* Check if the device supports it, vcaps is NULL means not supported */
532        for (i = 0;  i < vscreen->caps.caps.v2.num_video_caps; i++) {
533            if (vscreen->caps.caps.v2.video_caps[i].profile == profile &&
534                vscreen->caps.caps.v2.video_caps[i].entrypoint == entrypoint) {
535                vcaps = &vscreen->caps.caps.v2.video_caps[i];
536                break;
537            }
538        }
539    }
540 
541    /*
542     * Since there are calls like this:
543     *   pot_buffers = !pipe->screen->get_video_param
544     *   (
545     *      pipe->screen,
546     *      PIPE_VIDEO_PROFILE_UNKNOWN,
547     *      PIPE_VIDEO_ENTRYPOINT_UNKNOWN,
548     *      PIPE_VIDEO_CAP_NPOT_TEXTURES
549     *   );
550     * All parameters need to check the vcaps.
551     */
552    switch (param) {
553       case PIPE_VIDEO_CAP_SUPPORTED:
554          return vcaps != NULL;
555       case PIPE_VIDEO_CAP_NPOT_TEXTURES:
556          return vcaps ? vcaps->npot_texture : true;
557       case PIPE_VIDEO_CAP_MAX_WIDTH:
558          return vcaps ? vcaps->max_width : 0;
559       case PIPE_VIDEO_CAP_MAX_HEIGHT:
560          return vcaps ? vcaps->max_height : 0;
561       case PIPE_VIDEO_CAP_PREFERED_FORMAT:
562          return vcaps ? virgl_to_pipe_format(vcaps->prefered_format) : PIPE_FORMAT_NV12;
563       case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
564          return vcaps ? vcaps->prefers_interlaced : false;
565       case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
566          return vcaps ? vcaps->supports_interlaced : false;
567       case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
568          return vcaps ? vcaps->supports_progressive : true;
569       case PIPE_VIDEO_CAP_MAX_LEVEL:
570          return vcaps ? vcaps->max_level : 0;
571       case PIPE_VIDEO_CAP_STACKED_FRAMES:
572          return vcaps ? vcaps->stacked_frames : 0;
573       case PIPE_VIDEO_CAP_MAX_MACROBLOCKS:
574          return vcaps ? vcaps->max_macroblocks : 0;
575       case PIPE_VIDEO_CAP_MAX_TEMPORAL_LAYERS:
576          return vcaps ? vcaps->max_temporal_layers : 0;
577       default:
578          return 0;
579    }
580 }
581 
582 static float
virgl_get_paramf(struct pipe_screen * screen,enum pipe_capf param)583 virgl_get_paramf(struct pipe_screen *screen, enum pipe_capf param)
584 {
585    struct virgl_screen *vscreen = virgl_screen(screen);
586    switch (param) {
587    case PIPE_CAPF_MIN_LINE_WIDTH:
588    case PIPE_CAPF_MIN_LINE_WIDTH_AA:
589    case PIPE_CAPF_MIN_POINT_SIZE:
590    case PIPE_CAPF_MIN_POINT_SIZE_AA:
591       return 1;
592    case PIPE_CAPF_POINT_SIZE_GRANULARITY:
593    case PIPE_CAPF_LINE_WIDTH_GRANULARITY:
594       return 0.1;
595    case PIPE_CAPF_MAX_LINE_WIDTH:
596       return vscreen->caps.caps.v2.max_aliased_line_width;
597    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
598       return vscreen->caps.caps.v2.max_smooth_line_width;
599    case PIPE_CAPF_MAX_POINT_SIZE:
600       return vscreen->caps.caps.v2.max_aliased_point_size;
601    case PIPE_CAPF_MAX_POINT_SIZE_AA:
602       return vscreen->caps.caps.v2.max_smooth_point_size;
603    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
604       return vscreen->caps.caps.v2.max_anisotropy;
605    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
606       return vscreen->caps.caps.v2.max_texture_lod_bias;
607    case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
608    case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
609    case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
610       return 0.0f;
611    }
612    /* should only get here on unhandled cases */
613    debug_printf("Unexpected PIPE_CAPF %d query\n", param);
614    return 0.0;
615 }
616 
617 static int
virgl_get_compute_param(struct pipe_screen * screen,enum pipe_shader_ir ir_type,enum pipe_compute_cap param,void * ret)618 virgl_get_compute_param(struct pipe_screen *screen,
619                         enum pipe_shader_ir ir_type,
620                         enum pipe_compute_cap param,
621                         void *ret)
622 {
623    struct virgl_screen *vscreen = virgl_screen(screen);
624    if (!(vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_COMPUTE_SHADER))
625       return 0;
626    switch (param) {
627    case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
628       if (ret) {
629          uint64_t *grid_size = ret;
630          grid_size[0] = vscreen->caps.caps.v2.max_compute_grid_size[0];
631          grid_size[1] = vscreen->caps.caps.v2.max_compute_grid_size[1];
632          grid_size[2] = vscreen->caps.caps.v2.max_compute_grid_size[2];
633       }
634       return 3 * sizeof(uint64_t) ;
635    case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
636       if (ret) {
637          uint64_t *block_size = ret;
638          block_size[0] = vscreen->caps.caps.v2.max_compute_block_size[0];
639          block_size[1] = vscreen->caps.caps.v2.max_compute_block_size[1];
640          block_size[2] = vscreen->caps.caps.v2.max_compute_block_size[2];
641       }
642       return 3 * sizeof(uint64_t);
643    case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
644       if (ret) {
645          uint64_t *max_threads_per_block = ret;
646          *max_threads_per_block = vscreen->caps.caps.v2.max_compute_work_group_invocations;
647       }
648       return sizeof(uint64_t);
649    case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
650       if (ret) {
651          uint64_t *max_local_size = ret;
652          /* Value reported by the closed source driver. */
653          *max_local_size = vscreen->caps.caps.v2.max_compute_shared_memory_size;
654       }
655       return sizeof(uint64_t);
656    default:
657       break;
658    }
659    return 0;
660 }
661 
662 static bool
has_format_bit(struct virgl_supported_format_mask * mask,enum virgl_formats fmt)663 has_format_bit(struct virgl_supported_format_mask *mask,
664                enum virgl_formats fmt)
665 {
666    assert(fmt < VIRGL_FORMAT_MAX);
667    unsigned val = (unsigned)fmt;
668    unsigned idx = val / 32;
669    unsigned bit = val % 32;
670    assert(idx < ARRAY_SIZE(mask->bitmask));
671    return (mask->bitmask[idx] & (1u << bit)) != 0;
672 }
673 
674 bool
virgl_has_readback_format(struct pipe_screen * screen,enum virgl_formats fmt,bool allow_tweak)675 virgl_has_readback_format(struct pipe_screen *screen,
676                           enum virgl_formats fmt, bool allow_tweak)
677 {
678    struct virgl_screen *vscreen = virgl_screen(screen);
679    if (has_format_bit(&vscreen->caps.caps.v2.supported_readback_formats,
680                          fmt))
681       return true;
682 
683    if (allow_tweak && fmt == VIRGL_FORMAT_L8_SRGB && vscreen->tweak_l8_srgb_readback) {
684       return true;
685    }
686 
687    return false;
688 }
689 
690 static bool
virgl_is_vertex_format_supported(struct pipe_screen * screen,enum pipe_format format)691 virgl_is_vertex_format_supported(struct pipe_screen *screen,
692                                  enum pipe_format format)
693 {
694    struct virgl_screen *vscreen = virgl_screen(screen);
695    const struct util_format_description *format_desc;
696    int i;
697 
698    format_desc = util_format_description(format);
699 
700    if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
701       int vformat = VIRGL_FORMAT_R11G11B10_FLOAT;
702       int big = vformat / 32;
703       int small = vformat % 32;
704       if (!(vscreen->caps.caps.v1.vertexbuffer.bitmask[big] & (1 << small)))
705          return false;
706       return true;
707    }
708 
709    i = util_format_get_first_non_void_channel(format);
710    if (i == -1)
711       return false;
712 
713    if (format_desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
714       return false;
715 
716    if (format_desc->channel[i].type == UTIL_FORMAT_TYPE_FIXED)
717       return false;
718    return true;
719 }
720 
721 static bool
virgl_format_check_bitmask(enum pipe_format format,uint32_t bitmask[16],bool may_emulate_bgra)722 virgl_format_check_bitmask(enum pipe_format format,
723                            uint32_t bitmask[16],
724                            bool may_emulate_bgra)
725 {
726    enum virgl_formats vformat = pipe_to_virgl_format(format);
727    int big = vformat / 32;
728    int small = vformat % 32;
729    if ((bitmask[big] & (1u << small)))
730       return true;
731 
732    /* On GLES hosts we don't advertise BGRx_SRGB, but we may be able
733     * emulate it by using a swizzled RGBx */
734    if (may_emulate_bgra) {
735       if (format == PIPE_FORMAT_B8G8R8A8_SRGB)
736          format = PIPE_FORMAT_R8G8B8A8_SRGB;
737       else if (format == PIPE_FORMAT_B8G8R8X8_SRGB)
738          format = PIPE_FORMAT_R8G8B8X8_SRGB;
739       else {
740          return false;
741       }
742 
743       vformat = pipe_to_virgl_format(format);
744       big = vformat / 32;
745       small = vformat % 32;
746       if (bitmask[big] & (1 << small))
747          return true;
748    }
749    return false;
750 }
751 
virgl_has_scanout_format(struct virgl_screen * vscreen,enum pipe_format format,bool may_emulate_bgra)752 bool virgl_has_scanout_format(struct virgl_screen *vscreen,
753                               enum pipe_format format,
754                               bool may_emulate_bgra)
755 {
756    return  virgl_format_check_bitmask(format,
757                                       vscreen->caps.caps.v2.scanout.bitmask,
758                                       may_emulate_bgra);
759 }
760 
761 /**
762  * Query format support for creating a texture, drawing surface, etc.
763  * \param format  the format to test
764  * \param type  one of PIPE_TEXTURE, PIPE_SURFACE
765  */
766 static bool
virgl_is_format_supported(struct pipe_screen * screen,enum pipe_format format,enum pipe_texture_target target,unsigned sample_count,unsigned storage_sample_count,unsigned bind)767 virgl_is_format_supported( struct pipe_screen *screen,
768                                  enum pipe_format format,
769                                  enum pipe_texture_target target,
770                                  unsigned sample_count,
771                                  unsigned storage_sample_count,
772                                  unsigned bind)
773 {
774    struct virgl_screen *vscreen = virgl_screen(screen);
775    const struct util_format_description *format_desc;
776    int i;
777 
778    union virgl_caps *caps = &vscreen->caps.caps;
779    bool may_emulate_bgra = (caps->v2.capability_bits &
780                             VIRGL_CAP_APP_TWEAK_SUPPORT) &&
781                             vscreen->tweak_gles_emulate_bgra;
782 
783    if (MAX2(1, sample_count) != MAX2(1, storage_sample_count))
784       return false;
785 
786    if (!util_is_power_of_two_or_zero(sample_count))
787       return false;
788 
789    assert(target == PIPE_BUFFER ||
790           target == PIPE_TEXTURE_1D ||
791           target == PIPE_TEXTURE_1D_ARRAY ||
792           target == PIPE_TEXTURE_2D ||
793           target == PIPE_TEXTURE_2D_ARRAY ||
794           target == PIPE_TEXTURE_RECT ||
795           target == PIPE_TEXTURE_3D ||
796           target == PIPE_TEXTURE_CUBE ||
797           target == PIPE_TEXTURE_CUBE_ARRAY);
798 
799    format_desc = util_format_description(format);
800 
801    if (util_format_is_intensity(format))
802       return false;
803 
804    if (sample_count > 1) {
805       if (!caps->v1.bset.texture_multisample)
806          return false;
807 
808       if (bind & PIPE_BIND_SHADER_IMAGE) {
809          if (sample_count > caps->v2.max_image_samples)
810             return false;
811       }
812 
813       if (sample_count > caps->v1.max_samples)
814          return false;
815 
816       if (caps->v2.host_feature_check_version >= 9 &&
817           !has_format_bit(&caps->v2.supported_multisample_formats,
818                           pipe_to_virgl_format(format)))
819          return false;
820    }
821 
822    if (bind & PIPE_BIND_VERTEX_BUFFER) {
823       return virgl_is_vertex_format_supported(screen, format);
824    }
825 
826    if (util_format_is_compressed(format) && target == PIPE_BUFFER)
827       return false;
828 
829    /* Allow 3-comp 32 bit textures only for TBOs (needed for ARB_tbo_rgb32) */
830    if ((format == PIPE_FORMAT_R32G32B32_FLOAT ||
831        format == PIPE_FORMAT_R32G32B32_SINT ||
832        format == PIPE_FORMAT_R32G32B32_UINT) &&
833        target != PIPE_BUFFER)
834       return false;
835 
836    if ((format_desc->layout == UTIL_FORMAT_LAYOUT_RGTC ||
837         format_desc->layout == UTIL_FORMAT_LAYOUT_ETC ||
838         format_desc->layout == UTIL_FORMAT_LAYOUT_S3TC) &&
839        target == PIPE_TEXTURE_3D)
840       return false;
841 
842 
843    if (bind & PIPE_BIND_RENDER_TARGET) {
844       /* For ARB_framebuffer_no_attachments. */
845       if (format == PIPE_FORMAT_NONE)
846          return true;
847 
848       if (format_desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS)
849          return false;
850 
851       /*
852        * Although possible, it is unnatural to render into compressed or YUV
853        * surfaces. So disable these here to avoid going into weird paths
854        * inside gallium frontends.
855        */
856       if (format_desc->block.width != 1 ||
857           format_desc->block.height != 1)
858          return false;
859 
860       if (!virgl_format_check_bitmask(format,
861                                       caps->v1.render.bitmask,
862                                       may_emulate_bgra))
863          return false;
864    }
865 
866    if (bind & PIPE_BIND_DEPTH_STENCIL) {
867       if (format_desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
868          return false;
869    }
870 
871    if (bind & PIPE_BIND_SCANOUT) {
872       if (!virgl_format_check_bitmask(format, caps->v2.scanout.bitmask, false))
873          return false;
874    }
875 
876    /*
877     * All other operations (sampling, transfer, etc).
878     */
879 
880    if (format_desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
881       goto out_lookup;
882    }
883    if (format_desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
884       goto out_lookup;
885    }
886    if (format_desc->layout == UTIL_FORMAT_LAYOUT_BPTC) {
887       goto out_lookup;
888    }
889    if (format_desc->layout == UTIL_FORMAT_LAYOUT_ETC) {
890       goto out_lookup;
891    }
892 
893    if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
894       goto out_lookup;
895    } else if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
896       goto out_lookup;
897    }
898 
899    if (format_desc->layout == UTIL_FORMAT_LAYOUT_ASTC) {
900      goto out_lookup;
901    }
902 
903    i = util_format_get_first_non_void_channel(format);
904    if (i == -1)
905       return false;
906 
907    /* no L4A4 */
908    if (format_desc->nr_channels < 4 && format_desc->channel[i].size == 4)
909       return false;
910 
911  out_lookup:
912    return virgl_format_check_bitmask(format,
913                                      caps->v1.sampler.bitmask,
914                                      may_emulate_bgra);
915 }
916 
virgl_is_video_format_supported(struct pipe_screen * screen,enum pipe_format format,enum pipe_video_profile profile,enum pipe_video_entrypoint entrypoint)917 static bool virgl_is_video_format_supported(struct pipe_screen *screen,
918                                             enum pipe_format format,
919                                             enum pipe_video_profile profile,
920                                             enum pipe_video_entrypoint entrypoint)
921 {
922     return vl_video_buffer_is_format_supported(screen, format, profile, entrypoint);
923 }
924 
925 
virgl_flush_frontbuffer(struct pipe_screen * screen,struct pipe_context * ctx,struct pipe_resource * res,unsigned level,unsigned layer,void * winsys_drawable_handle,unsigned nboxes,struct pipe_box * sub_box)926 static void virgl_flush_frontbuffer(struct pipe_screen *screen,
927                                     struct pipe_context *ctx,
928                                       struct pipe_resource *res,
929                                       unsigned level, unsigned layer,
930                                     void *winsys_drawable_handle, unsigned nboxes, struct pipe_box *sub_box)
931 {
932    struct virgl_screen *vscreen = virgl_screen(screen);
933    struct virgl_winsys *vws = vscreen->vws;
934    struct virgl_resource *vres = virgl_resource(res);
935    struct virgl_context *vctx = virgl_context(ctx);
936 
937    if (vws->flush_frontbuffer) {
938       virgl_flush_eq(vctx, vctx, NULL);
939       vws->flush_frontbuffer(vws, vctx->cbuf, vres->hw_res, level, layer, winsys_drawable_handle,
940                              nboxes == 1 ? sub_box : NULL);
941    }
942 }
943 
virgl_fence_reference(struct pipe_screen * screen,struct pipe_fence_handle ** ptr,struct pipe_fence_handle * fence)944 static void virgl_fence_reference(struct pipe_screen *screen,
945                                   struct pipe_fence_handle **ptr,
946                                   struct pipe_fence_handle *fence)
947 {
948    struct virgl_screen *vscreen = virgl_screen(screen);
949    struct virgl_winsys *vws = vscreen->vws;
950 
951    vws->fence_reference(vws, ptr, fence);
952 }
953 
virgl_fence_finish(struct pipe_screen * screen,struct pipe_context * ctx,struct pipe_fence_handle * fence,uint64_t timeout)954 static bool virgl_fence_finish(struct pipe_screen *screen,
955                                struct pipe_context *ctx,
956                                struct pipe_fence_handle *fence,
957                                uint64_t timeout)
958 {
959    struct virgl_screen *vscreen = virgl_screen(screen);
960    struct virgl_winsys *vws = vscreen->vws;
961    struct virgl_context *vctx = virgl_context(ctx);
962 
963    if (vctx && timeout)
964       virgl_flush_eq(vctx, NULL, NULL);
965 
966    return vws->fence_wait(vws, fence, timeout);
967 }
968 
virgl_fence_get_fd(struct pipe_screen * screen,struct pipe_fence_handle * fence)969 static int virgl_fence_get_fd(struct pipe_screen *screen,
970             struct pipe_fence_handle *fence)
971 {
972    struct virgl_screen *vscreen = virgl_screen(screen);
973    struct virgl_winsys *vws = vscreen->vws;
974 
975    return vws->fence_get_fd(vws, fence);
976 }
977 
978 static void
virgl_destroy_screen(struct pipe_screen * screen)979 virgl_destroy_screen(struct pipe_screen *screen)
980 {
981    struct virgl_screen *vscreen = virgl_screen(screen);
982    struct virgl_winsys *vws = vscreen->vws;
983 
984    slab_destroy_parent(&vscreen->transfer_pool);
985 
986    if (vws)
987       vws->destroy(vws);
988 
989    disk_cache_destroy(vscreen->disk_cache);
990 
991    FREE(vscreen);
992 }
993 
994 static void
fixup_formats(union virgl_caps * caps,struct virgl_supported_format_mask * mask)995 fixup_formats(union virgl_caps *caps, struct virgl_supported_format_mask *mask)
996 {
997    const size_t size = ARRAY_SIZE(mask->bitmask);
998    for (int i = 0; i < size; ++i) {
999       if (mask->bitmask[i] != 0)
1000          return; /* we got some formats, we definitely have a new protocol */
1001    }
1002 
1003    /* old protocol used; fall back to considering all sampleable formats valid
1004     * readback-formats
1005     */
1006    for (int i = 0; i < size; ++i)
1007       mask->bitmask[i] = caps->v1.sampler.bitmask[i];
1008 }
1009 
virgl_query_memory_info(struct pipe_screen * screen,struct pipe_memory_info * info)1010 static void virgl_query_memory_info(struct pipe_screen *screen, struct pipe_memory_info *info)
1011 {
1012    struct virgl_screen *vscreen = virgl_screen(screen);
1013    struct pipe_context *ctx = screen->context_create(screen, NULL, 0);
1014    struct virgl_context *vctx = virgl_context(ctx);
1015    struct virgl_resource *res;
1016    struct virgl_memory_info virgl_info = {0};
1017    const static struct pipe_resource templ = {
1018       .target = PIPE_BUFFER,
1019       .format = PIPE_FORMAT_R8_UNORM,
1020       .bind = PIPE_BIND_CUSTOM,
1021       .width0 = sizeof(struct virgl_memory_info),
1022       .height0 = 1,
1023       .depth0 = 1,
1024       .array_size = 1,
1025       .last_level = 0,
1026       .nr_samples = 0,
1027       .flags = 0
1028    };
1029 
1030    res = (struct virgl_resource*) screen->resource_create(screen, &templ);
1031 
1032    virgl_encode_get_memory_info(vctx, res);
1033    ctx->flush(ctx, NULL, 0);
1034    vscreen->vws->resource_wait(vscreen->vws, res->hw_res);
1035    pipe_buffer_read(ctx, &res->b, 0, sizeof(struct virgl_memory_info), &virgl_info);
1036 
1037    info->avail_device_memory = virgl_info.avail_device_memory;
1038    info->avail_staging_memory = virgl_info.avail_staging_memory;
1039    info->device_memory_evicted = virgl_info.device_memory_evicted;
1040    info->nr_device_memory_evictions = virgl_info.nr_device_memory_evictions;
1041    info->total_device_memory = virgl_info.total_device_memory;
1042    info->total_staging_memory = virgl_info.total_staging_memory;
1043 
1044    screen->resource_destroy(screen, &res->b);
1045    ctx->destroy(ctx);
1046 }
1047 
virgl_get_disk_shader_cache(struct pipe_screen * pscreen)1048 static struct disk_cache *virgl_get_disk_shader_cache (struct pipe_screen *pscreen)
1049 {
1050    struct virgl_screen *screen = virgl_screen(pscreen);
1051 
1052    return screen->disk_cache;
1053 }
1054 
virgl_disk_cache_create(struct virgl_screen * screen)1055 static void virgl_disk_cache_create(struct virgl_screen *screen)
1056 {
1057    struct mesa_sha1 sha1_ctx;
1058    _mesa_sha1_init(&sha1_ctx);
1059 
1060 #ifdef HAVE_DL_ITERATE_PHDR
1061    const struct build_id_note *note =
1062       build_id_find_nhdr_for_addr(virgl_disk_cache_create);
1063    assert(note);
1064 
1065    unsigned build_id_len = build_id_length(note);
1066    assert(build_id_len == 20); /* sha1 */
1067 
1068    const uint8_t *id_sha1 = build_id_data(note);
1069    assert(id_sha1);
1070 
1071    _mesa_sha1_update(&sha1_ctx, id_sha1, build_id_len);
1072 #endif
1073 
1074    /* When we switch the host the caps might change and then we might have to
1075     * apply different lowering. */
1076    _mesa_sha1_update(&sha1_ctx, &screen->caps, sizeof(screen->caps));
1077 
1078    uint8_t sha1[20];
1079    _mesa_sha1_final(&sha1_ctx, sha1);
1080    char timestamp[41];
1081    _mesa_sha1_format(timestamp, sha1);
1082 
1083    screen->disk_cache = disk_cache_create("virgl", timestamp, 0);
1084 }
1085 
1086 static bool
virgl_is_dmabuf_modifier_supported(UNUSED struct pipe_screen * pscreen,UNUSED uint64_t modifier,UNUSED enum pipe_format format,UNUSED bool * external_only)1087 virgl_is_dmabuf_modifier_supported(UNUSED struct pipe_screen *pscreen,
1088                                    UNUSED uint64_t modifier,
1089                                    UNUSED enum pipe_format format,
1090                                    UNUSED bool *external_only)
1091 {
1092    /* Always advertise support until virgl starts checking against host
1093     * virglrenderer or consuming valid non-linear modifiers here.
1094     */
1095    return true;
1096 }
1097 
1098 static unsigned int
virgl_get_dmabuf_modifier_planes(UNUSED struct pipe_screen * pscreen,UNUSED uint64_t modifier,enum pipe_format format)1099 virgl_get_dmabuf_modifier_planes(UNUSED struct pipe_screen *pscreen,
1100                                  UNUSED uint64_t modifier,
1101                                  enum pipe_format format)
1102 {
1103    /* Return the format plane count queried from pipe_format. For virgl,
1104     * additional aux planes are entirely resolved on the host side.
1105     */
1106    return util_format_get_num_planes(format);
1107 }
1108 
1109 static void
fixup_renderer(union virgl_caps * caps)1110 fixup_renderer(union virgl_caps *caps)
1111 {
1112    if (caps->v2.host_feature_check_version < 5)
1113       return;
1114 
1115    char renderer[64];
1116    int renderer_len = snprintf(renderer, sizeof(renderer), "virgl (%s)",
1117                                caps->v2.renderer);
1118    if (renderer_len >= 64) {
1119       memcpy(renderer + 59, "...)", 4);
1120       renderer_len = 63;
1121    }
1122    memcpy(caps->v2.renderer, renderer, renderer_len + 1);
1123 }
1124 
1125 static const void *
virgl_get_compiler_options(struct pipe_screen * pscreen,enum pipe_shader_ir ir,enum pipe_shader_type shader)1126 virgl_get_compiler_options(struct pipe_screen *pscreen,
1127                            enum pipe_shader_ir ir,
1128                            enum pipe_shader_type shader)
1129 {
1130    struct virgl_screen *vscreen = virgl_screen(pscreen);
1131 
1132    return &vscreen->compiler_options;
1133 }
1134 
1135 static int
virgl_screen_get_fd(struct pipe_screen * pscreen)1136 virgl_screen_get_fd(struct pipe_screen *pscreen)
1137 {
1138    struct virgl_screen *vscreen = virgl_screen(pscreen);
1139    struct virgl_winsys *vws = vscreen->vws;
1140 
1141    if (vws->get_fd)
1142       return vws->get_fd(vws);
1143    else
1144       return -1;
1145 }
1146 
1147 struct pipe_screen *
virgl_create_screen(struct virgl_winsys * vws,const struct pipe_screen_config * config)1148 virgl_create_screen(struct virgl_winsys *vws, const struct pipe_screen_config *config)
1149 {
1150    struct virgl_screen *screen = CALLOC_STRUCT(virgl_screen);
1151 
1152    const char *VIRGL_GLES_EMULATE_BGRA = "gles_emulate_bgra";
1153    const char *VIRGL_GLES_APPLY_BGRA_DEST_SWIZZLE = "gles_apply_bgra_dest_swizzle";
1154    const char *VIRGL_GLES_SAMPLES_PASSED_VALUE = "gles_samples_passed_value";
1155    const char *VIRGL_FORMAT_L8_SRGB_ENABLE_READBACK = "format_l8_srgb_enable_readback";
1156    const char *VIRGL_SHADER_SYNC = "virgl_shader_sync";
1157 
1158    if (!screen)
1159       return NULL;
1160 
1161    virgl_debug = debug_get_option_virgl_debug();
1162 
1163    if (config && config->options) {
1164       driParseConfigFiles(config->options, config->options_info, 0, "virtio_gpu",
1165                           NULL, NULL, NULL, 0, NULL, 0);
1166 
1167       screen->tweak_gles_emulate_bgra =
1168             driQueryOptionb(config->options, VIRGL_GLES_EMULATE_BGRA);
1169       screen->tweak_gles_apply_bgra_dest_swizzle =
1170             driQueryOptionb(config->options, VIRGL_GLES_APPLY_BGRA_DEST_SWIZZLE);
1171       screen->tweak_gles_tf3_value =
1172             driQueryOptioni(config->options, VIRGL_GLES_SAMPLES_PASSED_VALUE);
1173       screen->tweak_l8_srgb_readback =
1174             driQueryOptionb(config->options, VIRGL_FORMAT_L8_SRGB_ENABLE_READBACK);
1175       screen->shader_sync = driQueryOptionb(config->options, VIRGL_SHADER_SYNC);
1176    }
1177    screen->tweak_gles_emulate_bgra &= !(virgl_debug & VIRGL_DEBUG_NO_EMULATE_BGRA);
1178    screen->tweak_gles_apply_bgra_dest_swizzle &= !(virgl_debug & VIRGL_DEBUG_NO_BGRA_DEST_SWIZZLE);
1179    screen->no_coherent = virgl_debug & VIRGL_DEBUG_NO_COHERENT;
1180    screen->tweak_l8_srgb_readback |= !!(virgl_debug & VIRGL_DEBUG_L8_SRGB_ENABLE_READBACK);
1181    screen->shader_sync |= !!(virgl_debug & VIRGL_DEBUG_SHADER_SYNC);
1182 
1183    screen->vws = vws;
1184    screen->base.get_name = virgl_get_name;
1185    screen->base.get_vendor = virgl_get_vendor;
1186    screen->base.get_screen_fd = virgl_screen_get_fd;
1187    screen->base.get_param = virgl_get_param;
1188    screen->base.get_shader_param = virgl_get_shader_param;
1189    screen->base.get_video_param = virgl_get_video_param;
1190    screen->base.get_compute_param = virgl_get_compute_param;
1191    screen->base.get_paramf = virgl_get_paramf;
1192    screen->base.get_compiler_options = virgl_get_compiler_options;
1193    screen->base.is_format_supported = virgl_is_format_supported;
1194    screen->base.is_video_format_supported = virgl_is_video_format_supported;
1195    screen->base.destroy = virgl_destroy_screen;
1196    screen->base.context_create = virgl_context_create;
1197    screen->base.flush_frontbuffer = virgl_flush_frontbuffer;
1198    screen->base.get_timestamp = u_default_get_timestamp;
1199    screen->base.fence_reference = virgl_fence_reference;
1200    //screen->base.fence_signalled = virgl_fence_signalled;
1201    screen->base.fence_finish = virgl_fence_finish;
1202    screen->base.fence_get_fd = virgl_fence_get_fd;
1203    screen->base.query_memory_info = virgl_query_memory_info;
1204    screen->base.get_disk_shader_cache = virgl_get_disk_shader_cache;
1205    screen->base.is_dmabuf_modifier_supported = virgl_is_dmabuf_modifier_supported;
1206    screen->base.get_dmabuf_modifier_planes = virgl_get_dmabuf_modifier_planes;
1207 
1208    virgl_init_screen_resource_functions(&screen->base);
1209 
1210    vws->get_caps(vws, &screen->caps);
1211    fixup_formats(&screen->caps.caps,
1212                  &screen->caps.caps.v2.supported_readback_formats);
1213    fixup_formats(&screen->caps.caps, &screen->caps.caps.v2.scanout);
1214    fixup_renderer(&screen->caps.caps);
1215 
1216    union virgl_caps *caps = &screen->caps.caps;
1217    screen->tweak_gles_emulate_bgra &= !virgl_format_check_bitmask(PIPE_FORMAT_B8G8R8A8_SRGB, caps->v1.render.bitmask, false);
1218    screen->refcnt = 1;
1219 
1220    /* Set up the NIR shader compiler options now that we've figured out the caps. */
1221    screen->compiler_options = *(nir_shader_compiler_options *)
1222       nir_to_tgsi_get_compiler_options(&screen->base, PIPE_SHADER_IR_NIR, PIPE_SHADER_FRAGMENT);
1223    if (virgl_get_param(&screen->base, PIPE_CAP_DOUBLES)) {
1224       /* virglrenderer is missing DFLR support, so avoid turning 64-bit
1225        * ffract+fsub back into ffloor.
1226        */
1227       screen->compiler_options.lower_ffloor = true;
1228       screen->compiler_options.lower_fneg = true;
1229    }
1230    screen->compiler_options.no_integers = screen->caps.caps.v1.glsl_level < 130;
1231    screen->compiler_options.lower_ffma32 = true;
1232    screen->compiler_options.fuse_ffma32 = false;
1233    screen->compiler_options.lower_ldexp = true;
1234    screen->compiler_options.lower_image_offset_to_range_base = true;
1235    screen->compiler_options.lower_atomic_offset_to_range_base = true;
1236 
1237    slab_create_parent(&screen->transfer_pool, sizeof(struct virgl_transfer), 16);
1238 
1239    virgl_disk_cache_create(screen);
1240    return &screen->base;
1241 }
1242