1 /*
2 * Copyright © 2014 Broadcom
3 * Copyright (C) 2012 Rob Clark <[email protected]>
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
22 * IN THE SOFTWARE.
23 */
24
25 #include "util/os_misc.h"
26 #include "pipe/p_defines.h"
27 #include "pipe/p_screen.h"
28 #include "pipe/p_state.h"
29
30 #include "util/u_debug.h"
31 #include "util/u_memory.h"
32 #include "util/format/u_format.h"
33 #include "util/u_hash_table.h"
34 #include "util/u_screen.h"
35 #include "util/u_transfer_helper.h"
36 #include "util/ralloc.h"
37
38 #include <xf86drm.h>
39 #include "drm-uapi/drm_fourcc.h"
40 #include "drm-uapi/vc4_drm.h"
41 #include "vc4_screen.h"
42 #include "vc4_context.h"
43 #include "vc4_resource.h"
44
45 static const struct debug_named_value vc4_debug_options[] = {
46 { "cl", VC4_DEBUG_CL,
47 "Dump command list during creation" },
48 { "surf", VC4_DEBUG_SURFACE,
49 "Dump surface layouts" },
50 { "qpu", VC4_DEBUG_QPU,
51 "Dump generated QPU instructions" },
52 { "qir", VC4_DEBUG_QIR,
53 "Dump QPU IR during program compile" },
54 { "nir", VC4_DEBUG_NIR,
55 "Dump NIR during program compile" },
56 { "tgsi", VC4_DEBUG_TGSI,
57 "Dump TGSI during program compile" },
58 { "shaderdb", VC4_DEBUG_SHADERDB,
59 "Dump program compile information for shader-db analysis" },
60 { "perf", VC4_DEBUG_PERF,
61 "Print during performance-related events" },
62 { "norast", VC4_DEBUG_NORAST,
63 "Skip actual hardware execution of commands" },
64 { "always_flush", VC4_DEBUG_ALWAYS_FLUSH,
65 "Flush after each draw call" },
66 { "always_sync", VC4_DEBUG_ALWAYS_SYNC,
67 "Wait for finish after each flush" },
68 #ifdef USE_VC4_SIMULATOR
69 { "dump", VC4_DEBUG_DUMP,
70 "Write a GPU command stream trace file" },
71 #endif
72 DEBUG_NAMED_VALUE_END
73 };
74
75 DEBUG_GET_ONCE_FLAGS_OPTION(vc4_debug, "VC4_DEBUG", vc4_debug_options, 0)
76 uint32_t vc4_mesa_debug;
77
78 static const char *
vc4_screen_get_name(struct pipe_screen * pscreen)79 vc4_screen_get_name(struct pipe_screen *pscreen)
80 {
81 struct vc4_screen *screen = vc4_screen(pscreen);
82
83 if (!screen->name) {
84 screen->name = ralloc_asprintf(screen,
85 "VC4 V3D %d.%d",
86 screen->v3d_ver / 10,
87 screen->v3d_ver % 10);
88 }
89
90 return screen->name;
91 }
92
93 static const char *
vc4_screen_get_vendor(struct pipe_screen * pscreen)94 vc4_screen_get_vendor(struct pipe_screen *pscreen)
95 {
96 return "Broadcom";
97 }
98
99 static void
vc4_screen_destroy(struct pipe_screen * pscreen)100 vc4_screen_destroy(struct pipe_screen *pscreen)
101 {
102 struct vc4_screen *screen = vc4_screen(pscreen);
103
104 _mesa_hash_table_destroy(screen->bo_handles, NULL);
105 vc4_bufmgr_destroy(pscreen);
106 slab_destroy_parent(&screen->transfer_pool);
107 if (screen->ro)
108 screen->ro->destroy(screen->ro);
109
110 #ifdef USE_VC4_SIMULATOR
111 vc4_simulator_destroy(screen);
112 #endif
113
114 u_transfer_helper_destroy(pscreen->transfer_helper);
115
116 close(screen->fd);
117 ralloc_free(pscreen);
118 }
119
120 static bool
vc4_has_feature(struct vc4_screen * screen,uint32_t feature)121 vc4_has_feature(struct vc4_screen *screen, uint32_t feature)
122 {
123 struct drm_vc4_get_param p = {
124 .param = feature,
125 };
126 int ret = vc4_ioctl(screen->fd, DRM_IOCTL_VC4_GET_PARAM, &p);
127
128 if (ret != 0)
129 return false;
130
131 return p.value;
132 }
133
134 static int
vc4_screen_get_param(struct pipe_screen * pscreen,enum pipe_cap param)135 vc4_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
136 {
137 struct vc4_screen *screen = vc4_screen(pscreen);
138
139 switch (param) {
140 /* Supported features (boolean caps). */
141 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
142 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
143 case PIPE_CAP_NPOT_TEXTURES:
144 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
145 case PIPE_CAP_TEXTURE_MULTISAMPLE:
146 case PIPE_CAP_TEXTURE_SWIZZLE:
147 case PIPE_CAP_TEXTURE_BARRIER:
148 case PIPE_CAP_TGSI_TEXCOORD:
149 return 1;
150
151 case PIPE_CAP_NATIVE_FENCE_FD:
152 return screen->has_syncobj;
153
154 case PIPE_CAP_TILE_RASTER_ORDER:
155 return vc4_has_feature(screen,
156 DRM_VC4_PARAM_SUPPORTS_FIXED_RCL_ORDER);
157
158 case PIPE_CAP_FS_COORD_ORIGIN_UPPER_LEFT:
159 case PIPE_CAP_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
160 case PIPE_CAP_FS_FACE_IS_INTEGER_SYSVAL:
161 return 1;
162
163 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
164 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
165 return 1;
166
167 /* Texturing. */
168 case PIPE_CAP_MAX_TEXTURE_2D_SIZE:
169 return 2048;
170 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
171 return VC4_MAX_MIP_LEVELS;
172 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
173 return 0;
174
175 case PIPE_CAP_MAX_VARYINGS:
176 return 8;
177
178 case PIPE_CAP_VENDOR_ID:
179 return 0x14E4;
180 case PIPE_CAP_ACCELERATED:
181 return 1;
182 case PIPE_CAP_VIDEO_MEMORY: {
183 uint64_t system_memory;
184
185 if (!os_get_total_physical_memory(&system_memory))
186 return 0;
187
188 return (int)(system_memory >> 20);
189 }
190 case PIPE_CAP_UMA:
191 return 1;
192
193 case PIPE_CAP_ALPHA_TEST:
194 case PIPE_CAP_VERTEX_COLOR_CLAMPED:
195 case PIPE_CAP_TWO_SIDED_COLOR:
196 case PIPE_CAP_TEXRECT:
197 case PIPE_CAP_IMAGE_STORE_FORMATTED:
198 return 0;
199
200 case PIPE_CAP_SUPPORTED_PRIM_MODES:
201 return screen->prim_types;
202
203 default:
204 return u_pipe_screen_get_param_defaults(pscreen, param);
205 }
206 }
207
208 static float
vc4_screen_get_paramf(struct pipe_screen * pscreen,enum pipe_capf param)209 vc4_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
210 {
211 switch (param) {
212 case PIPE_CAPF_MIN_LINE_WIDTH:
213 case PIPE_CAPF_MIN_LINE_WIDTH_AA:
214 case PIPE_CAPF_MIN_POINT_SIZE:
215 case PIPE_CAPF_MIN_POINT_SIZE_AA:
216 return 1;
217
218 case PIPE_CAPF_POINT_SIZE_GRANULARITY:
219 case PIPE_CAPF_LINE_WIDTH_GRANULARITY:
220 return 0.1;
221
222 case PIPE_CAPF_MAX_LINE_WIDTH:
223 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
224 return 32;
225
226 case PIPE_CAPF_MAX_POINT_SIZE:
227 case PIPE_CAPF_MAX_POINT_SIZE_AA:
228 return 512.0f;
229
230 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
231 return 0.0f;
232 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
233 return 0.0f;
234
235 case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
236 case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
237 case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
238 return 0.0f;
239 default:
240 fprintf(stderr, "unknown paramf %d\n", param);
241 return 0;
242 }
243 }
244
245 static int
vc4_screen_get_shader_param(struct pipe_screen * pscreen,enum pipe_shader_type shader,enum pipe_shader_cap param)246 vc4_screen_get_shader_param(struct pipe_screen *pscreen,
247 enum pipe_shader_type shader,
248 enum pipe_shader_cap param)
249 {
250 if (shader != PIPE_SHADER_VERTEX &&
251 shader != PIPE_SHADER_FRAGMENT) {
252 return 0;
253 }
254
255 /* this is probably not totally correct.. but it's a start: */
256 switch (param) {
257 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
258 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
259 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
260 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
261 return 16384;
262
263 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
264 return vc4_screen(pscreen)->has_control_flow;
265
266 case PIPE_SHADER_CAP_MAX_INPUTS:
267 return 8;
268 case PIPE_SHADER_CAP_MAX_OUTPUTS:
269 return shader == PIPE_SHADER_FRAGMENT ? 1 : 8;
270 case PIPE_SHADER_CAP_MAX_TEMPS:
271 return 256; /* GL_MAX_PROGRAM_TEMPORARIES_ARB */
272 case PIPE_SHADER_CAP_MAX_CONST_BUFFER0_SIZE:
273 return 16 * 1024 * sizeof(float);
274 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
275 return 1;
276 case PIPE_SHADER_CAP_CONT_SUPPORTED:
277 return 0;
278 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
279 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
280 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
281 return 0;
282 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
283 return 1;
284 case PIPE_SHADER_CAP_SUBROUTINES:
285 return 0;
286 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
287 return 0;
288 case PIPE_SHADER_CAP_INTEGERS:
289 return 1;
290 case PIPE_SHADER_CAP_INT64_ATOMICS:
291 case PIPE_SHADER_CAP_FP16:
292 case PIPE_SHADER_CAP_FP16_DERIVATIVES:
293 case PIPE_SHADER_CAP_FP16_CONST_BUFFERS:
294 case PIPE_SHADER_CAP_INT16:
295 case PIPE_SHADER_CAP_GLSL_16BIT_CONSTS:
296 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
297 return 0;
298 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
299 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
300 return VC4_MAX_TEXTURE_SAMPLERS;
301 case PIPE_SHADER_CAP_SUPPORTED_IRS:
302 return 1 << PIPE_SHADER_IR_NIR;
303 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
304 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
305 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
306 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
307 return 0;
308 default:
309 fprintf(stderr, "unknown shader param %d\n", param);
310 return 0;
311 }
312 return 0;
313 }
314
315 static bool
vc4_screen_is_format_supported(struct pipe_screen * pscreen,enum pipe_format format,enum pipe_texture_target target,unsigned sample_count,unsigned storage_sample_count,unsigned usage)316 vc4_screen_is_format_supported(struct pipe_screen *pscreen,
317 enum pipe_format format,
318 enum pipe_texture_target target,
319 unsigned sample_count,
320 unsigned storage_sample_count,
321 unsigned usage)
322 {
323 struct vc4_screen *screen = vc4_screen(pscreen);
324
325 if (MAX2(1, sample_count) != MAX2(1, storage_sample_count))
326 return false;
327
328 if (sample_count > 1 && sample_count != VC4_MAX_SAMPLES)
329 return false;
330
331 if (target >= PIPE_MAX_TEXTURE_TYPES) {
332 return false;
333 }
334
335 if (usage & PIPE_BIND_VERTEX_BUFFER) {
336 switch (format) {
337 case PIPE_FORMAT_R32G32B32A32_FLOAT:
338 case PIPE_FORMAT_R32G32B32_FLOAT:
339 case PIPE_FORMAT_R32G32_FLOAT:
340 case PIPE_FORMAT_R32_FLOAT:
341 case PIPE_FORMAT_R32G32B32A32_SNORM:
342 case PIPE_FORMAT_R32G32B32_SNORM:
343 case PIPE_FORMAT_R32G32_SNORM:
344 case PIPE_FORMAT_R32_SNORM:
345 case PIPE_FORMAT_R32G32B32A32_SSCALED:
346 case PIPE_FORMAT_R32G32B32_SSCALED:
347 case PIPE_FORMAT_R32G32_SSCALED:
348 case PIPE_FORMAT_R32_SSCALED:
349 case PIPE_FORMAT_R16G16B16A16_UNORM:
350 case PIPE_FORMAT_R16G16B16_UNORM:
351 case PIPE_FORMAT_R16G16_UNORM:
352 case PIPE_FORMAT_R16_UNORM:
353 case PIPE_FORMAT_R16G16B16A16_SNORM:
354 case PIPE_FORMAT_R16G16B16_SNORM:
355 case PIPE_FORMAT_R16G16_SNORM:
356 case PIPE_FORMAT_R16_SNORM:
357 case PIPE_FORMAT_R16G16B16A16_USCALED:
358 case PIPE_FORMAT_R16G16B16_USCALED:
359 case PIPE_FORMAT_R16G16_USCALED:
360 case PIPE_FORMAT_R16_USCALED:
361 case PIPE_FORMAT_R16G16B16A16_SSCALED:
362 case PIPE_FORMAT_R16G16B16_SSCALED:
363 case PIPE_FORMAT_R16G16_SSCALED:
364 case PIPE_FORMAT_R16_SSCALED:
365 case PIPE_FORMAT_R8G8B8A8_UNORM:
366 case PIPE_FORMAT_R8G8B8_UNORM:
367 case PIPE_FORMAT_R8G8_UNORM:
368 case PIPE_FORMAT_R8_UNORM:
369 case PIPE_FORMAT_R8G8B8A8_SNORM:
370 case PIPE_FORMAT_R8G8B8_SNORM:
371 case PIPE_FORMAT_R8G8_SNORM:
372 case PIPE_FORMAT_R8_SNORM:
373 case PIPE_FORMAT_R8G8B8A8_USCALED:
374 case PIPE_FORMAT_R8G8B8_USCALED:
375 case PIPE_FORMAT_R8G8_USCALED:
376 case PIPE_FORMAT_R8_USCALED:
377 case PIPE_FORMAT_R8G8B8A8_SSCALED:
378 case PIPE_FORMAT_R8G8B8_SSCALED:
379 case PIPE_FORMAT_R8G8_SSCALED:
380 case PIPE_FORMAT_R8_SSCALED:
381 break;
382 default:
383 return false;
384 }
385 }
386
387 if ((usage & PIPE_BIND_RENDER_TARGET) &&
388 !vc4_rt_format_supported(format)) {
389 return false;
390 }
391
392 if ((usage & PIPE_BIND_SAMPLER_VIEW) &&
393 (!vc4_tex_format_supported(format) ||
394 (format == PIPE_FORMAT_ETC1_RGB8 && !screen->has_etc1))) {
395 return false;
396 }
397
398 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
399 format != PIPE_FORMAT_S8_UINT_Z24_UNORM &&
400 format != PIPE_FORMAT_X8Z24_UNORM) {
401 return false;
402 }
403
404 if ((usage & PIPE_BIND_INDEX_BUFFER) &&
405 format != PIPE_FORMAT_R8_UINT &&
406 format != PIPE_FORMAT_R16_UINT) {
407 return false;
408 }
409
410 return true;
411 }
412
vc4_get_modifiers(struct pipe_screen * pscreen,int * num)413 static const uint64_t *vc4_get_modifiers(struct pipe_screen *pscreen, int *num)
414 {
415 struct vc4_screen *screen = vc4_screen(pscreen);
416 static const uint64_t all_modifiers[] = {
417 DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED,
418 DRM_FORMAT_MOD_LINEAR,
419 };
420 int m;
421
422 /* We support both modifiers (tiled and linear) for all sampler
423 * formats, but if we don't have the DRM_VC4_GET_TILING ioctl
424 * we shouldn't advertise the tiled formats.
425 */
426 if (screen->has_tiling_ioctl) {
427 m = 0;
428 *num = 2;
429 } else{
430 m = 1;
431 *num = 1;
432 }
433
434 return &all_modifiers[m];
435 }
436
437 static void
vc4_screen_query_dmabuf_modifiers(struct pipe_screen * pscreen,enum pipe_format format,int max,uint64_t * modifiers,unsigned int * external_only,int * count)438 vc4_screen_query_dmabuf_modifiers(struct pipe_screen *pscreen,
439 enum pipe_format format, int max,
440 uint64_t *modifiers,
441 unsigned int *external_only,
442 int *count)
443 {
444 const uint64_t *available_modifiers;
445 int i;
446 bool tex_will_lower;
447 int num_modifiers;
448
449 available_modifiers = vc4_get_modifiers(pscreen, &num_modifiers);
450
451 if (!modifiers) {
452 *count = num_modifiers;
453 return;
454 }
455
456 *count = MIN2(max, num_modifiers);
457 tex_will_lower = !vc4_tex_format_supported(format);
458 for (i = 0; i < *count; i++) {
459 modifiers[i] = available_modifiers[i];
460 if (external_only)
461 external_only[i] = tex_will_lower;
462 }
463 }
464
465 static bool
vc4_screen_is_dmabuf_modifier_supported(struct pipe_screen * pscreen,uint64_t modifier,enum pipe_format format,bool * external_only)466 vc4_screen_is_dmabuf_modifier_supported(struct pipe_screen *pscreen,
467 uint64_t modifier,
468 enum pipe_format format,
469 bool *external_only)
470 {
471 const uint64_t *available_modifiers;
472 int i, num_modifiers;
473
474 available_modifiers = vc4_get_modifiers(pscreen, &num_modifiers);
475
476 for (i = 0; i < num_modifiers; i++) {
477 if (modifier == available_modifiers[i]) {
478 if (external_only)
479 *external_only = !vc4_tex_format_supported(format);
480
481 return true;
482 }
483 }
484
485 return false;
486 }
487
488 static bool
vc4_get_chip_info(struct vc4_screen * screen)489 vc4_get_chip_info(struct vc4_screen *screen)
490 {
491 struct drm_vc4_get_param ident0 = {
492 .param = DRM_VC4_PARAM_V3D_IDENT0,
493 };
494 struct drm_vc4_get_param ident1 = {
495 .param = DRM_VC4_PARAM_V3D_IDENT1,
496 };
497 int ret;
498
499 ret = vc4_ioctl(screen->fd, DRM_IOCTL_VC4_GET_PARAM, &ident0);
500 if (ret != 0) {
501 if (errno == EINVAL) {
502 /* Backwards compatibility with 2835 kernels which
503 * only do V3D 2.1.
504 */
505 screen->v3d_ver = 21;
506 return true;
507 } else {
508 fprintf(stderr, "Couldn't get V3D IDENT0: %s\n",
509 strerror(errno));
510 return false;
511 }
512 }
513 ret = vc4_ioctl(screen->fd, DRM_IOCTL_VC4_GET_PARAM, &ident1);
514 if (ret != 0) {
515 fprintf(stderr, "Couldn't get V3D IDENT1: %s\n",
516 strerror(errno));
517 return false;
518 }
519
520 uint32_t major = (ident0.value >> 24) & 0xff;
521 uint32_t minor = (ident1.value >> 0) & 0xf;
522 screen->v3d_ver = major * 10 + minor;
523
524 if (screen->v3d_ver != 21 && screen->v3d_ver != 26) {
525 fprintf(stderr,
526 "V3D %d.%d not supported by this version of Mesa.\n",
527 screen->v3d_ver / 10,
528 screen->v3d_ver % 10);
529 return false;
530 }
531
532 return true;
533 }
534
535 static int
vc4_screen_get_fd(struct pipe_screen * pscreen)536 vc4_screen_get_fd(struct pipe_screen *pscreen)
537 {
538 struct vc4_screen *screen = vc4_screen(pscreen);
539
540 return screen->fd;
541 }
542
543 struct pipe_screen *
vc4_screen_create(int fd,const struct pipe_screen_config * config,struct renderonly * ro)544 vc4_screen_create(int fd, const struct pipe_screen_config *config,
545 struct renderonly *ro)
546 {
547 struct vc4_screen *screen = rzalloc(NULL, struct vc4_screen);
548 uint64_t syncobj_cap = 0;
549 struct pipe_screen *pscreen;
550 int err;
551
552 pscreen = &screen->base;
553
554 pscreen->destroy = vc4_screen_destroy;
555 pscreen->get_screen_fd = vc4_screen_get_fd;
556 pscreen->get_param = vc4_screen_get_param;
557 pscreen->get_paramf = vc4_screen_get_paramf;
558 pscreen->get_shader_param = vc4_screen_get_shader_param;
559 pscreen->context_create = vc4_context_create;
560 pscreen->is_format_supported = vc4_screen_is_format_supported;
561
562 screen->fd = fd;
563 screen->ro = ro;
564
565 list_inithead(&screen->bo_cache.time_list);
566 (void) mtx_init(&screen->bo_handles_mutex, mtx_plain);
567 screen->bo_handles = util_hash_table_create_ptr_keys();
568
569 screen->has_control_flow =
570 vc4_has_feature(screen, DRM_VC4_PARAM_SUPPORTS_BRANCHES);
571 screen->has_etc1 =
572 vc4_has_feature(screen, DRM_VC4_PARAM_SUPPORTS_ETC1);
573 screen->has_threaded_fs =
574 vc4_has_feature(screen, DRM_VC4_PARAM_SUPPORTS_THREADED_FS);
575 screen->has_madvise =
576 vc4_has_feature(screen, DRM_VC4_PARAM_SUPPORTS_MADVISE);
577 screen->has_perfmon_ioctl =
578 vc4_has_feature(screen, DRM_VC4_PARAM_SUPPORTS_PERFMON);
579
580 err = drmGetCap(fd, DRM_CAP_SYNCOBJ, &syncobj_cap);
581 if (err == 0 && syncobj_cap)
582 screen->has_syncobj = true;
583
584 if (!vc4_get_chip_info(screen))
585 goto fail;
586
587 slab_create_parent(&screen->transfer_pool, sizeof(struct vc4_transfer), 16);
588
589 vc4_fence_screen_init(screen);
590
591 vc4_mesa_debug = debug_get_option_vc4_debug();
592
593 #ifdef USE_VC4_SIMULATOR
594 vc4_simulator_init(screen);
595 #endif
596
597 vc4_resource_screen_init(pscreen);
598
599 pscreen->get_name = vc4_screen_get_name;
600 pscreen->get_vendor = vc4_screen_get_vendor;
601 pscreen->get_device_vendor = vc4_screen_get_vendor;
602 pscreen->get_compiler_options = vc4_screen_get_compiler_options;
603 pscreen->query_dmabuf_modifiers = vc4_screen_query_dmabuf_modifiers;
604 pscreen->is_dmabuf_modifier_supported = vc4_screen_is_dmabuf_modifier_supported;
605
606 if (screen->has_perfmon_ioctl) {
607 pscreen->get_driver_query_group_info = vc4_get_driver_query_group_info;
608 pscreen->get_driver_query_info = vc4_get_driver_query_info;
609 }
610
611 /* Generate the bitmask of supported draw primitives. */
612 screen->prim_types = BITFIELD_BIT(MESA_PRIM_POINTS) |
613 BITFIELD_BIT(MESA_PRIM_LINES) |
614 BITFIELD_BIT(MESA_PRIM_LINE_LOOP) |
615 BITFIELD_BIT(MESA_PRIM_LINE_STRIP) |
616 BITFIELD_BIT(MESA_PRIM_TRIANGLES) |
617 BITFIELD_BIT(MESA_PRIM_TRIANGLE_STRIP) |
618 BITFIELD_BIT(MESA_PRIM_TRIANGLE_FAN);
619
620
621 return pscreen;
622
623 fail:
624 close(fd);
625 ralloc_free(pscreen);
626 return NULL;
627 }
628