1 /************************************************************************** 2 * 3 * Copyright 2013 Advanced Micro Devices, Inc. 4 * 5 * SPDX-License-Identifier: MIT 6 * 7 **************************************************************************/ 8 9 #ifndef RADEON_VCE_H 10 #define RADEON_VCE_H 11 12 #include "radeon_video.h" 13 #include "util/list.h" 14 15 #define RVCE_CS(value) (enc->cs.current.buf[enc->cs.current.cdw++] = (value)) 16 #define RVCE_BEGIN(cmd) \ 17 { \ 18 uint32_t *begin = &enc->cs.current.buf[enc->cs.current.cdw++]; \ 19 RVCE_CS(cmd) 20 #define RVCE_READ(buf, domain, off) \ 21 si_vce_add_buffer(enc, (buf), RADEON_USAGE_READ, (domain), (off)) 22 #define RVCE_WRITE(buf, domain, off) \ 23 si_vce_add_buffer(enc, (buf), RADEON_USAGE_WRITE, (domain), (off)) 24 #define RVCE_READWRITE(buf, domain, off) \ 25 si_vce_add_buffer(enc, (buf), RADEON_USAGE_READWRITE, (domain), (off)) 26 #define RVCE_END() \ 27 *begin = (&enc->cs.current.buf[enc->cs.current.cdw] - begin) * 4; \ 28 } 29 30 #define RVCE_MAX_BITSTREAM_OUTPUT_ROW_SIZE (4096 * 16 * 2.5) 31 #define RVCE_MAX_AUX_BUFFER_NUM 4 32 33 struct si_screen; 34 35 /* driver dependent callback */ 36 typedef void (*rvce_get_buffer)(struct pipe_resource *resource, struct pb_buffer_lean **handle, 37 struct radeon_surf **surface); 38 39 /* Coded picture buffer slot */ 40 struct rvce_cpb_slot { 41 struct list_head list; 42 43 unsigned index; 44 enum pipe_h2645_enc_picture_type picture_type; 45 unsigned frame_num; 46 unsigned pic_order_cnt; 47 }; 48 49 struct rvce_rate_control { 50 uint32_t rc_method; 51 uint32_t target_bitrate; 52 uint32_t peak_bitrate; 53 uint32_t frame_rate_num; 54 uint32_t gop_size; 55 uint32_t quant_i_frames; 56 uint32_t quant_p_frames; 57 uint32_t quant_b_frames; 58 uint32_t vbv_buffer_size; 59 uint32_t frame_rate_den; 60 uint32_t vbv_buf_lv; 61 uint32_t max_au_size; 62 uint32_t qp_initial_mode; 63 uint32_t target_bits_picture; 64 uint32_t peak_bits_picture_integer; 65 uint32_t peak_bits_picture_fraction; 66 uint32_t min_qp; 67 uint32_t max_qp; 68 uint32_t skip_frame_enable; 69 uint32_t fill_data_enable; 70 uint32_t enforce_hrd; 71 uint32_t b_pics_delta_qp; 72 uint32_t ref_b_pics_delta_qp; 73 uint32_t rc_reinit_disable; 74 uint32_t enc_lcvbr_init_qp_flag; 75 uint32_t lcvbrsatd_based_nonlinear_bit_budget_flag; 76 }; 77 78 struct rvce_motion_estimation { 79 uint32_t enc_ime_decimation_search; 80 uint32_t motion_est_half_pixel; 81 uint32_t motion_est_quarter_pixel; 82 uint32_t disable_favor_pmv_point; 83 uint32_t force_zero_point_center; 84 uint32_t lsmvert; 85 uint32_t enc_search_range_x; 86 uint32_t enc_search_range_y; 87 uint32_t enc_search1_range_x; 88 uint32_t enc_search1_range_y; 89 uint32_t disable_16x16_frame1; 90 uint32_t disable_satd; 91 uint32_t enable_amd; 92 uint32_t enc_disable_sub_mode; 93 uint32_t enc_ime_skip_x; 94 uint32_t enc_ime_skip_y; 95 uint32_t enc_en_ime_overw_dis_subm; 96 uint32_t enc_ime_overw_dis_subm_no; 97 uint32_t enc_ime2_search_range_x; 98 uint32_t enc_ime2_search_range_y; 99 uint32_t parallel_mode_speedup_enable; 100 uint32_t fme0_enc_disable_sub_mode; 101 uint32_t fme1_enc_disable_sub_mode; 102 uint32_t ime_sw_speedup_enable; 103 }; 104 105 struct rvce_pic_control { 106 uint32_t enc_use_constrained_intra_pred; 107 uint32_t enc_cabac_enable; 108 uint32_t enc_cabac_idc; 109 uint32_t enc_loop_filter_disable; 110 int32_t enc_lf_beta_offset; 111 int32_t enc_lf_alpha_c0_offset; 112 uint32_t enc_crop_left_offset; 113 uint32_t enc_crop_right_offset; 114 uint32_t enc_crop_top_offset; 115 uint32_t enc_crop_bottom_offset; 116 uint32_t enc_num_mbs_per_slice; 117 uint32_t enc_intra_refresh_num_mbs_per_slot; 118 uint32_t enc_force_intra_refresh; 119 uint32_t enc_force_imb_period; 120 uint32_t enc_pic_order_cnt_type; 121 uint32_t log2_max_pic_order_cnt_lsb_minus4; 122 uint32_t enc_sps_id; 123 uint32_t enc_pps_id; 124 uint32_t enc_constraint_set_flags; 125 uint32_t enc_b_pic_pattern; 126 uint32_t weight_pred_mode_b_picture; 127 uint32_t enc_number_of_reference_frames; 128 uint32_t enc_max_num_ref_frames; 129 uint32_t enc_num_default_active_ref_l0; 130 uint32_t enc_num_default_active_ref_l1; 131 uint32_t enc_slice_mode; 132 uint32_t enc_max_slice_size; 133 }; 134 135 struct rvce_task_info { 136 uint32_t offset_of_next_task_info; 137 uint32_t task_operation; 138 uint32_t reference_picture_dependency; 139 uint32_t collocate_flag_dependency; 140 uint32_t feedback_index; 141 uint32_t video_bitstream_ring_index; 142 }; 143 144 struct rvce_feedback_buf_pkg { 145 uint32_t feedback_ring_address_hi; 146 uint32_t feedback_ring_address_lo; 147 uint32_t feedback_ring_size; 148 }; 149 150 struct rvce_rdo { 151 uint32_t enc_disable_tbe_pred_i_frame; 152 uint32_t enc_disable_tbe_pred_p_frame; 153 uint32_t use_fme_interpol_y; 154 uint32_t use_fme_interpol_uv; 155 uint32_t use_fme_intrapol_y; 156 uint32_t use_fme_intrapol_uv; 157 uint32_t use_fme_interpol_y_1; 158 uint32_t use_fme_interpol_uv_1; 159 uint32_t use_fme_intrapol_y_1; 160 uint32_t use_fme_intrapol_uv_1; 161 uint32_t enc_16x16_cost_adj; 162 uint32_t enc_skip_cost_adj; 163 uint32_t enc_force_16x16_skip; 164 uint32_t enc_disable_threshold_calc_a; 165 uint32_t enc_luma_coeff_cost; 166 uint32_t enc_luma_mb_coeff_cost; 167 uint32_t enc_chroma_coeff_cost; 168 }; 169 170 struct rvce_vui { 171 uint32_t aspect_ratio_info_present_flag; 172 uint32_t aspect_ratio_idc; 173 uint32_t sar_width; 174 uint32_t sar_height; 175 uint32_t overscan_info_present_flag; 176 uint32_t overscan_Approp_flag; 177 uint32_t video_signal_type_present_flag; 178 uint32_t video_format; 179 uint32_t video_full_range_flag; 180 uint32_t color_description_present_flag; 181 uint32_t color_prim; 182 uint32_t transfer_char; 183 uint32_t matrix_coef; 184 uint32_t chroma_loc_info_present_flag; 185 uint32_t chroma_loc_top; 186 uint32_t chroma_loc_bottom; 187 uint32_t timing_info_present_flag; 188 uint32_t num_units_in_tick; 189 uint32_t time_scale; 190 uint32_t fixed_frame_rate_flag; 191 uint32_t nal_hrd_parameters_present_flag; 192 uint32_t cpb_cnt_minus1; 193 uint32_t bit_rate_scale; 194 uint32_t cpb_size_scale; 195 uint32_t bit_rate_value_minus; 196 uint32_t cpb_size_value_minus; 197 uint32_t cbr_flag; 198 uint32_t initial_cpb_removal_delay_length_minus1; 199 uint32_t cpb_removal_delay_length_minus1; 200 uint32_t dpb_output_delay_length_minus1; 201 uint32_t time_offset_length; 202 uint32_t low_delay_hrd_flag; 203 uint32_t pic_struct_present_flag; 204 uint32_t bitstream_restriction_present_flag; 205 uint32_t motion_vectors_over_pic_boundaries_flag; 206 uint32_t max_bytes_per_pic_denom; 207 uint32_t max_bits_per_mb_denom; 208 uint32_t log2_max_mv_length_hori; 209 uint32_t log2_max_mv_length_vert; 210 uint32_t num_reorder_frames; 211 uint32_t max_dec_frame_buffering; 212 }; 213 214 struct rvce_enc_operation { 215 uint32_t insert_headers; 216 uint32_t picture_structure; 217 uint32_t allowed_max_bitstream_size; 218 uint32_t force_refresh_map; 219 uint32_t insert_aud; 220 uint32_t end_of_sequence; 221 uint32_t end_of_stream; 222 uint32_t input_picture_luma_address_hi; 223 uint32_t input_picture_luma_address_lo; 224 uint32_t input_picture_chroma_address_hi; 225 uint32_t input_picture_chroma_address_lo; 226 uint32_t enc_input_frame_y_pitch; 227 uint32_t enc_input_pic_luma_pitch; 228 uint32_t enc_input_pic_chroma_pitch; 229 ; 230 uint32_t enc_input_pic_addr_array; 231 uint32_t enc_input_pic_addr_array_disable2pipe_disablemboffload; 232 uint32_t enc_input_pic_tile_config; 233 uint32_t enc_pic_type; 234 uint32_t enc_idr_flag; 235 uint32_t enc_idr_pic_id; 236 uint32_t enc_mgs_key_pic; 237 uint32_t enc_reference_flag; 238 uint32_t enc_temporal_layer_index; 239 uint32_t num_ref_idx_active_override_flag; 240 uint32_t num_ref_idx_l0_active_minus1; 241 uint32_t num_ref_idx_l1_active_minus1; 242 uint32_t enc_ref_list_modification_op; 243 uint32_t enc_ref_list_modification_num; 244 uint32_t enc_decoded_picture_marking_op; 245 uint32_t enc_decoded_picture_marking_num; 246 uint32_t enc_decoded_picture_marking_idx; 247 uint32_t enc_decoded_ref_base_picture_marking_op; 248 uint32_t enc_decoded_ref_base_picture_marking_num; 249 uint32_t l0_picture_structure; 250 uint32_t l0_enc_pic_type; 251 uint32_t l0_frame_number; 252 uint32_t l0_picture_order_count; 253 uint32_t l0_luma_offset; 254 uint32_t l0_chroma_offset; 255 uint32_t l1_picture_structure; 256 uint32_t l1_enc_pic_type; 257 uint32_t l1_frame_number; 258 uint32_t l1_picture_order_count; 259 uint32_t l1_luma_offset; 260 uint32_t l1_chroma_offset; 261 uint32_t enc_reconstructed_luma_offset; 262 uint32_t enc_reconstructed_chroma_offset; 263 ; 264 uint32_t enc_coloc_buffer_offset; 265 uint32_t enc_reconstructed_ref_base_picture_luma_offset; 266 uint32_t enc_reconstructed_ref_base_picture_chroma_offset; 267 uint32_t enc_reference_ref_base_picture_luma_offset; 268 uint32_t enc_reference_ref_base_picture_chroma_offset; 269 uint32_t picture_count; 270 uint32_t frame_number; 271 uint32_t picture_order_count; 272 uint32_t num_i_pic_remain_in_rcgop; 273 uint32_t num_p_pic_remain_in_rcgop; 274 uint32_t num_b_pic_remain_in_rcgop; 275 uint32_t num_ir_pic_remain_in_rcgop; 276 uint32_t enable_intra_refresh; 277 uint32_t aq_variance_en; 278 uint32_t aq_block_size; 279 uint32_t aq_mb_variance_sel; 280 uint32_t aq_frame_variance_sel; 281 uint32_t aq_param_a; 282 uint32_t aq_param_b; 283 uint32_t aq_param_c; 284 uint32_t aq_param_d; 285 uint32_t aq_param_e; 286 uint32_t context_in_sfb; 287 }; 288 289 struct rvce_enc_create { 290 uint32_t enc_use_circular_buffer; 291 uint32_t enc_profile; 292 uint32_t enc_level; 293 uint32_t enc_pic_struct_restriction; 294 uint32_t enc_image_width; 295 uint32_t enc_image_height; 296 uint32_t enc_ref_pic_luma_pitch; 297 uint32_t enc_ref_pic_chroma_pitch; 298 uint32_t enc_ref_y_height_in_qw; 299 uint32_t enc_ref_pic_addr_array_enc_pic_struct_restriction_disable_rdo; 300 uint32_t enc_pre_encode_context_buffer_offset; 301 uint32_t enc_pre_encode_input_luma_buffer_offset; 302 uint32_t enc_pre_encode_input_chroma_buffer_offset; 303 uint32_t enc_pre_encode_mode_chromaflag_vbaqmode_scenechangesensitivity; 304 }; 305 306 struct rvce_config_ext { 307 uint32_t enc_enable_perf_logging; 308 }; 309 310 struct rvce_h264_enc_pic { 311 struct rvce_rate_control rc; 312 struct rvce_motion_estimation me; 313 struct rvce_pic_control pc; 314 struct rvce_task_info ti; 315 struct rvce_feedback_buf_pkg fb; 316 struct rvce_rdo rdo; 317 struct rvce_vui vui; 318 struct rvce_enc_operation eo; 319 struct rvce_enc_create ec; 320 struct rvce_config_ext ce; 321 322 unsigned quant_i_frames; 323 unsigned quant_p_frames; 324 unsigned quant_b_frames; 325 326 enum pipe_h2645_enc_picture_type picture_type; 327 unsigned frame_num; 328 unsigned frame_num_cnt; 329 unsigned p_remain; 330 unsigned i_remain; 331 unsigned idr_pic_id; 332 unsigned gop_cnt; 333 unsigned gop_size; 334 unsigned pic_order_cnt; 335 unsigned ref_idx_l0; 336 unsigned ref_idx_l1; 337 unsigned addrmode_arraymode_disrdo_distwoinstants; 338 339 bool not_referenced; 340 bool is_idr; 341 bool has_ref_pic_list; 342 bool enable_vui; 343 unsigned int ref_pic_list_0[32]; 344 unsigned int ref_pic_list_1[32]; 345 unsigned int frame_idx[32]; 346 }; 347 348 /* VCE encoder representation */ 349 struct rvce_encoder { 350 struct pipe_video_codec base; 351 352 /* version specific packets */ 353 void (*session)(struct rvce_encoder *enc); 354 void (*create)(struct rvce_encoder *enc); 355 void (*feedback)(struct rvce_encoder *enc); 356 void (*rate_control)(struct rvce_encoder *enc); 357 void (*config_extension)(struct rvce_encoder *enc); 358 void (*pic_control)(struct rvce_encoder *enc); 359 void (*motion_estimation)(struct rvce_encoder *enc); 360 void (*rdo)(struct rvce_encoder *enc); 361 void (*vui)(struct rvce_encoder *enc); 362 void (*config)(struct rvce_encoder *enc); 363 void (*encode)(struct rvce_encoder *enc); 364 void (*destroy)(struct rvce_encoder *enc); 365 void (*task_info)(struct rvce_encoder *enc, uint32_t op, uint32_t dep, uint32_t fb_idx, 366 uint32_t ring_idx); 367 void (*si_get_pic_param)(struct rvce_encoder *enc, struct pipe_h264_enc_picture_desc *pic); 368 369 unsigned stream_handle; 370 371 struct pipe_screen *screen; 372 struct radeon_winsys *ws; 373 struct radeon_cmdbuf cs; 374 375 rvce_get_buffer get_buffer; 376 377 struct pb_buffer_lean *handle; 378 struct radeon_surf *luma; 379 struct radeon_surf *chroma; 380 381 struct pb_buffer_lean *bs_handle; 382 unsigned bs_size; 383 384 struct rvce_cpb_slot *cpb_array; 385 struct list_head cpb_slots; 386 unsigned cpb_num; 387 388 struct rvid_buffer *fb; 389 struct rvid_buffer cpb; 390 struct pipe_h264_enc_picture_desc pic; 391 struct rvce_h264_enc_pic enc_pic; 392 393 unsigned task_info_idx; 394 unsigned bs_idx; 395 396 bool use_vm; 397 bool use_vui; 398 bool dual_pipe; 399 bool dual_inst; 400 }; 401 402 /* CPB handling functions */ 403 struct rvce_cpb_slot *si_current_slot(struct rvce_encoder *enc); 404 struct rvce_cpb_slot *si_l0_slot(struct rvce_encoder *enc); 405 struct rvce_cpb_slot *si_l1_slot(struct rvce_encoder *enc); 406 void si_vce_frame_offset(struct rvce_encoder *enc, struct rvce_cpb_slot *slot, signed *luma_offset, 407 signed *chroma_offset); 408 409 struct pipe_video_codec *si_vce_create_encoder(struct pipe_context *context, 410 const struct pipe_video_codec *templat, 411 struct radeon_winsys *ws, 412 rvce_get_buffer get_buffer); 413 414 bool si_vce_is_fw_version_supported(struct si_screen *sscreen); 415 416 void si_vce_add_buffer(struct rvce_encoder *enc, struct pb_buffer_lean *buf, unsigned usage, 417 enum radeon_bo_domain domain, signed offset); 418 419 /* init vce fw 40.2.2 specific callbacks */ 420 void si_vce_40_2_2_init(struct rvce_encoder *enc); 421 422 /* init vce fw 50 specific callbacks */ 423 void si_vce_50_init(struct rvce_encoder *enc); 424 425 /* init vce fw 52 specific callbacks */ 426 void si_vce_52_init(struct rvce_encoder *enc); 427 428 /* get parameters for vce 40.2.2 */ 429 void si_vce_40_2_2_get_param(struct rvce_encoder *enc, struct pipe_h264_enc_picture_desc *pic); 430 431 /* get parameters for vce 50 */ 432 void si_vce_50_get_param(struct rvce_encoder *enc, struct pipe_h264_enc_picture_desc *pic); 433 434 /* get parameters for vce 52 */ 435 void si_vce_52_get_param(struct rvce_encoder *enc, struct pipe_h264_enc_picture_desc *pic); 436 437 #endif 438