1 /* 2 * Copyright 2013 Advanced Micro Devices, Inc. 3 * Authors: 4 * Christian König <[email protected]> 5 * SPDX-License-Identifier: MIT 6 */ 7 8 #ifndef RADEON_VCE_H 9 #define RADEON_VCE_H 10 11 #include "util/list.h" 12 13 #define RVCE_CS(value) (enc->cs.current.buf[enc->cs.current.cdw++] = (value)) 14 #define RVCE_BEGIN(cmd) { \ 15 uint32_t *begin = &enc->cs.current.buf[enc->cs.current.cdw++]; \ 16 RVCE_CS(cmd) 17 #define RVCE_READ(buf, domain, off) rvce_add_buffer(enc, (buf), RADEON_USAGE_READ, (domain), (off)) 18 #define RVCE_WRITE(buf, domain, off) rvce_add_buffer(enc, (buf), RADEON_USAGE_WRITE, (domain), (off)) 19 #define RVCE_READWRITE(buf, domain, off) rvce_add_buffer(enc, (buf), RADEON_USAGE_READWRITE, (domain), (off)) 20 #define RVCE_END() *begin = (&enc->cs.current.buf[enc->cs.current.cdw] - begin) * 4; } 21 22 #define RVCE_MAX_BITSTREAM_OUTPUT_ROW_SIZE (4096 * 16 * 2.5) 23 #define RVCE_MAX_AUX_BUFFER_NUM 4 24 25 struct r600_common_screen; 26 27 /* driver dependent callback */ 28 typedef void (*rvce_get_buffer)(struct pipe_resource *resource, 29 struct pb_buffer_lean **handle, 30 struct radeon_surf **surface); 31 32 /* Coded picture buffer slot */ 33 struct rvce_cpb_slot { 34 struct list_head list; 35 36 unsigned index; 37 enum pipe_h2645_enc_picture_type picture_type; 38 unsigned frame_num; 39 unsigned pic_order_cnt; 40 }; 41 42 struct rvce_rate_control { 43 uint32_t rc_method; 44 uint32_t target_bitrate; 45 uint32_t peak_bitrate; 46 uint32_t frame_rate_num; 47 uint32_t gop_size; 48 uint32_t quant_i_frames; 49 uint32_t quant_p_frames; 50 uint32_t quant_b_frames; 51 uint32_t vbv_buffer_size; 52 uint32_t frame_rate_den; 53 uint32_t vbv_buf_lv; 54 uint32_t max_au_size; 55 uint32_t qp_initial_mode; 56 uint32_t target_bits_picture; 57 uint32_t peak_bits_picture_integer; 58 uint32_t peak_bits_picture_fraction; 59 uint32_t min_qp; 60 uint32_t max_qp; 61 uint32_t skip_frame_enable; 62 uint32_t fill_data_enable; 63 uint32_t enforce_hrd; 64 uint32_t b_pics_delta_qp; 65 uint32_t ref_b_pics_delta_qp; 66 uint32_t rc_reinit_disable; 67 uint32_t enc_lcvbr_init_qp_flag; 68 uint32_t lcvbrsatd_based_nonlinear_bit_budget_flag; 69 }; 70 71 struct rvce_motion_estimation { 72 uint32_t enc_ime_decimation_search; 73 uint32_t motion_est_half_pixel; 74 uint32_t motion_est_quarter_pixel; 75 uint32_t disable_favor_pmv_point; 76 uint32_t force_zero_point_center; 77 uint32_t lsmvert; 78 uint32_t enc_search_range_x; 79 uint32_t enc_search_range_y; 80 uint32_t enc_search1_range_x; 81 uint32_t enc_search1_range_y; 82 uint32_t disable_16x16_frame1; 83 uint32_t disable_satd; 84 uint32_t enable_amd; 85 uint32_t enc_disable_sub_mode; 86 uint32_t enc_ime_skip_x; 87 uint32_t enc_ime_skip_y; 88 uint32_t enc_en_ime_overw_dis_subm; 89 uint32_t enc_ime_overw_dis_subm_no; 90 uint32_t enc_ime2_search_range_x; 91 uint32_t enc_ime2_search_range_y; 92 uint32_t parallel_mode_speedup_enable; 93 uint32_t fme0_enc_disable_sub_mode; 94 uint32_t fme1_enc_disable_sub_mode; 95 uint32_t ime_sw_speedup_enable; 96 }; 97 98 struct rvce_pic_control { 99 uint32_t enc_use_constrained_intra_pred; 100 uint32_t enc_cabac_enable; 101 uint32_t enc_cabac_idc; 102 uint32_t enc_loop_filter_disable; 103 int32_t enc_lf_beta_offset; 104 int32_t enc_lf_alpha_c0_offset; 105 uint32_t enc_crop_left_offset; 106 uint32_t enc_crop_right_offset; 107 uint32_t enc_crop_top_offset; 108 uint32_t enc_crop_bottom_offset; 109 uint32_t enc_num_mbs_per_slice; 110 uint32_t enc_intra_refresh_num_mbs_per_slot; 111 uint32_t enc_force_intra_refresh; 112 uint32_t enc_force_imb_period; 113 uint32_t enc_pic_order_cnt_type; 114 uint32_t log2_max_pic_order_cnt_lsb_minus4; 115 uint32_t enc_sps_id; 116 uint32_t enc_pps_id; 117 uint32_t enc_constraint_set_flags; 118 uint32_t enc_b_pic_pattern; 119 uint32_t weight_pred_mode_b_picture; 120 uint32_t enc_number_of_reference_frames; 121 uint32_t enc_max_num_ref_frames; 122 uint32_t enc_num_default_active_ref_l0; 123 uint32_t enc_num_default_active_ref_l1; 124 uint32_t enc_slice_mode; 125 uint32_t enc_max_slice_size; 126 }; 127 128 struct rvce_task_info { 129 uint32_t offset_of_next_task_info; 130 uint32_t task_operation; 131 uint32_t reference_picture_dependency; 132 uint32_t collocate_flag_dependency; 133 uint32_t feedback_index; 134 uint32_t video_bitstream_ring_index; 135 }; 136 137 struct rvce_feedback_buf_pkg { 138 uint32_t feedback_ring_address_hi; 139 uint32_t feedback_ring_address_lo; 140 uint32_t feedback_ring_size; 141 }; 142 143 struct rvce_rdo { 144 uint32_t enc_disable_tbe_pred_i_frame; 145 uint32_t enc_disable_tbe_pred_p_frame; 146 uint32_t use_fme_interpol_y; 147 uint32_t use_fme_interpol_uv; 148 uint32_t use_fme_intrapol_y; 149 uint32_t use_fme_intrapol_uv; 150 uint32_t use_fme_interpol_y_1; 151 uint32_t use_fme_interpol_uv_1; 152 uint32_t use_fme_intrapol_y_1; 153 uint32_t use_fme_intrapol_uv_1; 154 uint32_t enc_16x16_cost_adj; 155 uint32_t enc_skip_cost_adj; 156 uint32_t enc_force_16x16_skip; 157 uint32_t enc_disable_threshold_calc_a; 158 uint32_t enc_luma_coeff_cost; 159 uint32_t enc_luma_mb_coeff_cost; 160 uint32_t enc_chroma_coeff_cost; 161 }; 162 163 struct rvce_vui { 164 uint32_t aspect_ratio_info_present_flag; 165 uint32_t aspect_ratio_idc; 166 uint32_t sar_width; 167 uint32_t sar_height; 168 uint32_t overscan_info_present_flag; 169 uint32_t overscan_Approp_flag; 170 uint32_t video_signal_type_present_flag; 171 uint32_t video_format; 172 uint32_t video_full_range_flag; 173 uint32_t color_description_present_flag; 174 uint32_t color_prim; 175 uint32_t transfer_char; 176 uint32_t matrix_coef; 177 uint32_t chroma_loc_info_present_flag; 178 uint32_t chroma_loc_top; 179 uint32_t chroma_loc_bottom; 180 uint32_t timing_info_present_flag; 181 uint32_t num_units_in_tick; 182 uint32_t time_scale; 183 uint32_t fixed_frame_rate_flag; 184 uint32_t nal_hrd_parameters_present_flag; 185 uint32_t cpb_cnt_minus1; 186 uint32_t bit_rate_scale; 187 uint32_t cpb_size_scale; 188 uint32_t bit_rate_value_minus; 189 uint32_t cpb_size_value_minus; 190 uint32_t cbr_flag; 191 uint32_t initial_cpb_removal_delay_length_minus1; 192 uint32_t cpb_removal_delay_length_minus1; 193 uint32_t dpb_output_delay_length_minus1; 194 uint32_t time_offset_length; 195 uint32_t low_delay_hrd_flag; 196 uint32_t pic_struct_present_flag; 197 uint32_t bitstream_restriction_present_flag; 198 uint32_t motion_vectors_over_pic_boundaries_flag; 199 uint32_t max_bytes_per_pic_denom; 200 uint32_t max_bits_per_mb_denom; 201 uint32_t log2_max_mv_length_hori; 202 uint32_t log2_max_mv_length_vert; 203 uint32_t num_reorder_frames; 204 uint32_t max_dec_frame_buffering; 205 }; 206 207 struct rvce_enc_operation { 208 uint32_t insert_headers; 209 uint32_t picture_structure; 210 uint32_t allowed_max_bitstream_size; 211 uint32_t force_refresh_map; 212 uint32_t insert_aud; 213 uint32_t end_of_sequence; 214 uint32_t end_of_stream; 215 uint32_t input_picture_luma_address_hi; 216 uint32_t input_picture_luma_address_lo; 217 uint32_t input_picture_chroma_address_hi; 218 uint32_t input_picture_chroma_address_lo; 219 uint32_t enc_input_frame_y_pitch; 220 uint32_t enc_input_pic_luma_pitch; 221 uint32_t enc_input_pic_chroma_pitch;; 222 uint32_t enc_input_pic_addr_array; 223 uint32_t enc_input_pic_addr_array_disable2pipe_disablemboffload; 224 uint32_t enc_input_pic_tile_config; 225 uint32_t enc_pic_type; 226 uint32_t enc_idr_flag; 227 uint32_t enc_idr_pic_id; 228 uint32_t enc_mgs_key_pic; 229 uint32_t enc_reference_flag; 230 uint32_t enc_temporal_layer_index; 231 uint32_t num_ref_idx_active_override_flag; 232 uint32_t num_ref_idx_l0_active_minus1; 233 uint32_t num_ref_idx_l1_active_minus1; 234 uint32_t enc_ref_list_modification_op; 235 uint32_t enc_ref_list_modification_num; 236 uint32_t enc_decoded_picture_marking_op; 237 uint32_t enc_decoded_picture_marking_num; 238 uint32_t enc_decoded_picture_marking_idx; 239 uint32_t enc_decoded_ref_base_picture_marking_op; 240 uint32_t enc_decoded_ref_base_picture_marking_num; 241 uint32_t l0_picture_structure; 242 uint32_t l0_enc_pic_type; 243 uint32_t l0_frame_number; 244 uint32_t l0_picture_order_count; 245 uint32_t l0_luma_offset; 246 uint32_t l0_chroma_offset; 247 uint32_t l1_picture_structure; 248 uint32_t l1_enc_pic_type; 249 uint32_t l1_frame_number; 250 uint32_t l1_picture_order_count; 251 uint32_t l1_luma_offset; 252 uint32_t l1_chroma_offset; 253 uint32_t enc_reconstructed_luma_offset; 254 uint32_t enc_reconstructed_chroma_offset;; 255 uint32_t enc_coloc_buffer_offset; 256 uint32_t enc_reconstructed_ref_base_picture_luma_offset; 257 uint32_t enc_reconstructed_ref_base_picture_chroma_offset; 258 uint32_t enc_reference_ref_base_picture_luma_offset; 259 uint32_t enc_reference_ref_base_picture_chroma_offset; 260 uint32_t picture_count; 261 uint32_t frame_number; 262 uint32_t picture_order_count; 263 uint32_t num_i_pic_remain_in_rcgop; 264 uint32_t num_p_pic_remain_in_rcgop; 265 uint32_t num_b_pic_remain_in_rcgop; 266 uint32_t num_ir_pic_remain_in_rcgop; 267 uint32_t enable_intra_refresh; 268 uint32_t aq_variance_en; 269 uint32_t aq_block_size; 270 uint32_t aq_mb_variance_sel; 271 uint32_t aq_frame_variance_sel; 272 uint32_t aq_param_a; 273 uint32_t aq_param_b; 274 uint32_t aq_param_c; 275 uint32_t aq_param_d; 276 uint32_t aq_param_e; 277 uint32_t context_in_sfb; 278 }; 279 280 struct rvce_enc_create { 281 uint32_t enc_use_circular_buffer; 282 uint32_t enc_profile; 283 uint32_t enc_level; 284 uint32_t enc_pic_struct_restriction; 285 uint32_t enc_image_width; 286 uint32_t enc_image_height; 287 uint32_t enc_ref_pic_luma_pitch; 288 uint32_t enc_ref_pic_chroma_pitch; 289 uint32_t enc_ref_y_height_in_qw; 290 uint32_t enc_ref_pic_addr_array_enc_pic_struct_restriction_disable_rdo; 291 uint32_t enc_pre_encode_context_buffer_offset; 292 uint32_t enc_pre_encode_input_luma_buffer_offset; 293 uint32_t enc_pre_encode_input_chroma_buffer_offset; 294 uint32_t enc_pre_encode_mode_chromaflag_vbaqmode_scenechangesensitivity; 295 }; 296 297 struct rvce_config_ext { 298 uint32_t enc_enable_perf_logging; 299 }; 300 301 struct rvce_h264_enc_pic { 302 struct rvce_rate_control rc; 303 struct rvce_motion_estimation me; 304 struct rvce_pic_control pc; 305 struct rvce_task_info ti; 306 struct rvce_feedback_buf_pkg fb; 307 struct rvce_rdo rdo; 308 struct rvce_vui vui; 309 struct rvce_enc_operation eo; 310 struct rvce_enc_create ec; 311 struct rvce_config_ext ce; 312 313 unsigned quant_i_frames; 314 unsigned quant_p_frames; 315 unsigned quant_b_frames; 316 317 enum pipe_h2645_enc_picture_type picture_type; 318 unsigned frame_num; 319 unsigned frame_num_cnt; 320 unsigned p_remain; 321 unsigned i_remain; 322 unsigned idr_pic_id; 323 unsigned gop_cnt; 324 unsigned gop_size; 325 unsigned pic_order_cnt; 326 unsigned ref_idx_l0; 327 unsigned ref_idx_l1; 328 unsigned addrmode_arraymode_disrdo_distwoinstants; 329 330 bool not_referenced; 331 bool is_idr; 332 bool has_ref_pic_list; 333 bool enable_vui; 334 unsigned int ref_pic_list_0[32]; 335 unsigned int ref_pic_list_1[32]; 336 unsigned int frame_idx[32]; 337 }; 338 339 /* VCE encoder representation */ 340 struct rvce_encoder { 341 struct pipe_video_codec base; 342 343 /* version specific packets */ 344 void (*session)(struct rvce_encoder *enc); 345 void (*create)(struct rvce_encoder *enc); 346 void (*feedback)(struct rvce_encoder *enc); 347 void (*rate_control)(struct rvce_encoder *enc); 348 void (*config_extension)(struct rvce_encoder *enc); 349 void (*pic_control)(struct rvce_encoder *enc); 350 void (*motion_estimation)(struct rvce_encoder *enc); 351 void (*rdo)(struct rvce_encoder *enc); 352 void (*vui)(struct rvce_encoder *enc); 353 void (*config)(struct rvce_encoder *enc); 354 void (*encode)(struct rvce_encoder *enc); 355 void (*destroy)(struct rvce_encoder *enc); 356 void (*task_info)(struct rvce_encoder *enc, uint32_t op, 357 uint32_t dep, uint32_t fb_idx, 358 uint32_t ring_idx); 359 360 unsigned stream_handle; 361 362 struct pipe_screen *screen; 363 struct radeon_winsys* ws; 364 struct radeon_cmdbuf cs; 365 366 rvce_get_buffer get_buffer; 367 368 struct pb_buffer_lean* handle; 369 struct radeon_surf* luma; 370 struct radeon_surf* chroma; 371 372 struct pb_buffer_lean* bs_handle; 373 unsigned bs_size; 374 375 struct rvce_cpb_slot *cpb_array; 376 struct list_head cpb_slots; 377 unsigned cpb_num; 378 379 struct rvid_buffer *fb; 380 struct rvid_buffer cpb; 381 struct pipe_h264_enc_picture_desc pic; 382 struct rvce_h264_enc_pic enc_pic; 383 384 unsigned task_info_idx; 385 unsigned bs_idx; 386 387 bool use_vm; 388 bool use_vui; 389 bool dual_pipe; 390 bool dual_inst; 391 }; 392 393 /* CPB handling functions */ 394 struct rvce_cpb_slot *current_slot(struct rvce_encoder *enc); 395 struct rvce_cpb_slot *l0_slot(struct rvce_encoder *enc); 396 struct rvce_cpb_slot *l1_slot(struct rvce_encoder *enc); 397 void rvce_frame_offset(struct rvce_encoder *enc, struct rvce_cpb_slot *slot, 398 signed *luma_offset, signed *chroma_offset); 399 400 struct pipe_video_codec *rvce_create_encoder(struct pipe_context *context, 401 const struct pipe_video_codec *templat, 402 struct radeon_winsys* ws, 403 rvce_get_buffer get_buffer); 404 405 bool rvce_is_fw_version_supported(struct r600_common_screen *rscreen); 406 407 void rvce_add_buffer(struct rvce_encoder *enc, struct pb_buffer_lean *buf, 408 unsigned usage, enum radeon_bo_domain domain, 409 signed offset); 410 411 /* init vce fw 40.2.2 specific callbacks */ 412 void radeon_vce_40_2_2_init(struct rvce_encoder *enc); 413 414 /* init vce fw 50 specific callbacks */ 415 void radeon_vce_50_init(struct rvce_encoder *enc); 416 417 /* init vce fw 52 specific callbacks */ 418 void radeon_vce_52_init(struct rvce_encoder *enc); 419 420 /* get parameters for vce 40.2.2 */ 421 void radeon_vce_40_2_2_get_param(struct rvce_encoder *enc, 422 struct pipe_h264_enc_picture_desc *pic); 423 424 /* get parameters for vce 50 */ 425 void radeon_vce_50_get_param(struct rvce_encoder *enc, 426 struct pipe_h264_enc_picture_desc *pic); 427 428 /* get parameters for vce 52 */ 429 void radeon_vce_52_get_param(struct rvce_encoder *enc, 430 struct pipe_h264_enc_picture_desc *pic); 431 432 #endif 433