1 /* 2 * Copyright 2011 Advanced Micro Devices, Inc. 3 * Authors: 4 * Christian König <[email protected]> 5 * SPDX-License-Identifier: MIT 6 */ 7 8 #ifndef RADEON_UVD_H 9 #define RADEON_UVD_H 10 11 #include "winsys/radeon_winsys.h" 12 #include "vl/vl_video_buffer.h" 13 14 /* UVD uses PM4 packet type 0 and 2 */ 15 #define RUVD_PKT_TYPE_S(x) (((unsigned)(x) & 0x3) << 30) 16 #define RUVD_PKT_TYPE_G(x) (((x) >> 30) & 0x3) 17 #define RUVD_PKT_TYPE_C 0x3FFFFFFF 18 #define RUVD_PKT_COUNT_S(x) (((unsigned)(x) & 0x3FFF) << 16) 19 #define RUVD_PKT_COUNT_G(x) (((x) >> 16) & 0x3FFF) 20 #define RUVD_PKT_COUNT_C 0xC000FFFF 21 #define RUVD_PKT0_BASE_INDEX_S(x) (((unsigned)(x) & 0xFFFF) << 0) 22 #define RUVD_PKT0_BASE_INDEX_G(x) (((x) >> 0) & 0xFFFF) 23 #define RUVD_PKT0_BASE_INDEX_C 0xFFFF0000 24 #define RUVD_PKT0(index, count) (RUVD_PKT_TYPE_S(0) | RUVD_PKT0_BASE_INDEX_S(index) | RUVD_PKT_COUNT_S(count)) 25 #define RUVD_PKT2() (RUVD_PKT_TYPE_S(2)) 26 27 /* registers involved with UVD */ 28 #define RUVD_GPCOM_VCPU_CMD 0xEF0C 29 #define RUVD_GPCOM_VCPU_DATA0 0xEF10 30 #define RUVD_GPCOM_VCPU_DATA1 0xEF14 31 #define RUVD_ENGINE_CNTL 0xEF18 32 33 #define RUVD_GPCOM_VCPU_CMD_SOC15 0x2070c 34 #define RUVD_GPCOM_VCPU_DATA0_SOC15 0x20710 35 #define RUVD_GPCOM_VCPU_DATA1_SOC15 0x20714 36 #define RUVD_ENGINE_CNTL_SOC15 0x20718 37 38 /* UVD commands to VCPU */ 39 #define RUVD_CMD_MSG_BUFFER 0x00000000 40 #define RUVD_CMD_DPB_BUFFER 0x00000001 41 #define RUVD_CMD_DECODING_TARGET_BUFFER 0x00000002 42 #define RUVD_CMD_FEEDBACK_BUFFER 0x00000003 43 #define RUVD_CMD_SESSION_CONTEXT_BUFFER 0x00000005 44 #define RUVD_CMD_BITSTREAM_BUFFER 0x00000100 45 #define RUVD_CMD_ITSCALING_TABLE_BUFFER 0x00000204 46 #define RUVD_CMD_CONTEXT_BUFFER 0x00000206 47 48 /* UVD message types */ 49 #define RUVD_MSG_CREATE 0 50 #define RUVD_MSG_DECODE 1 51 #define RUVD_MSG_DESTROY 2 52 53 /* UVD stream types */ 54 #define RUVD_CODEC_H264 0x00000000 55 #define RUVD_CODEC_VC1 0x00000001 56 #define RUVD_CODEC_MPEG2 0x00000003 57 #define RUVD_CODEC_MPEG4 0x00000004 58 #define RUVD_CODEC_H264_PERF 0x00000007 59 #define RUVD_CODEC_MJPEG 0x00000008 60 #define RUVD_CODEC_H265 0x00000010 61 62 /* UVD decode target buffer tiling mode */ 63 #define RUVD_TILE_LINEAR 0x00000000 64 #define RUVD_TILE_8X4 0x00000001 65 #define RUVD_TILE_8X8 0x00000002 66 #define RUVD_TILE_32AS8 0x00000003 67 68 /* UVD decode target buffer array mode */ 69 #define RUVD_ARRAY_MODE_LINEAR 0x00000000 70 #define RUVD_ARRAY_MODE_MACRO_LINEAR_MICRO_TILED 0x00000001 71 #define RUVD_ARRAY_MODE_1D_THIN 0x00000002 72 #define RUVD_ARRAY_MODE_2D_THIN 0x00000004 73 #define RUVD_ARRAY_MODE_MACRO_TILED_MICRO_LINEAR 0x00000004 74 #define RUVD_ARRAY_MODE_MACRO_TILED_MICRO_TILED 0x00000005 75 76 /* UVD tile config */ 77 #define RUVD_BANK_WIDTH(x) ((x) << 0) 78 #define RUVD_BANK_HEIGHT(x) ((x) << 3) 79 #define RUVD_MACRO_TILE_ASPECT_RATIO(x) ((x) << 6) 80 #define RUVD_NUM_BANKS(x) ((x) << 9) 81 82 /* H.264 profile definitions */ 83 #define RUVD_H264_PROFILE_BASELINE 0x00000000 84 #define RUVD_H264_PROFILE_MAIN 0x00000001 85 #define RUVD_H264_PROFILE_HIGH 0x00000002 86 #define RUVD_H264_PROFILE_STEREO_HIGH 0x00000003 87 #define RUVD_H264_PROFILE_MVC 0x00000004 88 89 /* VC-1 profile definitions */ 90 #define RUVD_VC1_PROFILE_SIMPLE 0x00000000 91 #define RUVD_VC1_PROFILE_MAIN 0x00000001 92 #define RUVD_VC1_PROFILE_ADVANCED 0x00000002 93 94 struct ruvd_mvc_element { 95 uint16_t viewOrderIndex; 96 uint16_t viewId; 97 uint16_t numOfAnchorRefsInL0; 98 uint16_t viewIdOfAnchorRefsInL0[15]; 99 uint16_t numOfAnchorRefsInL1; 100 uint16_t viewIdOfAnchorRefsInL1[15]; 101 uint16_t numOfNonAnchorRefsInL0; 102 uint16_t viewIdOfNonAnchorRefsInL0[15]; 103 uint16_t numOfNonAnchorRefsInL1; 104 uint16_t viewIdOfNonAnchorRefsInL1[15]; 105 }; 106 107 struct ruvd_h264 { 108 uint32_t profile; 109 uint32_t level; 110 111 uint32_t sps_info_flags; 112 uint32_t pps_info_flags; 113 uint8_t chroma_format; 114 uint8_t bit_depth_luma_minus8; 115 uint8_t bit_depth_chroma_minus8; 116 uint8_t log2_max_frame_num_minus4; 117 118 uint8_t pic_order_cnt_type; 119 uint8_t log2_max_pic_order_cnt_lsb_minus4; 120 uint8_t num_ref_frames; 121 uint8_t reserved_8bit; 122 123 int8_t pic_init_qp_minus26; 124 int8_t pic_init_qs_minus26; 125 int8_t chroma_qp_index_offset; 126 int8_t second_chroma_qp_index_offset; 127 128 uint8_t num_slice_groups_minus1; 129 uint8_t slice_group_map_type; 130 uint8_t num_ref_idx_l0_active_minus1; 131 uint8_t num_ref_idx_l1_active_minus1; 132 133 uint16_t slice_group_change_rate_minus1; 134 uint16_t reserved_16bit_1; 135 136 uint8_t scaling_list_4x4[6][16]; 137 uint8_t scaling_list_8x8[2][64]; 138 139 uint32_t frame_num; 140 uint32_t frame_num_list[16]; 141 int32_t curr_field_order_cnt_list[2]; 142 int32_t field_order_cnt_list[16][2]; 143 144 uint32_t decoded_pic_idx; 145 146 uint32_t curr_pic_ref_frame_num; 147 148 uint8_t ref_frame_list[16]; 149 150 uint32_t reserved[122]; 151 152 struct { 153 uint32_t numViews; 154 uint32_t viewId0; 155 struct ruvd_mvc_element mvcElements[1]; 156 } mvc; 157 }; 158 159 struct ruvd_h265 { 160 uint32_t sps_info_flags; 161 uint32_t pps_info_flags; 162 163 uint8_t chroma_format; 164 uint8_t bit_depth_luma_minus8; 165 uint8_t bit_depth_chroma_minus8; 166 uint8_t log2_max_pic_order_cnt_lsb_minus4; 167 168 uint8_t sps_max_dec_pic_buffering_minus1; 169 uint8_t log2_min_luma_coding_block_size_minus3; 170 uint8_t log2_diff_max_min_luma_coding_block_size; 171 uint8_t log2_min_transform_block_size_minus2; 172 173 uint8_t log2_diff_max_min_transform_block_size; 174 uint8_t max_transform_hierarchy_depth_inter; 175 uint8_t max_transform_hierarchy_depth_intra; 176 uint8_t pcm_sample_bit_depth_luma_minus1; 177 178 uint8_t pcm_sample_bit_depth_chroma_minus1; 179 uint8_t log2_min_pcm_luma_coding_block_size_minus3; 180 uint8_t log2_diff_max_min_pcm_luma_coding_block_size; 181 uint8_t num_extra_slice_header_bits; 182 183 uint8_t num_short_term_ref_pic_sets; 184 uint8_t num_long_term_ref_pic_sps; 185 uint8_t num_ref_idx_l0_default_active_minus1; 186 uint8_t num_ref_idx_l1_default_active_minus1; 187 188 int8_t pps_cb_qp_offset; 189 int8_t pps_cr_qp_offset; 190 int8_t pps_beta_offset_div2; 191 int8_t pps_tc_offset_div2; 192 193 uint8_t diff_cu_qp_delta_depth; 194 uint8_t num_tile_columns_minus1; 195 uint8_t num_tile_rows_minus1; 196 uint8_t log2_parallel_merge_level_minus2; 197 198 uint16_t column_width_minus1[19]; 199 uint16_t row_height_minus1[21]; 200 201 int8_t init_qp_minus26; 202 uint8_t num_delta_pocs_ref_rps_idx; 203 uint8_t curr_idx; 204 uint8_t reserved1; 205 int32_t curr_poc; 206 uint8_t ref_pic_list[16]; 207 int32_t poc_list[16]; 208 uint8_t ref_pic_set_st_curr_before[8]; 209 uint8_t ref_pic_set_st_curr_after[8]; 210 uint8_t ref_pic_set_lt_curr[8]; 211 212 uint8_t ucScalingListDCCoefSizeID2[6]; 213 uint8_t ucScalingListDCCoefSizeID3[2]; 214 215 uint8_t highestTid; 216 uint8_t isNonRef; 217 218 uint8_t p010_mode; 219 uint8_t msb_mode; 220 uint8_t luma_10to8; 221 uint8_t chroma_10to8; 222 uint8_t sclr_luma10to8; 223 uint8_t sclr_chroma10to8; 224 225 uint8_t direct_reflist[2][15]; 226 }; 227 228 struct ruvd_vc1 { 229 uint32_t profile; 230 uint32_t level; 231 uint32_t sps_info_flags; 232 uint32_t pps_info_flags; 233 uint32_t pic_structure; 234 uint32_t chroma_format; 235 }; 236 237 struct ruvd_mpeg2 { 238 uint32_t decoded_pic_idx; 239 uint32_t ref_pic_idx[2]; 240 241 uint8_t load_intra_quantiser_matrix; 242 uint8_t load_nonintra_quantiser_matrix; 243 uint8_t reserved_quantiser_alignement[2]; 244 uint8_t intra_quantiser_matrix[64]; 245 uint8_t nonintra_quantiser_matrix[64]; 246 247 uint8_t profile_and_level_indication; 248 uint8_t chroma_format; 249 250 uint8_t picture_coding_type; 251 252 uint8_t reserved_1; 253 254 uint8_t f_code[2][2]; 255 uint8_t intra_dc_precision; 256 uint8_t pic_structure; 257 uint8_t top_field_first; 258 uint8_t frame_pred_frame_dct; 259 uint8_t concealment_motion_vectors; 260 uint8_t q_scale_type; 261 uint8_t intra_vlc_format; 262 uint8_t alternate_scan; 263 }; 264 265 struct ruvd_mpeg4 266 { 267 uint32_t decoded_pic_idx; 268 uint32_t ref_pic_idx[2]; 269 270 uint32_t variant_type; 271 uint8_t profile_and_level_indication; 272 273 uint8_t video_object_layer_verid; 274 uint8_t video_object_layer_shape; 275 276 uint8_t reserved_1; 277 278 uint16_t video_object_layer_width; 279 uint16_t video_object_layer_height; 280 281 uint16_t vop_time_increment_resolution; 282 283 uint16_t reserved_2; 284 285 uint32_t flags; 286 287 uint8_t quant_type; 288 289 uint8_t reserved_3[3]; 290 291 uint8_t intra_quant_mat[64]; 292 uint8_t nonintra_quant_mat[64]; 293 294 struct { 295 uint8_t sprite_enable; 296 297 uint8_t reserved_4[3]; 298 299 uint16_t sprite_width; 300 uint16_t sprite_height; 301 int16_t sprite_left_coordinate; 302 int16_t sprite_top_coordinate; 303 304 uint8_t no_of_sprite_warping_points; 305 uint8_t sprite_warping_accuracy; 306 uint8_t sprite_brightness_change; 307 uint8_t low_latency_sprite_enable; 308 } sprite_config; 309 310 struct { 311 uint32_t flags; 312 uint8_t vol_mode; 313 uint8_t reserved_5[3]; 314 } divx_311_config; 315 }; 316 317 /* message between driver and hardware */ 318 struct ruvd_msg { 319 320 uint32_t size; 321 uint32_t msg_type; 322 uint32_t stream_handle; 323 uint32_t status_report_feedback_number; 324 325 union { 326 struct { 327 uint32_t stream_type; 328 uint32_t session_flags; 329 uint32_t asic_id; 330 uint32_t width_in_samples; 331 uint32_t height_in_samples; 332 uint32_t dpb_buffer; 333 uint32_t dpb_size; 334 uint32_t dpb_model; 335 uint32_t version_info; 336 } create; 337 338 struct { 339 uint32_t stream_type; 340 uint32_t decode_flags; 341 uint32_t width_in_samples; 342 uint32_t height_in_samples; 343 344 uint32_t dpb_buffer; 345 uint32_t dpb_size; 346 uint32_t dpb_model; 347 uint32_t dpb_reserved; 348 349 uint32_t db_offset_alignment; 350 uint32_t db_pitch; 351 uint32_t db_tiling_mode; 352 uint32_t db_array_mode; 353 uint32_t db_field_mode; 354 uint32_t db_surf_tile_config; 355 uint32_t db_aligned_height; 356 uint32_t db_reserved; 357 358 uint32_t use_addr_macro; 359 360 uint32_t bsd_buffer; 361 uint32_t bsd_size; 362 363 uint32_t pic_param_buffer; 364 uint32_t pic_param_size; 365 uint32_t mb_cntl_buffer; 366 uint32_t mb_cntl_size; 367 368 uint32_t dt_buffer; 369 uint32_t dt_pitch; 370 uint32_t dt_tiling_mode; 371 uint32_t dt_array_mode; 372 uint32_t dt_field_mode; 373 uint32_t dt_luma_top_offset; 374 uint32_t dt_luma_bottom_offset; 375 uint32_t dt_chroma_top_offset; 376 uint32_t dt_chroma_bottom_offset; 377 uint32_t dt_surf_tile_config; 378 uint32_t dt_uv_surf_tile_config; 379 // reuse dt_wa_chroma_top_offset as dt_ext_info for UV pitch in stoney 380 uint32_t dt_wa_chroma_top_offset; 381 uint32_t dt_wa_chroma_bottom_offset; 382 383 uint32_t reserved[16]; 384 385 union { 386 struct ruvd_h264 h264; 387 struct ruvd_h265 h265; 388 struct ruvd_vc1 vc1; 389 struct ruvd_mpeg2 mpeg2; 390 struct ruvd_mpeg4 mpeg4; 391 392 uint32_t info[768]; 393 } codec; 394 395 uint8_t extension_support; 396 uint8_t reserved_8bit_1; 397 uint8_t reserved_8bit_2; 398 uint8_t reserved_8bit_3; 399 uint32_t extension_reserved[64]; 400 } decode; 401 } body; 402 }; 403 404 /* driver dependent callback */ 405 typedef struct pb_buffer_lean* (*ruvd_set_dtb) 406 (struct ruvd_msg* msg, struct vl_video_buffer *vb); 407 408 /* create an UVD decode */ 409 struct pipe_video_codec *ruvd_create_decoder(struct pipe_context *context, 410 const struct pipe_video_codec *templat, 411 ruvd_set_dtb set_dtb); 412 413 /* fill decoding target field from the luma and chroma surfaces */ 414 void ruvd_set_dt_surfaces(struct ruvd_msg *msg, struct radeon_surf *luma, 415 struct radeon_surf *chroma); 416 #endif 417