1 /*
2 * Copyright 2008 Corbin Simpson <[email protected]>
3 * Copyright 2010 Marek Olšák <[email protected]>
4 * SPDX-License-Identifier: MIT
5 */
6
7 #include "compiler/nir/nir.h"
8 #include "util/format/u_format.h"
9 #include "util/format/u_format_s3tc.h"
10 #include "util/u_screen.h"
11 #include "util/u_memory.h"
12 #include "util/hex.h"
13 #include "util/os_time.h"
14 #include "util/xmlconfig.h"
15 #include "vl/vl_decoder.h"
16 #include "vl/vl_video_buffer.h"
17
18 #include "r300_context.h"
19 #include "r300_texture.h"
20 #include "r300_screen_buffer.h"
21 #include "r300_state_inlines.h"
22 #include "r300_public.h"
23 #include "compiler/r300_nir.h"
24
25 #include "draw/draw_context.h"
26
27 /* Return the identifier behind whom the brave coders responsible for this
28 * amalgamation of code, sweat, and duct tape, routinely obscure their names.
29 *
30 * ...I should have just put "Corbin Simpson", but I'm not that cool.
31 *
32 * (Or egotistical. Yet.) */
r300_get_vendor(struct pipe_screen * pscreen)33 static const char* r300_get_vendor(struct pipe_screen* pscreen)
34 {
35 return "Mesa";
36 }
37
r300_get_device_vendor(struct pipe_screen * pscreen)38 static const char* r300_get_device_vendor(struct pipe_screen* pscreen)
39 {
40 return "ATI";
41 }
42
43 static const char* chip_families[] = {
44 "unknown",
45 "ATI R300",
46 "ATI R350",
47 "ATI RV350",
48 "ATI RV370",
49 "ATI RV380",
50 "ATI RS400",
51 "ATI RC410",
52 "ATI RS480",
53 "ATI R420",
54 "ATI R423",
55 "ATI R430",
56 "ATI R480",
57 "ATI R481",
58 "ATI RV410",
59 "ATI RS600",
60 "ATI RS690",
61 "ATI RS740",
62 "ATI RV515",
63 "ATI R520",
64 "ATI RV530",
65 "ATI R580",
66 "ATI RV560",
67 "ATI RV570"
68 };
69
r300_get_family_name(struct r300_screen * r300screen)70 static const char* r300_get_family_name(struct r300_screen* r300screen)
71 {
72 return chip_families[r300screen->caps.family];
73 }
74
r300_get_name(struct pipe_screen * pscreen)75 static const char* r300_get_name(struct pipe_screen* pscreen)
76 {
77 struct r300_screen* r300screen = r300_screen(pscreen);
78
79 return r300_get_family_name(r300screen);
80 }
81
r300_disk_cache_create(struct r300_screen * r300screen)82 static void r300_disk_cache_create(struct r300_screen* r300screen)
83 {
84 struct mesa_sha1 ctx;
85 unsigned char sha1[20];
86 char cache_id[20 * 2 + 1];
87
88 _mesa_sha1_init(&ctx);
89 if (!disk_cache_get_function_identifier(r300_disk_cache_create,
90 &ctx))
91 return;
92
93 _mesa_sha1_final(&ctx, sha1);
94 mesa_bytes_to_hex(cache_id, sha1, 20);
95
96 r300screen->disk_shader_cache =
97 disk_cache_create(r300_get_family_name(r300screen),
98 cache_id,
99 r300screen->debug);
100 }
101
r300_get_disk_shader_cache(struct pipe_screen * pscreen)102 static struct disk_cache* r300_get_disk_shader_cache(struct pipe_screen* pscreen)
103 {
104 struct r300_screen* r300screen = r300_screen(pscreen);
105 return r300screen->disk_shader_cache;
106 }
107
r300_get_param(struct pipe_screen * pscreen,enum pipe_cap param)108 static int r300_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
109 {
110 struct r300_screen* r300screen = r300_screen(pscreen);
111 bool is_r500 = r300screen->caps.is_r500;
112
113 switch (param) {
114 /* Supported features (boolean caps). */
115 case PIPE_CAP_NPOT_TEXTURES:
116 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
117 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
118 case PIPE_CAP_ANISOTROPIC_FILTER:
119 case PIPE_CAP_OCCLUSION_QUERY:
120 case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
121 case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE:
122 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
123 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
124 case PIPE_CAP_FS_COORD_ORIGIN_UPPER_LEFT:
125 case PIPE_CAP_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
126 case PIPE_CAP_CONDITIONAL_RENDER:
127 case PIPE_CAP_TEXTURE_BARRIER:
128 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
129 case PIPE_CAP_CLIP_HALFZ:
130 case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
131 case PIPE_CAP_LEGACY_MATH_RULES:
132 case PIPE_CAP_TGSI_TEXCOORD:
133 return 1;
134
135 case PIPE_CAP_TEXTURE_TRANSFER_MODES:
136 return PIPE_TEXTURE_TRANSFER_BLIT;
137
138 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
139 return R300_BUFFER_ALIGNMENT;
140
141 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
142 return 16;
143
144 case PIPE_CAP_GLSL_FEATURE_LEVEL:
145 case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
146 return 120;
147
148 /* r300 cannot do swizzling of compressed textures. Supported otherwise. */
149 case PIPE_CAP_TEXTURE_SWIZZLE:
150 return r300screen->caps.dxtc_swizzle;
151
152 /* We don't support color clamping on r500, so that we can use color
153 * interpolators for generic varyings. */
154 case PIPE_CAP_VERTEX_COLOR_CLAMPED:
155 return !is_r500;
156
157 /* Supported on r500 only. */
158 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
159 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
160 case PIPE_CAP_FRAGMENT_SHADER_TEXTURE_LOD:
161 case PIPE_CAP_FRAGMENT_SHADER_DERIVATIVES:
162 return is_r500 ? 1 : 0;
163
164 case PIPE_CAP_SHAREABLE_SHADERS:
165 return 0;
166
167 case PIPE_CAP_MAX_GS_INVOCATIONS:
168 return 32;
169 case PIPE_CAP_MAX_SHADER_BUFFER_SIZE_UINT:
170 return 1 << 27;
171
172 /* SWTCL-only features. */
173 case PIPE_CAP_PRIMITIVE_RESTART:
174 case PIPE_CAP_PRIMITIVE_RESTART_FIXED_INDEX:
175 case PIPE_CAP_USER_VERTEX_BUFFERS:
176 case PIPE_CAP_VS_WINDOW_SPACE_POSITION:
177 return !r300screen->caps.has_tcl;
178
179 /* HWTCL-only features / limitations. */
180 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
181 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
182 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
183 return r300screen->caps.has_tcl;
184
185 /* Texturing. */
186 case PIPE_CAP_MAX_TEXTURE_2D_SIZE:
187 return is_r500 ? 4096 : 2048;
188 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
189 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
190 /* 13 == 4096, 12 == 2048 */
191 return is_r500 ? 13 : 12;
192
193 /* Render targets. */
194 case PIPE_CAP_MAX_RENDER_TARGETS:
195 return 4;
196 case PIPE_CAP_ENDIANNESS:
197 return PIPE_ENDIAN_LITTLE;
198
199 case PIPE_CAP_MAX_VIEWPORTS:
200 return 1;
201
202 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
203 return 2048;
204
205 case PIPE_CAP_MAX_VARYINGS:
206 return 10;
207
208 case PIPE_CAP_PREFER_IMM_ARRAYS_AS_CONSTBUF:
209 return 0;
210
211 case PIPE_CAP_VENDOR_ID:
212 return 0x1002;
213 case PIPE_CAP_DEVICE_ID:
214 return r300screen->info.pci_id;
215 case PIPE_CAP_ACCELERATED:
216 return 1;
217 case PIPE_CAP_VIDEO_MEMORY:
218 return r300screen->info.vram_size_kb >> 10;
219 case PIPE_CAP_UMA:
220 return 0;
221 case PIPE_CAP_PCI_GROUP:
222 return r300screen->info.pci.domain;
223 case PIPE_CAP_PCI_BUS:
224 return r300screen->info.pci.bus;
225 case PIPE_CAP_PCI_DEVICE:
226 return r300screen->info.pci.dev;
227 case PIPE_CAP_PCI_FUNCTION:
228 return r300screen->info.pci.func;
229 default:
230 return u_pipe_screen_get_param_defaults(pscreen, param);
231 }
232 }
233
r300_get_shader_param(struct pipe_screen * pscreen,enum pipe_shader_type shader,enum pipe_shader_cap param)234 static int r300_get_shader_param(struct pipe_screen *pscreen,
235 enum pipe_shader_type shader,
236 enum pipe_shader_cap param)
237 {
238 struct r300_screen* r300screen = r300_screen(pscreen);
239 bool is_r400 = r300screen->caps.is_r400;
240 bool is_r500 = r300screen->caps.is_r500;
241
242 switch (param) {
243 case PIPE_SHADER_CAP_SUPPORTED_IRS:
244 return (1 << PIPE_SHADER_IR_NIR) | (1 << PIPE_SHADER_IR_TGSI);
245 default:
246 break;
247 }
248
249 switch (shader) {
250 case PIPE_SHADER_FRAGMENT:
251 switch (param)
252 {
253 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
254 return is_r500 || is_r400 ? 512 : 96;
255 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
256 return is_r500 || is_r400 ? 512 : 64;
257 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
258 return is_r500 || is_r400 ? 512 : 32;
259 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
260 return is_r500 ? 511 : 4;
261 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
262 return is_r500 ? 64 : 0; /* Actually unlimited on r500. */
263 /* Fragment shader limits. */
264 case PIPE_SHADER_CAP_MAX_INPUTS:
265 /* 2 colors + 8 texcoords are always supported
266 * (minus fog and wpos).
267 *
268 * R500 has the ability to turn 3rd and 4th color into
269 * additional texcoords but there is no two-sided color
270 * selection then. However the facing bit can be used instead. */
271 return 10;
272 case PIPE_SHADER_CAP_MAX_OUTPUTS:
273 return 4;
274 case PIPE_SHADER_CAP_MAX_CONST_BUFFER0_SIZE:
275 return (is_r500 ? 256 : 32) * sizeof(float[4]);
276 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
277 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
278 return 1;
279 case PIPE_SHADER_CAP_MAX_TEMPS:
280 return is_r500 ? 128 : is_r400 ? 64 : 32;
281 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
282 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
283 return r300screen->caps.num_tex_units;
284 case PIPE_SHADER_CAP_CONT_SUPPORTED:
285 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
286 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
287 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
288 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
289 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
290 case PIPE_SHADER_CAP_SUBROUTINES:
291 case PIPE_SHADER_CAP_INTEGERS:
292 case PIPE_SHADER_CAP_INT64_ATOMICS:
293 case PIPE_SHADER_CAP_FP16:
294 case PIPE_SHADER_CAP_FP16_DERIVATIVES:
295 case PIPE_SHADER_CAP_FP16_CONST_BUFFERS:
296 case PIPE_SHADER_CAP_INT16:
297 case PIPE_SHADER_CAP_GLSL_16BIT_CONSTS:
298 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
299 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
300 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
301 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
302 return 0;
303 default:
304 break;
305 }
306 break;
307 case PIPE_SHADER_VERTEX:
308 switch (param)
309 {
310 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
311 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
312 case PIPE_SHADER_CAP_SUBROUTINES:
313 return 0;
314 default:;
315 }
316
317 if (!r300screen->caps.has_tcl) {
318 switch (param) {
319 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
320 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
321 return 0;
322
323 /* mesa/st requires that this cap is the same across stages, and the FS
324 * can't do ints.
325 */
326 case PIPE_SHADER_CAP_INTEGERS:
327 return 0;
328
329 /* Even if gallivm NIR can do this, we call nir_to_tgsi manually and
330 * TGSI can't.
331 */
332 case PIPE_SHADER_CAP_INT16:
333 case PIPE_SHADER_CAP_FP16:
334 case PIPE_SHADER_CAP_FP16_DERIVATIVES:
335 case PIPE_SHADER_CAP_FP16_CONST_BUFFERS:
336 return 0;
337
338 /* While draw could normally handle this for the VS, the NIR lowering
339 * to regs can't handle our non-native-integers, so we have to lower to
340 * if ladders.
341 */
342 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
343 return 0;
344 default:
345 return draw_get_shader_param(shader, param);
346 }
347 }
348
349 switch (param)
350 {
351 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
352 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
353 return is_r500 ? 1024 : 256;
354 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
355 return is_r500 ? 4 : 0; /* For loops; not sure about conditionals. */
356 case PIPE_SHADER_CAP_MAX_INPUTS:
357 return 16;
358 case PIPE_SHADER_CAP_MAX_OUTPUTS:
359 return 10;
360 case PIPE_SHADER_CAP_MAX_CONST_BUFFER0_SIZE:
361 return 256 * sizeof(float[4]);
362 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
363 return 1;
364 case PIPE_SHADER_CAP_MAX_TEMPS:
365 return 32;
366 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
367 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
368 return 1;
369 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
370 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
371 case PIPE_SHADER_CAP_CONT_SUPPORTED:
372 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
373 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
374 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
375 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
376 case PIPE_SHADER_CAP_SUBROUTINES:
377 case PIPE_SHADER_CAP_INTEGERS:
378 case PIPE_SHADER_CAP_FP16:
379 case PIPE_SHADER_CAP_FP16_CONST_BUFFERS:
380 case PIPE_SHADER_CAP_FP16_DERIVATIVES:
381 case PIPE_SHADER_CAP_INT16:
382 case PIPE_SHADER_CAP_GLSL_16BIT_CONSTS:
383 case PIPE_SHADER_CAP_INT64_ATOMICS:
384 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
385 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
386 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
387 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
388 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
389 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
390 return 0;
391 default:
392 break;
393 }
394 break;
395 default:
396 ; /* nothing */
397 }
398 return 0;
399 }
400
r300_get_paramf(struct pipe_screen * pscreen,enum pipe_capf param)401 static float r300_get_paramf(struct pipe_screen* pscreen,
402 enum pipe_capf param)
403 {
404 struct r300_screen* r300screen = r300_screen(pscreen);
405
406 switch (param) {
407 case PIPE_CAPF_MIN_LINE_WIDTH:
408 case PIPE_CAPF_MIN_LINE_WIDTH_AA:
409 case PIPE_CAPF_MIN_POINT_SIZE:
410 case PIPE_CAPF_MIN_POINT_SIZE_AA:
411 return 1;
412 case PIPE_CAPF_POINT_SIZE_GRANULARITY:
413 case PIPE_CAPF_LINE_WIDTH_GRANULARITY:
414 return 0.1;
415 case PIPE_CAPF_MAX_LINE_WIDTH:
416 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
417 case PIPE_CAPF_MAX_POINT_SIZE:
418 case PIPE_CAPF_MAX_POINT_SIZE_AA:
419 /* The maximum dimensions of the colorbuffer are our practical
420 * rendering limits. 2048 pixels should be enough for anybody. */
421 if (r300screen->caps.is_r500) {
422 return 4096.0f;
423 } else if (r300screen->caps.is_r400) {
424 return 4021.0f;
425 } else {
426 return 2560.0f;
427 }
428 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
429 return 16.0f;
430 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
431 return 16.0f;
432 case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
433 case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
434 case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
435 return 0.0f;
436 default:
437 debug_printf("r300: Warning: Unknown CAP %d in get_paramf.\n",
438 param);
439 return 0.0f;
440 }
441 }
442
r300_get_video_param(struct pipe_screen * screen,enum pipe_video_profile profile,enum pipe_video_entrypoint entrypoint,enum pipe_video_cap param)443 static int r300_get_video_param(struct pipe_screen *screen,
444 enum pipe_video_profile profile,
445 enum pipe_video_entrypoint entrypoint,
446 enum pipe_video_cap param)
447 {
448 switch (param) {
449 case PIPE_VIDEO_CAP_SUPPORTED:
450 return vl_profile_supported(screen, profile, entrypoint);
451 case PIPE_VIDEO_CAP_NPOT_TEXTURES:
452 return 0;
453 case PIPE_VIDEO_CAP_MAX_WIDTH:
454 case PIPE_VIDEO_CAP_MAX_HEIGHT:
455 return vl_video_buffer_max_size(screen);
456 case PIPE_VIDEO_CAP_PREFERED_FORMAT:
457 return PIPE_FORMAT_NV12;
458 case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
459 return false;
460 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
461 return false;
462 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
463 return true;
464 case PIPE_VIDEO_CAP_MAX_LEVEL:
465 return vl_level_supported(screen, profile);
466 default:
467 return 0;
468 }
469 }
470
471 #define COMMON_NIR_OPTIONS \
472 .fdot_replicates = true, \
473 .fuse_ffma32 = true, \
474 .fuse_ffma64 = true, \
475 .lower_bitops = true, \
476 .lower_extract_byte = true, \
477 .lower_extract_word = true, \
478 .lower_fceil = true, \
479 .lower_fdiv = true, \
480 .lower_fdph = true, \
481 .lower_ffloor = true, \
482 .lower_flrp32 = true, \
483 .lower_flrp64 = true, \
484 .lower_fmod = true, \
485 .lower_fsign = true, \
486 .lower_fsqrt = true, \
487 .lower_ftrunc = true, \
488 .lower_insert_byte = true, \
489 .lower_insert_word = true, \
490 .lower_uniforms_to_ubo = true, \
491 .lower_vector_cmp = true, \
492 .no_integers = true, \
493 .use_interpolated_input_intrinsics = true, \
494 .has_ddx_intrinsics = true
495
496 static const nir_shader_compiler_options r500_vs_compiler_options = {
497 COMMON_NIR_OPTIONS,
498 .has_fused_comp_and_csel = true,
499
500 /* Have HW loops support and 1024 max instr count, but don't unroll *too*
501 * hard.
502 */
503 .max_unroll_iterations = 29,
504 };
505
506 static const nir_shader_compiler_options r500_fs_compiler_options = {
507 COMMON_NIR_OPTIONS,
508 .lower_fpow = true, /* POW is only in the VS */
509 .has_fused_comp_and_csel = true,
510
511 /* Have HW loops support and 512 max instr count, but don't unroll *too*
512 * hard.
513 */
514 .max_unroll_iterations = 32,
515 };
516
517 static const nir_shader_compiler_options r300_vs_compiler_options = {
518 COMMON_NIR_OPTIONS,
519 .lower_fsat = true, /* No fsat in pre-r500 VS */
520 .lower_sincos = true,
521
522 /* Note: has HW loops support, but only 256 ALU instructions. */
523 .max_unroll_iterations = 32,
524 };
525
526 static const nir_shader_compiler_options r400_vs_compiler_options = {
527 COMMON_NIR_OPTIONS,
528 .lower_fsat = true, /* No fsat in pre-r500 VS */
529
530 /* Note: has HW loops support, but only 256 ALU instructions. */
531 .max_unroll_iterations = 32,
532 };
533
534 static const nir_shader_compiler_options r300_fs_compiler_options = {
535 COMMON_NIR_OPTIONS,
536 .lower_fpow = true, /* POW is only in the VS */
537 .lower_sincos = true,
538 .has_fused_comp_and_csel = true,
539
540 /* No HW loops support, so set it equal to ALU instr max */
541 .max_unroll_iterations = 64,
542 };
543
544 static const void *
r300_get_compiler_options(struct pipe_screen * pscreen,enum pipe_shader_ir ir,enum pipe_shader_type shader)545 r300_get_compiler_options(struct pipe_screen *pscreen,
546 enum pipe_shader_ir ir,
547 enum pipe_shader_type shader)
548 {
549 struct r300_screen* r300screen = r300_screen(pscreen);
550
551 assert(ir == PIPE_SHADER_IR_NIR);
552
553 if (r300screen->caps.is_r500) {
554 if (shader == PIPE_SHADER_VERTEX)
555 return &r500_vs_compiler_options;
556 else
557 return &r500_fs_compiler_options;
558 } else {
559 if (shader == PIPE_SHADER_VERTEX) {
560 if (r300screen->caps.is_r400)
561 return &r400_vs_compiler_options;
562
563 return &r300_vs_compiler_options;
564 } else {
565 return &r300_fs_compiler_options;
566 }
567 }
568 }
569
570 /**
571 * Whether the format matches:
572 * PIPE_FORMAT_?10?10?10?2_UNORM
573 */
574 static inline bool
util_format_is_rgba1010102_variant(const struct util_format_description * desc)575 util_format_is_rgba1010102_variant(const struct util_format_description *desc)
576 {
577 static const unsigned size[4] = {10, 10, 10, 2};
578 unsigned chan;
579
580 if (desc->block.width != 1 ||
581 desc->block.height != 1 ||
582 desc->block.bits != 32)
583 return false;
584
585 for (chan = 0; chan < 4; ++chan) {
586 if(desc->channel[chan].type != UTIL_FORMAT_TYPE_UNSIGNED &&
587 desc->channel[chan].type != UTIL_FORMAT_TYPE_VOID)
588 return false;
589 if (desc->channel[chan].size != size[chan])
590 return false;
591 }
592
593 return true;
594 }
595
r300_is_blending_supported(struct r300_screen * rscreen,enum pipe_format format)596 static bool r300_is_blending_supported(struct r300_screen *rscreen,
597 enum pipe_format format)
598 {
599 int c;
600 const struct util_format_description *desc =
601 util_format_description(format);
602
603 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
604 return false;
605
606 c = util_format_get_first_non_void_channel(format);
607
608 /* RGBA16F */
609 if (rscreen->caps.is_r500 &&
610 desc->nr_channels == 4 &&
611 desc->channel[c].size == 16 &&
612 desc->channel[c].type == UTIL_FORMAT_TYPE_FLOAT)
613 return true;
614
615 if (desc->channel[c].normalized &&
616 desc->channel[c].type == UTIL_FORMAT_TYPE_UNSIGNED &&
617 desc->channel[c].size >= 4 &&
618 desc->channel[c].size <= 10) {
619 /* RGB10_A2, RGBA8, RGB5_A1, RGBA4, RGB565 */
620 if (desc->nr_channels >= 3)
621 return true;
622
623 if (format == PIPE_FORMAT_R8G8_UNORM)
624 return true;
625
626 /* R8, I8, L8, A8 */
627 if (desc->nr_channels == 1)
628 return true;
629 }
630
631 return false;
632 }
633
r300_is_format_supported(struct pipe_screen * screen,enum pipe_format format,enum pipe_texture_target target,unsigned sample_count,unsigned storage_sample_count,unsigned usage)634 static bool r300_is_format_supported(struct pipe_screen* screen,
635 enum pipe_format format,
636 enum pipe_texture_target target,
637 unsigned sample_count,
638 unsigned storage_sample_count,
639 unsigned usage)
640 {
641 uint32_t retval = 0;
642 bool is_r500 = r300_screen(screen)->caps.is_r500;
643 bool is_r400 = r300_screen(screen)->caps.is_r400;
644 bool is_color2101010 = format == PIPE_FORMAT_R10G10B10A2_UNORM ||
645 format == PIPE_FORMAT_R10G10B10X2_SNORM ||
646 format == PIPE_FORMAT_B10G10R10A2_UNORM ||
647 format == PIPE_FORMAT_B10G10R10X2_UNORM ||
648 format == PIPE_FORMAT_R10SG10SB10SA2U_NORM;
649 bool is_ati1n = format == PIPE_FORMAT_RGTC1_UNORM ||
650 format == PIPE_FORMAT_RGTC1_SNORM ||
651 format == PIPE_FORMAT_LATC1_UNORM ||
652 format == PIPE_FORMAT_LATC1_SNORM;
653 bool is_ati2n = format == PIPE_FORMAT_RGTC2_UNORM ||
654 format == PIPE_FORMAT_RGTC2_SNORM ||
655 format == PIPE_FORMAT_LATC2_UNORM ||
656 format == PIPE_FORMAT_LATC2_SNORM;
657 bool is_half_float = format == PIPE_FORMAT_R16_FLOAT ||
658 format == PIPE_FORMAT_R16G16_FLOAT ||
659 format == PIPE_FORMAT_R16G16B16_FLOAT ||
660 format == PIPE_FORMAT_R16G16B16A16_FLOAT ||
661 format == PIPE_FORMAT_R16G16B16X16_FLOAT;
662 const struct util_format_description *desc;
663
664 if (MAX2(1, sample_count) != MAX2(1, storage_sample_count))
665 return false;
666
667 /* Check multisampling support. */
668 switch (sample_count) {
669 case 0:
670 case 1:
671 break;
672 case 2:
673 case 4:
674 case 6:
675 /* No texturing and scanout. */
676 if (usage & (PIPE_BIND_SAMPLER_VIEW |
677 PIPE_BIND_DISPLAY_TARGET |
678 PIPE_BIND_SCANOUT)) {
679 return false;
680 }
681
682 desc = util_format_description(format);
683
684 if (is_r500) {
685 /* Only allow depth/stencil, RGBA8, RGBA1010102, RGBA16F. */
686 if (!util_format_is_depth_or_stencil(format) &&
687 !util_format_is_rgba8_variant(desc) &&
688 !util_format_is_rgba1010102_variant(desc) &&
689 format != PIPE_FORMAT_R16G16B16A16_FLOAT &&
690 format != PIPE_FORMAT_R16G16B16X16_FLOAT) {
691 return false;
692 }
693 } else {
694 /* Only allow depth/stencil, RGBA8. */
695 if (!util_format_is_depth_or_stencil(format) &&
696 !util_format_is_rgba8_variant(desc)) {
697 return false;
698 }
699 }
700 break;
701 default:
702 return false;
703 }
704
705 /* Check sampler format support. */
706 if ((usage & PIPE_BIND_SAMPLER_VIEW) &&
707 /* these two are broken for an unknown reason */
708 format != PIPE_FORMAT_R8G8B8X8_SNORM &&
709 format != PIPE_FORMAT_R16G16B16X16_SNORM &&
710 /* ATI1N is r5xx-only. */
711 (is_r500 || !is_ati1n) &&
712 /* ATI2N is supported on r4xx-r5xx. */
713 (is_r400 || is_r500 || !is_ati2n) &&
714 r300_is_sampler_format_supported(format)) {
715 retval |= PIPE_BIND_SAMPLER_VIEW;
716 }
717
718 /* Check colorbuffer format support. */
719 if ((usage & (PIPE_BIND_RENDER_TARGET |
720 PIPE_BIND_DISPLAY_TARGET |
721 PIPE_BIND_SCANOUT |
722 PIPE_BIND_SHARED |
723 PIPE_BIND_BLENDABLE)) &&
724 /* 2101010 cannot be rendered to on non-r5xx. */
725 (!is_color2101010 || is_r500) &&
726 r300_is_colorbuffer_format_supported(format)) {
727 retval |= usage &
728 (PIPE_BIND_RENDER_TARGET |
729 PIPE_BIND_DISPLAY_TARGET |
730 PIPE_BIND_SCANOUT |
731 PIPE_BIND_SHARED);
732
733 if (r300_is_blending_supported(r300_screen(screen), format)) {
734 retval |= usage & PIPE_BIND_BLENDABLE;
735 }
736 }
737
738 /* Check depth-stencil format support. */
739 if (usage & PIPE_BIND_DEPTH_STENCIL &&
740 r300_is_zs_format_supported(format)) {
741 retval |= PIPE_BIND_DEPTH_STENCIL;
742 }
743
744 /* Check vertex buffer format support. */
745 if (usage & PIPE_BIND_VERTEX_BUFFER) {
746 if (r300_screen(screen)->caps.has_tcl) {
747 /* Half float is supported on >= R400. */
748 if ((is_r400 || is_r500 || !is_half_float) &&
749 r300_translate_vertex_data_type(format) != R300_INVALID_FORMAT) {
750 retval |= PIPE_BIND_VERTEX_BUFFER;
751 }
752 } else {
753 /* SW TCL */
754 if (!util_format_is_pure_integer(format)) {
755 retval |= PIPE_BIND_VERTEX_BUFFER;
756 }
757 }
758 }
759
760 if (usage & PIPE_BIND_INDEX_BUFFER) {
761 if (format == PIPE_FORMAT_R8_UINT ||
762 format == PIPE_FORMAT_R16_UINT ||
763 format == PIPE_FORMAT_R32_UINT)
764 retval |= PIPE_BIND_INDEX_BUFFER;
765 }
766
767 return retval == usage;
768 }
769
r300_destroy_screen(struct pipe_screen * pscreen)770 static void r300_destroy_screen(struct pipe_screen* pscreen)
771 {
772 struct r300_screen* r300screen = r300_screen(pscreen);
773 struct radeon_winsys *rws = radeon_winsys(pscreen);
774
775 if (rws && !rws->unref(rws))
776 return;
777
778 mtx_destroy(&r300screen->cmask_mutex);
779 slab_destroy_parent(&r300screen->pool_transfers);
780
781 disk_cache_destroy(r300screen->disk_shader_cache);
782
783 if (rws)
784 rws->destroy(rws);
785
786 FREE(r300screen);
787 }
788
r300_fence_reference(struct pipe_screen * screen,struct pipe_fence_handle ** ptr,struct pipe_fence_handle * fence)789 static void r300_fence_reference(struct pipe_screen *screen,
790 struct pipe_fence_handle **ptr,
791 struct pipe_fence_handle *fence)
792 {
793 struct radeon_winsys *rws = r300_screen(screen)->rws;
794
795 rws->fence_reference(rws, ptr, fence);
796 }
797
r300_fence_finish(struct pipe_screen * screen,struct pipe_context * ctx,struct pipe_fence_handle * fence,uint64_t timeout)798 static bool r300_fence_finish(struct pipe_screen *screen,
799 struct pipe_context *ctx,
800 struct pipe_fence_handle *fence,
801 uint64_t timeout)
802 {
803 struct radeon_winsys *rws = r300_screen(screen)->rws;
804
805 return rws->fence_wait(rws, fence, timeout);
806 }
807
r300_screen_get_fd(struct pipe_screen * screen)808 static int r300_screen_get_fd(struct pipe_screen *screen)
809 {
810 struct radeon_winsys *rws = r300_screen(screen)->rws;
811
812 return rws->get_fd(rws);
813 }
814
r300_screen_create(struct radeon_winsys * rws,const struct pipe_screen_config * config)815 struct pipe_screen* r300_screen_create(struct radeon_winsys *rws,
816 const struct pipe_screen_config *config)
817 {
818 struct r300_screen *r300screen = CALLOC_STRUCT(r300_screen);
819
820 if (!r300screen) {
821 FREE(r300screen);
822 return NULL;
823 }
824
825 rws->query_info(rws, &r300screen->info);
826
827 r300_init_debug(r300screen);
828 r300_parse_chipset(r300screen->info.pci_id, &r300screen->caps);
829
830 driParseConfigFiles(config->options, config->options_info, 0, "r300", NULL,
831 NULL, NULL, 0, NULL, 0);
832
833 #define OPT_BOOL(name, dflt, description) \
834 r300screen->options.name = driQueryOptionb(config->options, "r300_" #name);
835 #include "r300_debug_options.h"
836
837 if (SCREEN_DBG_ON(r300screen, DBG_NO_ZMASK) ||
838 r300screen->options.nozmask)
839 r300screen->caps.zmask_ram = 0;
840 if (SCREEN_DBG_ON(r300screen, DBG_NO_HIZ) ||
841 r300screen->options.nohiz)
842 r300screen->caps.hiz_ram = 0;
843 if (SCREEN_DBG_ON(r300screen, DBG_NO_TCL))
844 r300screen->caps.has_tcl = false;
845
846 r300screen->rws = rws;
847 r300screen->screen.destroy = r300_destroy_screen;
848 r300screen->screen.get_name = r300_get_name;
849 r300screen->screen.get_vendor = r300_get_vendor;
850 r300screen->screen.get_compiler_options = r300_get_compiler_options;
851 r300screen->screen.finalize_nir = r300_finalize_nir;
852 r300screen->screen.get_device_vendor = r300_get_device_vendor;
853 r300screen->screen.get_disk_shader_cache = r300_get_disk_shader_cache;
854 r300screen->screen.get_screen_fd = r300_screen_get_fd;
855 r300screen->screen.get_param = r300_get_param;
856 r300screen->screen.get_shader_param = r300_get_shader_param;
857 r300screen->screen.get_paramf = r300_get_paramf;
858 r300screen->screen.get_video_param = r300_get_video_param;
859 r300screen->screen.is_format_supported = r300_is_format_supported;
860 r300screen->screen.is_video_format_supported = vl_video_buffer_is_format_supported;
861 r300screen->screen.context_create = r300_create_context;
862 r300screen->screen.fence_reference = r300_fence_reference;
863 r300screen->screen.fence_finish = r300_fence_finish;
864
865 r300_init_screen_resource_functions(r300screen);
866
867 r300_disk_cache_create(r300screen);
868
869 slab_create_parent(&r300screen->pool_transfers, sizeof(struct pipe_transfer), 64);
870
871 (void) mtx_init(&r300screen->cmask_mutex, mtx_plain);
872
873 return &r300screen->screen;
874 }
875