xref: /aosp_15_r20/external/mesa3d/src/gallium/drivers/r300/r300_emit.c (revision 6104692788411f58d303aa86923a9ff6ecaded22) 
1 /*
2  * Copyright 2008 Corbin Simpson <[email protected]>
3  * Copyright 2009 Marek Olšák <[email protected]>
4  * SPDX-License-Identifier: MIT
5  */
6 
7 /* r300_emit: Functions for emitting state. */
8 
9 #include "util/format/u_format.h"
10 #include "util/u_math.h"
11 
12 #include "r300_context.h"
13 #include "r300_cb.h"
14 #include "r300_cs.h"
15 #include "r300_emit.h"
16 #include "r300_fs.h"
17 #include "r300_screen.h"
18 #include "r300_screen_buffer.h"
19 #include "r300_vs.h"
20 
r300_emit_blend_state(struct r300_context * r300,unsigned size,void * state)21 void r300_emit_blend_state(struct r300_context* r300,
22                            unsigned size, void* state)
23 {
24     struct r300_blend_state* blend = (struct r300_blend_state*)state;
25     struct pipe_framebuffer_state* fb =
26         (struct pipe_framebuffer_state*)r300->fb_state.state;
27     struct pipe_surface *cb;
28     CS_LOCALS(r300);
29 
30     cb = fb->nr_cbufs ? r300_get_nonnull_cb(fb, 0) : NULL;
31 
32     if (cb) {
33         if (cb->format == PIPE_FORMAT_R16G16B16A16_FLOAT) {
34             WRITE_CS_TABLE(blend->cb_noclamp, size);
35         } else if (cb->format == PIPE_FORMAT_R16G16B16X16_FLOAT) {
36             WRITE_CS_TABLE(blend->cb_noclamp_noalpha, size);
37         } else {
38             unsigned swz = r300_surface(cb)->colormask_swizzle;
39             WRITE_CS_TABLE(blend->cb_clamp[swz], size);
40         }
41     } else {
42         WRITE_CS_TABLE(blend->cb_no_readwrite, size);
43     }
44 }
45 
r300_emit_blend_color_state(struct r300_context * r300,unsigned size,void * state)46 void r300_emit_blend_color_state(struct r300_context* r300,
47                                  unsigned size, void* state)
48 {
49     struct r300_blend_color_state* bc = (struct r300_blend_color_state*)state;
50     CS_LOCALS(r300);
51 
52     WRITE_CS_TABLE(bc->cb, size);
53 }
54 
r300_emit_clip_state(struct r300_context * r300,unsigned size,void * state)55 void r300_emit_clip_state(struct r300_context* r300,
56                           unsigned size, void* state)
57 {
58     struct r300_clip_state* clip = (struct r300_clip_state*)state;
59     CS_LOCALS(r300);
60 
61     WRITE_CS_TABLE(clip->cb, size);
62 }
63 
r300_emit_dsa_state(struct r300_context * r300,unsigned size,void * state)64 void r300_emit_dsa_state(struct r300_context* r300, unsigned size, void* state)
65 {
66     struct r300_dsa_state* dsa = (struct r300_dsa_state*)state;
67     struct pipe_framebuffer_state* fb =
68         (struct pipe_framebuffer_state*)r300->fb_state.state;
69     bool is_r500 = r300->screen->caps.is_r500;
70     CS_LOCALS(r300);
71     uint32_t alpha_func = dsa->alpha_function;
72 
73     /* Choose the alpha ref value between 8-bit (FG_ALPHA_FUNC.AM_VAL) and
74      * 16-bit (FG_ALPHA_VALUE). */
75     if (is_r500 && (alpha_func & R300_FG_ALPHA_FUNC_ENABLE)) {
76         struct pipe_surface *cb = fb->nr_cbufs ? r300_get_nonnull_cb(fb, 0) : NULL;
77 
78         if (cb &&
79             (cb->format == PIPE_FORMAT_R16G16B16A16_FLOAT ||
80              cb->format == PIPE_FORMAT_R16G16B16X16_FLOAT)) {
81             alpha_func |= R500_FG_ALPHA_FUNC_FP16_ENABLE;
82         } else {
83             alpha_func |= R500_FG_ALPHA_FUNC_8BIT;
84         }
85     }
86 
87     /* Setup alpha-to-coverage. */
88     if (r300->alpha_to_coverage && r300->msaa_enable) {
89         /* Always set 3/6, it improves precision even for 2x and 4x MSAA. */
90         alpha_func |= R300_FG_ALPHA_FUNC_MASK_ENABLE |
91                       R300_FG_ALPHA_FUNC_CFG_3_OF_6;
92     }
93 
94     BEGIN_CS(size);
95     OUT_CS_REG(R300_FG_ALPHA_FUNC, alpha_func);
96     OUT_CS_TABLE(fb->zsbuf ? &dsa->cb_begin : dsa->cb_zb_no_readwrite, size-2);
97     END_CS;
98 }
99 
get_rc_constant_state(float vec[4],struct r300_context * r300,struct rc_constant * constant)100 static void get_rc_constant_state(
101     float vec[4],
102     struct r300_context * r300,
103     struct rc_constant * constant)
104 {
105     struct r300_textures_state* texstate = r300->textures_state.state;
106     struct r300_resource *tex;
107 
108     assert(constant->Type == RC_CONSTANT_STATE);
109 
110     /* vec should either be (0, 0, 0, 1), which should be a relatively safe
111      * RGBA or STRQ value, or it could be one of the RC_CONSTANT_STATE
112      * state factors. */
113 
114     switch (constant->u.State[0]) {
115         /* Factor for converting rectangle coords to
116          * normalized coords. Should only show up on non-r500. */
117         case RC_STATE_R300_TEXRECT_FACTOR:
118             tex = r300_resource(texstate->sampler_views[constant->u.State[1]]->base.texture);
119             vec[0] = 1.0 / tex->tex.width0;
120             vec[1] = 1.0 / tex->tex.height0;
121             vec[2] = 0;
122             vec[3] = 1;
123             break;
124 
125         case RC_STATE_R300_TEXSCALE_FACTOR:
126             tex = r300_resource(texstate->sampler_views[constant->u.State[1]]->base.texture);
127             /* Add a small number to the texture size to work around rounding errors in hw. */
128             vec[0] = tex->b.width0  / (tex->tex.width0  + 0.001f);
129             vec[1] = tex->b.height0 / (tex->tex.height0 + 0.001f);
130             vec[2] = tex->b.depth0  / (tex->tex.depth0  + 0.001f);
131             vec[3] = 1;
132             break;
133 
134         case RC_STATE_R300_VIEWPORT_SCALE:
135             vec[0] = r300->viewport.scale[0];
136             vec[1] = r300->viewport.scale[1];
137             vec[2] = r300->viewport.scale[2];
138             vec[3] = 1;
139             break;
140 
141         case RC_STATE_R300_VIEWPORT_OFFSET:
142             vec[0] = r300->viewport.translate[0];
143             vec[1] = r300->viewport.translate[1];
144             vec[2] = r300->viewport.translate[2];
145             vec[3] = 1;
146             break;
147 
148         default:
149             fprintf(stderr, "r300: Implementation error: "
150                 "Unknown RC_CONSTANT type %d\n", constant->u.State[0]);
151             vec[0] = 0;
152             vec[1] = 0;
153             vec[2] = 0;
154             vec[3] = 1;
155     }
156 }
157 
158 /* Convert a normal single-precision float into the 7.16 format
159  * used by the R300 fragment shader.
160  */
pack_float24(float f)161 uint32_t pack_float24(float f)
162 {
163     union {
164         float fl;
165         uint32_t u;
166     } u;
167     float mantissa;
168     int exponent;
169     uint32_t float24 = 0;
170 
171     if (f == 0.0)
172         return 0;
173 
174     u.fl = f;
175 
176     mantissa = frexpf(f, &exponent);
177 
178     /* Handle -ve */
179     if (mantissa < 0) {
180         float24 |= (1 << 23);
181         mantissa = mantissa * -1.0;
182     }
183     /* Handle exponent, bias of 63 */
184     exponent += 62;
185     float24 |= (exponent << 16);
186     /* Kill 7 LSB of mantissa */
187     float24 |= (u.u & 0x7FFFFF) >> 7;
188 
189     return float24;
190 }
191 
r300_emit_fs(struct r300_context * r300,unsigned size,void * state)192 void r300_emit_fs(struct r300_context* r300, unsigned size, void *state)
193 {
194     struct r300_fragment_shader *fs = r300_fs(r300);
195     CS_LOCALS(r300);
196 
197     WRITE_CS_TABLE(fs->shader->cb_code, fs->shader->cb_code_size);
198 }
199 
r300_emit_fs_constants(struct r300_context * r300,unsigned size,void * state)200 void r300_emit_fs_constants(struct r300_context* r300, unsigned size, void *state)
201 {
202     struct r300_fragment_shader *fs = r300_fs(r300);
203     struct r300_constant_buffer *buf = (struct r300_constant_buffer*)state;
204     unsigned count = fs->shader->externals_count;
205     unsigned i, j;
206     CS_LOCALS(r300);
207 
208     if (count == 0)
209         return;
210 
211     BEGIN_CS(size);
212     OUT_CS_REG_SEQ(R300_PFS_PARAM_0_X, count * 4);
213     if (buf->remap_table){
214         for (i = 0; i < count; i++) {
215             for (j = 0; j < 4; j++) {
216                 unsigned swz = buf->remap_table[i].swizzle[j];
217                 unsigned index = buf->remap_table[i].index[j];
218                 if (index == -1)
219                     OUT_CS(pack_float24(0.0f));
220                 else {
221                     OUT_CS(pack_float24(*(float*)&buf->ptr[index * 4 + swz]));
222                 }
223             }
224         }
225     } else {
226         for (i = 0; i < count; i++)
227             for (j = 0; j < 4; j++)
228                 OUT_CS(pack_float24(*(float*)&buf->ptr[i*4+j]));
229     }
230 
231     END_CS;
232 }
233 
r300_emit_fs_rc_constant_state(struct r300_context * r300,unsigned size,void * state)234 void r300_emit_fs_rc_constant_state(struct r300_context* r300, unsigned size, void *state)
235 {
236     struct r300_fragment_shader *fs = r300_fs(r300);
237     struct rc_constant_list *constants = &fs->shader->code.constants;
238     unsigned i;
239     unsigned count = fs->shader->rc_state_count;
240     unsigned first = fs->shader->externals_count;
241     unsigned end = constants->Count;
242     unsigned j;
243     CS_LOCALS(r300);
244 
245     if (count == 0)
246         return;
247 
248     BEGIN_CS(size);
249     for(i = first; i < end; ++i) {
250         if (constants->Constants[i].Type == RC_CONSTANT_STATE) {
251             float data[4];
252 
253             get_rc_constant_state(data, r300, &constants->Constants[i]);
254 
255             OUT_CS_REG_SEQ(R300_PFS_PARAM_0_X + i * 16, 4);
256             for (j = 0; j < 4; j++)
257                 OUT_CS(pack_float24(data[j]));
258         }
259     }
260     END_CS;
261 }
262 
r500_emit_fs(struct r300_context * r300,unsigned size,void * state)263 void r500_emit_fs(struct r300_context* r300, unsigned size, void *state)
264 {
265     struct r300_fragment_shader *fs = r300_fs(r300);
266     CS_LOCALS(r300);
267 
268     WRITE_CS_TABLE(fs->shader->cb_code, fs->shader->cb_code_size);
269 }
270 
r500_emit_fs_constants(struct r300_context * r300,unsigned size,void * state)271 void r500_emit_fs_constants(struct r300_context* r300, unsigned size, void *state)
272 {
273     struct r300_fragment_shader *fs = r300_fs(r300);
274     struct r300_constant_buffer *buf = (struct r300_constant_buffer*)state;
275     unsigned count = fs->shader->externals_count;
276     CS_LOCALS(r300);
277 
278     if (count == 0)
279         return;
280 
281     BEGIN_CS(size);
282     OUT_CS_REG(R500_GA_US_VECTOR_INDEX, R500_GA_US_VECTOR_INDEX_TYPE_CONST);
283     OUT_CS_ONE_REG(R500_GA_US_VECTOR_DATA, count * 4);
284     if (buf->remap_table){
285         for (unsigned i = 0; i < count; i++) {
286             uint32_t data[4] = {};
287             for (unsigned chan = 0; chan < 4; chan++){
288                 if (buf->remap_table[i].swizzle[chan] != RC_SWIZZLE_UNUSED)
289                 data[chan] = buf->ptr[buf->remap_table[i].index[chan] * 4 + buf->remap_table[i].swizzle[chan]];
290             }
291             OUT_CS_TABLE(data, 4);
292         }
293     } else {
294         OUT_CS_TABLE(buf->ptr, count * 4);
295     }
296     END_CS;
297 }
298 
r500_emit_fs_rc_constant_state(struct r300_context * r300,unsigned size,void * state)299 void r500_emit_fs_rc_constant_state(struct r300_context* r300, unsigned size, void *state)
300 {
301     struct r300_fragment_shader *fs = r300_fs(r300);
302     struct rc_constant_list *constants = &fs->shader->code.constants;
303     unsigned i;
304     unsigned count = fs->shader->rc_state_count;
305     unsigned first = fs->shader->externals_count;
306     unsigned end = constants->Count;
307     CS_LOCALS(r300);
308 
309     if (count == 0)
310         return;
311 
312     BEGIN_CS(size);
313     for(i = first; i < end; ++i) {
314         if (constants->Constants[i].Type == RC_CONSTANT_STATE) {
315             float data[4];
316 
317             get_rc_constant_state(data, r300, &constants->Constants[i]);
318 
319             OUT_CS_REG(R500_GA_US_VECTOR_INDEX,
320                        R500_GA_US_VECTOR_INDEX_TYPE_CONST |
321                        (i & R500_GA_US_VECTOR_INDEX_MASK));
322             OUT_CS_ONE_REG(R500_GA_US_VECTOR_DATA, 4);
323             OUT_CS_TABLE(data, 4);
324         }
325     }
326     END_CS;
327 }
328 
r300_emit_gpu_flush(struct r300_context * r300,unsigned size,void * state)329 void r300_emit_gpu_flush(struct r300_context *r300, unsigned size, void *state)
330 {
331     struct r300_gpu_flush *gpuflush = (struct r300_gpu_flush*)state;
332     struct pipe_framebuffer_state* fb =
333             (struct pipe_framebuffer_state*)r300->fb_state.state;
334     uint32_t height = fb->height;
335     uint32_t width = fb->width;
336     CS_LOCALS(r300);
337 
338     if (r300->cbzb_clear) {
339         struct r300_surface *surf = r300_surface(fb->cbufs[0]);
340 
341         height = surf->cbzb_height;
342         width = surf->cbzb_width;
343     }
344 
345     DBG(r300, DBG_SCISSOR,
346 	"r300: Scissor width: %i, height: %i, CBZB clear: %s\n",
347 	width, height, r300->cbzb_clear ? "YES" : "NO");
348 
349     BEGIN_CS(size);
350 
351     /* Set up scissors.
352      * By writing to the SC registers, SC & US assert idle. */
353     OUT_CS_REG_SEQ(R300_SC_SCISSORS_TL, 2);
354     if (r300->screen->caps.is_r500) {
355         OUT_CS(0);
356         OUT_CS(((width  - 1) << R300_SCISSORS_X_SHIFT) |
357                ((height - 1) << R300_SCISSORS_Y_SHIFT));
358     } else {
359         OUT_CS((1440 << R300_SCISSORS_X_SHIFT) |
360                (1440 << R300_SCISSORS_Y_SHIFT));
361         OUT_CS(((width  + 1440-1) << R300_SCISSORS_X_SHIFT) |
362                ((height + 1440-1) << R300_SCISSORS_Y_SHIFT));
363     }
364 
365     /* Flush CB & ZB caches and wait until the 3D engine is idle and clean. */
366     OUT_CS_TABLE(gpuflush->cb_flush_clean, 6);
367     END_CS;
368 }
369 
r300_emit_aa_state(struct r300_context * r300,unsigned size,void * state)370 void r300_emit_aa_state(struct r300_context *r300, unsigned size, void *state)
371 {
372     struct r300_aa_state *aa = (struct r300_aa_state*)state;
373     CS_LOCALS(r300);
374 
375     BEGIN_CS(size);
376     OUT_CS_REG(R300_GB_AA_CONFIG, aa->aa_config);
377 
378     if (aa->dest) {
379         OUT_CS_REG_SEQ(R300_RB3D_AARESOLVE_OFFSET, 3);
380         OUT_CS(aa->dest->offset);
381         OUT_CS(aa->dest->pitch & R300_RB3D_AARESOLVE_PITCH_MASK);
382         OUT_CS(R300_RB3D_AARESOLVE_CTL_AARESOLVE_MODE_RESOLVE |
383                R300_RB3D_AARESOLVE_CTL_AARESOLVE_ALPHA_AVERAGE);
384         OUT_CS_RELOC(aa->dest);
385     } else {
386         OUT_CS_REG(R300_RB3D_AARESOLVE_CTL, 0);
387     }
388 
389     END_CS;
390 }
391 
r300_emit_fb_state(struct r300_context * r300,unsigned size,void * state)392 void r300_emit_fb_state(struct r300_context* r300, unsigned size, void* state)
393 {
394     struct pipe_framebuffer_state* fb = (struct pipe_framebuffer_state*)state;
395     struct r300_surface* surf;
396     unsigned i;
397     uint32_t rb3d_cctl = 0;
398 
399     CS_LOCALS(r300);
400 
401     BEGIN_CS(size);
402 
403     if (r300->screen->caps.is_r500) {
404         rb3d_cctl = R300_RB3D_CCTL_INDEPENDENT_COLORFORMAT_ENABLE_ENABLE;
405     }
406     /* NUM_MULTIWRITES replicates COLOR[0] to all colorbuffers. */
407     if (fb->nr_cbufs && r300->fb_multiwrite) {
408         rb3d_cctl |= R300_RB3D_CCTL_NUM_MULTIWRITES(fb->nr_cbufs);
409     }
410     if (r300->cmask_in_use) {
411         rb3d_cctl |= R300_RB3D_CCTL_AA_COMPRESSION_ENABLE |
412                      R300_RB3D_CCTL_CMASK_ENABLE;
413     }
414 
415     OUT_CS_REG(R300_RB3D_CCTL, rb3d_cctl);
416 
417     /* Set up colorbuffers. */
418     for (i = 0; i < fb->nr_cbufs; i++) {
419         surf = r300_surface(r300_get_nonnull_cb(fb, i));
420 
421         OUT_CS_REG(R300_RB3D_COLOROFFSET0 + (4 * i), surf->offset);
422         OUT_CS_RELOC(surf);
423 
424         OUT_CS_REG(R300_RB3D_COLORPITCH0 + (4 * i), surf->pitch);
425         OUT_CS_RELOC(surf);
426 
427         if (r300->cmask_in_use && i == 0) {
428             OUT_CS_REG(R300_RB3D_CMASK_OFFSET0, 0);
429             OUT_CS_REG(R300_RB3D_CMASK_PITCH0, surf->pitch_cmask);
430             OUT_CS_REG(R300_RB3D_COLOR_CLEAR_VALUE, r300->color_clear_value);
431             if (r300->screen->caps.is_r500) {
432                 OUT_CS_REG_SEQ(R500_RB3D_COLOR_CLEAR_VALUE_AR, 2);
433                 OUT_CS(r300->color_clear_value_ar);
434                 OUT_CS(r300->color_clear_value_gb);
435             }
436         }
437     }
438 
439     /* Set up the ZB part of the CBZB clear. */
440     if (r300->cbzb_clear) {
441         surf = r300_surface(fb->cbufs[0]);
442 
443         OUT_CS_REG(R300_ZB_FORMAT, surf->cbzb_format);
444 
445         OUT_CS_REG(R300_ZB_DEPTHOFFSET, surf->cbzb_midpoint_offset);
446         OUT_CS_RELOC(surf);
447 
448         OUT_CS_REG(R300_ZB_DEPTHPITCH, surf->cbzb_pitch);
449         OUT_CS_RELOC(surf);
450 
451         DBG(r300, DBG_CBZB,
452             "CBZB clearing cbuf %08x %08x\n", surf->cbzb_format,
453             surf->cbzb_pitch);
454     }
455     /* Set up a zbuffer. */
456     else if (fb->zsbuf) {
457         surf = r300_surface(fb->zsbuf);
458 
459         OUT_CS_REG(R300_ZB_FORMAT, surf->format);
460 
461         OUT_CS_REG(R300_ZB_DEPTHOFFSET, surf->offset);
462         OUT_CS_RELOC(surf);
463 
464         OUT_CS_REG(R300_ZB_DEPTHPITCH, surf->pitch);
465         OUT_CS_RELOC(surf);
466 
467         if (r300->hyperz_enabled) {
468             /* HiZ RAM. */
469             OUT_CS_REG(R300_ZB_HIZ_OFFSET, 0);
470             OUT_CS_REG(R300_ZB_HIZ_PITCH, surf->pitch_hiz);
471             /* Z Mask RAM. (compressed zbuffer) */
472             OUT_CS_REG(R300_ZB_ZMASK_OFFSET, 0);
473             OUT_CS_REG(R300_ZB_ZMASK_PITCH, surf->pitch_zmask);
474         }
475     }
476 
477     END_CS;
478 }
479 
r300_emit_hyperz_state(struct r300_context * r300,unsigned size,void * state)480 void r300_emit_hyperz_state(struct r300_context *r300,
481                             unsigned size, void *state)
482 {
483     struct r300_hyperz_state *z = state;
484     CS_LOCALS(r300);
485 
486     if (z->flush)
487         WRITE_CS_TABLE(&z->cb_flush_begin, size);
488     else
489         WRITE_CS_TABLE(&z->cb_begin, size - 2);
490 }
491 
r300_emit_hyperz_end(struct r300_context * r300)492 void r300_emit_hyperz_end(struct r300_context *r300)
493 {
494     struct r300_hyperz_state z =
495             *(struct r300_hyperz_state*)r300->hyperz_state.state;
496 
497     z.flush = 1;
498     z.zb_bw_cntl = 0;
499     z.zb_depthclearvalue = 0;
500     z.sc_hyperz = R300_SC_HYPERZ_ADJ_2;
501     z.gb_z_peq_config = 0;
502 
503     r300_emit_hyperz_state(r300, r300->hyperz_state.size, &z);
504 }
505 
506 #define R300_NIBBLES(x0, y0, x1, y1, x2, y2, d0y, d0x)  \
507     (((x0) & 0xf) | (((y0) & 0xf) << 4) |		   \
508     (((x1) & 0xf) << 8) | (((y1) & 0xf) << 12) |	   \
509     (((x2) & 0xf) << 16) | (((y2) & 0xf) << 20) |	   \
510     (((d0y) & 0xf) << 24) | (((d0x) & 0xf) << 28))
511 
r300_get_mspos(int index,unsigned * p)512 static unsigned r300_get_mspos(int index, unsigned *p)
513 {
514     unsigned reg, i, distx, disty, dist;
515 
516     if (index == 0) {
517         /* MSPOS0 contains positions for samples 0,1,2 as (X,Y) pairs of nibbles,
518          * followed by a (Y,X) pair containing the minimum distance from the pixel
519          * edge:
520          *     X0, Y0, X1, Y1, X2, Y2, D0_Y, D0_X
521          *
522          * There is a quirk when setting D0_X. The value represents the distance
523          * from the left edge of the pixel quad to the first sample in subpixels.
524          * All values less than eight should use the actual value, but „7‟ should
525          * be used for the distance „8‟. The hardware will convert 7 into 8 internally.
526          */
527         distx = 11;
528         for (i = 0; i < 12; i += 2) {
529             if (p[i] < distx)
530                 distx = p[i];
531         }
532 
533         disty = 11;
534         for (i = 1; i < 12; i += 2) {
535             if (p[i] < disty)
536                 disty = p[i];
537         }
538 
539         if (distx == 8)
540             distx = 7;
541 
542         reg = R300_NIBBLES(p[0], p[1], p[2], p[3], p[4], p[5], disty, distx);
543     } else {
544         /* MSPOS1 contains positions for samples 3,4,5 as (X,Y) pairs of nibbles,
545          * followed by the minimum distance from the pixel edge (not sure if X or Y):
546          *     X3, Y3, X4, Y4, X5, Y5, D1
547          */
548         dist = 11;
549         for (i = 0; i < 12; i++) {
550             if (p[i] < dist)
551                 dist = p[i];
552         }
553 
554         reg = R300_NIBBLES(p[6], p[7], p[8], p[9], p[10], p[11], dist, 0);
555     }
556     return reg;
557 }
558 
r300_emit_fb_state_pipelined(struct r300_context * r300,unsigned size,void * state)559 void r300_emit_fb_state_pipelined(struct r300_context *r300,
560                                   unsigned size, void *state)
561 {
562     /* The sample coordinates are in the range [0,11], because
563      * GB_TILE_CONFIG.SUBPIXEL is set to the 1/12 subpixel precision.
564      *
565      * Some sample coordinates reach to neighboring pixels and should not be used.
566      * (e.g. Y=11)
567      *
568      * The unused samples must be set to the positions of other valid samples. */
569     static unsigned sample_locs_1x[12] = {
570         6,6,  6,6,  6,6,  6,6,  6,6,  6,6
571     };
572     static unsigned sample_locs_2x[12] = {
573         3,9,  9,3,  9,3,  9,3,  9,3,  9,3
574     };
575     static unsigned sample_locs_4x[12] = {
576         4,4,  8,8,  2,10,  10,2,  10,2,  10,2
577     };
578     static unsigned sample_locs_6x[12] = {
579         3,1,  7,3,  11,5,  1,7,  5,9,  9,10
580     };
581 
582     struct pipe_framebuffer_state* fb =
583             (struct pipe_framebuffer_state*)r300->fb_state.state;
584     unsigned i, num_cbufs = fb->nr_cbufs;
585     unsigned mspos0, mspos1;
586     CS_LOCALS(r300);
587 
588     /* If we use the multiwrite feature, the colorbuffers 2,3,4 must be
589      * marked as UNUSED in the US block. */
590     if (r300->fb_multiwrite) {
591         num_cbufs = MIN2(num_cbufs, 1);
592     }
593 
594     BEGIN_CS(size);
595 
596     /* Colorbuffer format in the US block.
597      * (must be written after unpipelined regs) */
598     OUT_CS_REG_SEQ(R300_US_OUT_FMT_0, 4);
599     for (i = 0; i < num_cbufs; i++) {
600         OUT_CS(r300_surface(r300_get_nonnull_cb(fb, i))->format);
601     }
602     for (; i < 1; i++) {
603         OUT_CS(R300_US_OUT_FMT_C4_8 |
604                R300_C0_SEL_B | R300_C1_SEL_G |
605                R300_C2_SEL_R | R300_C3_SEL_A);
606     }
607     for (; i < 4; i++) {
608         OUT_CS(R300_US_OUT_FMT_UNUSED);
609     }
610 
611     /* Set sample positions. It depends on the framebuffer sample count.
612      * These are pipelined regs and as such cannot be moved to the AA state.
613      */
614     switch (r300->num_samples) {
615     default:
616         mspos0 = r300_get_mspos(0, sample_locs_1x);
617         mspos1 = r300_get_mspos(1, sample_locs_1x);
618         break;
619     case 2:
620         mspos0 = r300_get_mspos(0, sample_locs_2x);
621         mspos1 = r300_get_mspos(1, sample_locs_2x);
622         break;
623     case 4:
624         mspos0 = r300_get_mspos(0, sample_locs_4x);
625         mspos1 = r300_get_mspos(1, sample_locs_4x);
626         break;
627     case 6:
628         mspos0 = r300_get_mspos(0, sample_locs_6x);
629         mspos1 = r300_get_mspos(1, sample_locs_6x);
630         break;
631     }
632 
633     OUT_CS_REG_SEQ(R300_GB_MSPOS0, 2);
634     OUT_CS(mspos0);
635     OUT_CS(mspos1);
636     END_CS;
637 }
638 
r300_emit_query_start(struct r300_context * r300,unsigned size,void * state)639 void r300_emit_query_start(struct r300_context *r300, unsigned size, void*state)
640 {
641     struct r300_query *query = r300->query_current;
642     CS_LOCALS(r300);
643 
644     if (!query)
645 	return;
646 
647     BEGIN_CS(size);
648     if (r300->screen->caps.family == CHIP_RV530) {
649         OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL);
650     } else {
651         OUT_CS_REG(R300_SU_REG_DEST, R300_RASTER_PIPE_SELECT_ALL);
652     }
653     OUT_CS_REG(R300_ZB_ZPASS_DATA, 0);
654     END_CS;
655     query->begin_emitted = true;
656 }
657 
r300_emit_query_end_frag_pipes(struct r300_context * r300,struct r300_query * query)658 static void r300_emit_query_end_frag_pipes(struct r300_context *r300,
659                                            struct r300_query *query)
660 {
661     struct r300_capabilities* caps = &r300->screen->caps;
662     uint32_t gb_pipes = r300->screen->info.r300_num_gb_pipes;
663     CS_LOCALS(r300);
664 
665     assert(gb_pipes);
666 
667     BEGIN_CS(6 * gb_pipes + 2);
668     /* I'm not so sure I like this switch, but it's hard to be elegant
669      * when there's so many special cases...
670      *
671      * So here's the basic idea. For each pipe, enable writes to it only,
672      * then put out the relocation for ZPASS_ADDR, taking into account a
673      * 4-byte offset for each pipe. RV380 and older are special; they have
674      * only two pipes, and the second pipe's enable is on bit 3, not bit 1,
675      * so there's a chipset cap for that. */
676     switch (gb_pipes) {
677         case 4:
678             /* pipe 3 only */
679             OUT_CS_REG(R300_SU_REG_DEST, 1 << 3);
680             OUT_CS_REG(R300_ZB_ZPASS_ADDR, (query->num_results + 3) * 4);
681             OUT_CS_RELOC(r300->query_current);
682             FALLTHROUGH;
683         case 3:
684             /* pipe 2 only */
685             OUT_CS_REG(R300_SU_REG_DEST, 1 << 2);
686             OUT_CS_REG(R300_ZB_ZPASS_ADDR, (query->num_results + 2) * 4);
687             OUT_CS_RELOC(r300->query_current);
688             FALLTHROUGH;
689         case 2:
690             /* pipe 1 only */
691             /* As mentioned above, accommodate RV380 and older. */
692             OUT_CS_REG(R300_SU_REG_DEST,
693                     1 << (caps->high_second_pipe ? 3 : 1));
694             OUT_CS_REG(R300_ZB_ZPASS_ADDR, (query->num_results + 1) * 4);
695             OUT_CS_RELOC(r300->query_current);
696             FALLTHROUGH;
697         case 1:
698             /* pipe 0 only */
699             OUT_CS_REG(R300_SU_REG_DEST, 1 << 0);
700             OUT_CS_REG(R300_ZB_ZPASS_ADDR, (query->num_results + 0) * 4);
701             OUT_CS_RELOC(r300->query_current);
702             break;
703         default:
704             fprintf(stderr, "r300: Implementation error: Chipset reports %d"
705                     " pixel pipes!\n", gb_pipes);
706             abort();
707     }
708 
709     /* And, finally, reset it to normal... */
710     OUT_CS_REG(R300_SU_REG_DEST, 0xF);
711     END_CS;
712 }
713 
rv530_emit_query_end_single_z(struct r300_context * r300,struct r300_query * query)714 static void rv530_emit_query_end_single_z(struct r300_context *r300,
715                                           struct r300_query *query)
716 {
717     CS_LOCALS(r300);
718 
719     BEGIN_CS(8);
720     OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_0);
721     OUT_CS_REG(R300_ZB_ZPASS_ADDR, query->num_results * 4);
722     OUT_CS_RELOC(r300->query_current);
723     OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL);
724     END_CS;
725 }
726 
rv530_emit_query_end_double_z(struct r300_context * r300,struct r300_query * query)727 static void rv530_emit_query_end_double_z(struct r300_context *r300,
728                                           struct r300_query *query)
729 {
730     CS_LOCALS(r300);
731 
732     BEGIN_CS(14);
733     OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_0);
734     OUT_CS_REG(R300_ZB_ZPASS_ADDR, (query->num_results + 0) * 4);
735     OUT_CS_RELOC(r300->query_current);
736     OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_1);
737     OUT_CS_REG(R300_ZB_ZPASS_ADDR, (query->num_results + 1) * 4);
738     OUT_CS_RELOC(r300->query_current);
739     OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL);
740     END_CS;
741 }
742 
r300_emit_query_end(struct r300_context * r300)743 void r300_emit_query_end(struct r300_context* r300)
744 {
745     struct r300_capabilities *caps = &r300->screen->caps;
746     struct r300_query *query = r300->query_current;
747 
748     if (!query)
749 	return;
750 
751     if (query->begin_emitted == false)
752         return;
753 
754     if (caps->family == CHIP_RV530) {
755         if (r300->screen->info.r300_num_z_pipes == 2)
756             rv530_emit_query_end_double_z(r300, query);
757         else
758             rv530_emit_query_end_single_z(r300, query);
759     } else
760         r300_emit_query_end_frag_pipes(r300, query);
761 
762     query->begin_emitted = false;
763     query->num_results += query->num_pipes;
764 
765     /* XXX grab all the results and reset the counter. */
766     if (query->num_results >= query->buf->size / 4 - 4) {
767         query->num_results = (query->buf->size / 4) / 2;
768         fprintf(stderr, "r300: Rewinding OQBO...\n");
769     }
770 }
771 
r300_emit_invariant_state(struct r300_context * r300,unsigned size,void * state)772 void r300_emit_invariant_state(struct r300_context *r300,
773                                unsigned size, void *state)
774 {
775     CS_LOCALS(r300);
776     WRITE_CS_TABLE(state, size);
777 }
778 
r300_emit_rs_state(struct r300_context * r300,unsigned size,void * state)779 void r300_emit_rs_state(struct r300_context* r300, unsigned size, void* state)
780 {
781     struct r300_rs_state* rs = state;
782     CS_LOCALS(r300);
783 
784     BEGIN_CS(size);
785     OUT_CS_TABLE(rs->cb_main, RS_STATE_MAIN_SIZE);
786     if (rs->polygon_offset_enable) {
787         if (r300->zbuffer_bpp == 16) {
788             OUT_CS_TABLE(rs->cb_poly_offset_zb16, 5);
789         } else {
790             OUT_CS_TABLE(rs->cb_poly_offset_zb24, 5);
791         }
792     }
793     END_CS;
794 }
795 
r300_emit_rs_block_state(struct r300_context * r300,unsigned size,void * state)796 void r300_emit_rs_block_state(struct r300_context* r300,
797                               unsigned size, void* state)
798 {
799     struct r300_rs_block* rs = (struct r300_rs_block*)state;
800     unsigned i;
801     /* It's the same for both INST and IP tables */
802     unsigned count = (rs->inst_count & R300_RS_INST_COUNT_MASK) + 1;
803     CS_LOCALS(r300);
804 
805     if (DBG_ON(r300, DBG_RS_BLOCK)) {
806         r500_dump_rs_block(rs);
807 
808         fprintf(stderr, "r300: RS emit:\n");
809 
810         for (i = 0; i < count; i++)
811             fprintf(stderr, "    : ip %d: 0x%08x\n", i, rs->ip[i]);
812 
813         for (i = 0; i < count; i++)
814             fprintf(stderr, "    : inst %d: 0x%08x\n", i, rs->inst[i]);
815 
816         fprintf(stderr, "    : count: 0x%08x inst_count: 0x%08x\n",
817             rs->count, rs->inst_count);
818     }
819 
820     BEGIN_CS(size);
821     OUT_CS_REG_SEQ(R300_VAP_VTX_STATE_CNTL, 2);
822     OUT_CS(rs->vap_vtx_state_cntl);
823     OUT_CS(rs->vap_vsm_vtx_assm);
824     OUT_CS_REG_SEQ(R300_VAP_OUTPUT_VTX_FMT_0, 2);
825     OUT_CS(rs->vap_out_vtx_fmt[0]);
826     OUT_CS(rs->vap_out_vtx_fmt[1]);
827     OUT_CS_REG_SEQ(R300_GB_ENABLE, 1);
828     OUT_CS(rs->gb_enable);
829 
830     if (r300->screen->caps.is_r500) {
831         OUT_CS_REG_SEQ(R500_RS_IP_0, count);
832     } else {
833         OUT_CS_REG_SEQ(R300_RS_IP_0, count);
834     }
835     OUT_CS_TABLE(rs->ip, count);
836 
837     OUT_CS_REG_SEQ(R300_RS_COUNT, 2);
838     OUT_CS(rs->count);
839     OUT_CS(rs->inst_count);
840 
841     if (r300->screen->caps.is_r500) {
842         OUT_CS_REG_SEQ(R500_RS_INST_0, count);
843     } else {
844         OUT_CS_REG_SEQ(R300_RS_INST_0, count);
845     }
846     OUT_CS_TABLE(rs->inst, count);
847     END_CS;
848 }
849 
r300_emit_sample_mask(struct r300_context * r300,unsigned size,void * state)850 void r300_emit_sample_mask(struct r300_context *r300,
851                            unsigned size, void *state)
852 {
853     unsigned mask = (*(unsigned*)state) & ((1 << 6)-1);
854     CS_LOCALS(r300);
855 
856     BEGIN_CS(size);
857     OUT_CS_REG(R300_SC_SCREENDOOR,
858                mask | (mask << 6) | (mask << 12) | (mask << 18));
859     END_CS;
860 }
861 
r300_emit_scissor_state(struct r300_context * r300,unsigned size,void * state)862 void r300_emit_scissor_state(struct r300_context* r300,
863                              unsigned size, void* state)
864 {
865     struct pipe_scissor_state* scissor = (struct pipe_scissor_state*)state;
866     CS_LOCALS(r300);
867 
868     BEGIN_CS(size);
869     OUT_CS_REG_SEQ(R300_SC_CLIPRECT_TL_0, 2);
870     if (r300->screen->caps.is_r500) {
871         OUT_CS((scissor->minx << R300_CLIPRECT_X_SHIFT) |
872                (scissor->miny << R300_CLIPRECT_Y_SHIFT));
873         OUT_CS(((scissor->maxx - 1) << R300_CLIPRECT_X_SHIFT) |
874                ((scissor->maxy - 1) << R300_CLIPRECT_Y_SHIFT));
875     } else {
876         OUT_CS(((scissor->minx + 1440) << R300_CLIPRECT_X_SHIFT) |
877                ((scissor->miny + 1440) << R300_CLIPRECT_Y_SHIFT));
878         OUT_CS(((scissor->maxx + 1440-1) << R300_CLIPRECT_X_SHIFT) |
879                ((scissor->maxy + 1440-1) << R300_CLIPRECT_Y_SHIFT));
880     }
881     END_CS;
882 }
883 
r300_emit_textures_state(struct r300_context * r300,unsigned size,void * state)884 void r300_emit_textures_state(struct r300_context *r300,
885                               unsigned size, void *state)
886 {
887     struct r300_textures_state *allstate = (struct r300_textures_state*)state;
888     struct r300_texture_sampler_state *texstate;
889     struct r300_resource *tex;
890     unsigned i;
891     bool has_us_format = r300->screen->caps.has_us_format;
892     CS_LOCALS(r300);
893 
894     BEGIN_CS(size);
895     OUT_CS_REG(R300_TX_ENABLE, allstate->tx_enable);
896 
897     for (i = 0; i < allstate->count; i++) {
898         if ((1 << i) & allstate->tx_enable) {
899             texstate = &allstate->regs[i];
900             tex = r300_resource(allstate->sampler_views[i]->base.texture);
901 
902             OUT_CS_REG(R300_TX_FILTER0_0 + (i * 4), texstate->filter0);
903             OUT_CS_REG(R300_TX_FILTER1_0 + (i * 4), texstate->filter1);
904             OUT_CS_REG(R300_TX_BORDER_COLOR_0 + (i * 4),
905                        texstate->border_color);
906 
907             OUT_CS_REG(R300_TX_FORMAT0_0 + (i * 4), texstate->format.format0);
908             OUT_CS_REG(R300_TX_FORMAT1_0 + (i * 4), texstate->format.format1);
909             OUT_CS_REG(R300_TX_FORMAT2_0 + (i * 4), texstate->format.format2);
910 
911             OUT_CS_REG(R300_TX_OFFSET_0 + (i * 4), texstate->format.tile_config);
912             OUT_CS_RELOC(tex);
913 
914             if (has_us_format) {
915                 OUT_CS_REG(R500_US_FORMAT0_0 + (i * 4),
916                            texstate->format.us_format0);
917             }
918         }
919     }
920     END_CS;
921 }
922 
r300_emit_vertex_arrays(struct r300_context * r300,int offset,bool indexed,int instance_id)923 void r300_emit_vertex_arrays(struct r300_context* r300, int offset,
924                              bool indexed, int instance_id)
925 {
926     struct pipe_vertex_buffer *vbuf = r300->vertex_buffer;
927     struct pipe_vertex_element *velem = r300->velems->velem;
928     struct r300_resource *buf;
929     int i;
930     unsigned vertex_array_count = r300->velems->count;
931     unsigned packet_size = (vertex_array_count * 3 + 1) / 2;
932     struct pipe_vertex_buffer *vb1, *vb2;
933     unsigned *hw_format_size = r300->velems->format_size;
934     unsigned size1, size2, offset1, offset2, stride1, stride2;
935     CS_LOCALS(r300);
936 
937     BEGIN_CS(2 + packet_size + vertex_array_count * 2);
938     OUT_CS_PKT3(R300_PACKET3_3D_LOAD_VBPNTR, packet_size);
939     OUT_CS(vertex_array_count | (!indexed ? R300_VC_FORCE_PREFETCH : 0));
940 
941     if (instance_id == -1) {
942         /* Non-instanced arrays. This ignores instance_divisor and instance_id. */
943         for (i = 0; i < vertex_array_count - 1; i += 2) {
944             vb1 = &vbuf[velem[i].vertex_buffer_index];
945             vb2 = &vbuf[velem[i+1].vertex_buffer_index];
946             size1 = hw_format_size[i];
947             size2 = hw_format_size[i+1];
948 
949             OUT_CS(R300_VBPNTR_SIZE0(size1) | R300_VBPNTR_STRIDE0(velem[i].src_stride) |
950                    R300_VBPNTR_SIZE1(size2) | R300_VBPNTR_STRIDE1(velem[i+1].src_stride));
951             OUT_CS(vb1->buffer_offset + velem[i].src_offset   + offset * velem[i].src_stride);
952             OUT_CS(vb2->buffer_offset + velem[i+1].src_offset + offset * velem[i+1].src_stride);
953         }
954 
955         if (vertex_array_count & 1) {
956             vb1 = &vbuf[velem[i].vertex_buffer_index];
957             size1 = hw_format_size[i];
958 
959             OUT_CS(R300_VBPNTR_SIZE0(size1) | R300_VBPNTR_STRIDE0(velem[i].src_stride));
960             OUT_CS(vb1->buffer_offset + velem[i].src_offset + offset * velem[i].src_stride);
961         }
962 
963         for (i = 0; i < vertex_array_count; i++) {
964             buf = r300_resource(vbuf[velem[i].vertex_buffer_index].buffer.resource);
965             OUT_CS_RELOC(buf);
966         }
967     } else {
968         /* Instanced arrays. */
969         for (i = 0; i < vertex_array_count - 1; i += 2) {
970             vb1 = &vbuf[velem[i].vertex_buffer_index];
971             vb2 = &vbuf[velem[i+1].vertex_buffer_index];
972             size1 = hw_format_size[i];
973             size2 = hw_format_size[i+1];
974 
975             if (velem[i].instance_divisor) {
976                 stride1 = 0;
977                 offset1 = vb1->buffer_offset + velem[i].src_offset +
978                           (instance_id / velem[i].instance_divisor) * velem[i].src_stride;
979             } else {
980                 stride1 = velem[i].src_stride;
981                 offset1 = vb1->buffer_offset + velem[i].src_offset + offset * velem[i].src_stride;
982             }
983             if (velem[i+1].instance_divisor) {
984                 stride2 = 0;
985                 offset2 = vb2->buffer_offset + velem[i+1].src_offset +
986                           (instance_id / velem[i+1].instance_divisor) * velem[i+1].src_stride;
987             } else {
988                 stride2 = velem[i+1].src_stride;
989                 offset2 = vb2->buffer_offset + velem[i+1].src_offset + offset * velem[i+1].src_stride;
990             }
991 
992             OUT_CS(R300_VBPNTR_SIZE0(size1) | R300_VBPNTR_STRIDE0(stride1) |
993                    R300_VBPNTR_SIZE1(size2) | R300_VBPNTR_STRIDE1(stride2));
994             OUT_CS(offset1);
995             OUT_CS(offset2);
996         }
997 
998         if (vertex_array_count & 1) {
999             vb1 = &vbuf[velem[i].vertex_buffer_index];
1000             size1 = hw_format_size[i];
1001 
1002             if (velem[i].instance_divisor) {
1003                 stride1 = 0;
1004                 offset1 = vb1->buffer_offset + velem[i].src_offset +
1005                           (instance_id / velem[i].instance_divisor) * velem[i].src_stride;
1006             } else {
1007                 stride1 = velem[i].src_stride;
1008                 offset1 = vb1->buffer_offset + velem[i].src_offset + offset * velem[i].src_stride;
1009             }
1010 
1011             OUT_CS(R300_VBPNTR_SIZE0(size1) | R300_VBPNTR_STRIDE0(stride1));
1012             OUT_CS(offset1);
1013         }
1014 
1015         for (i = 0; i < vertex_array_count; i++) {
1016             buf = r300_resource(vbuf[velem[i].vertex_buffer_index].buffer.resource);
1017             OUT_CS_RELOC(buf);
1018         }
1019     }
1020     END_CS;
1021 }
1022 
r300_emit_vertex_arrays_swtcl(struct r300_context * r300,bool indexed)1023 void r300_emit_vertex_arrays_swtcl(struct r300_context *r300, bool indexed)
1024 {
1025     CS_LOCALS(r300);
1026 
1027     DBG(r300, DBG_SWTCL, "r300: Preparing vertex buffer %p for render, "
1028             "vertex size %d\n", r300->vbo,
1029             r300->vertex_info.size);
1030     /* Set the pointer to our vertex buffer. The emitted values are this:
1031      * PACKET3 [3D_LOAD_VBPNTR]
1032      * COUNT   [1]
1033      * FORMAT  [size | stride << 8]
1034      * OFFSET  [offset into BO]
1035      * VBPNTR  [relocated BO]
1036      */
1037     BEGIN_CS(7);
1038     OUT_CS_PKT3(R300_PACKET3_3D_LOAD_VBPNTR, 3);
1039     OUT_CS(1 | (!indexed ? R300_VC_FORCE_PREFETCH : 0));
1040     OUT_CS(r300->vertex_info.size |
1041             (r300->vertex_info.size << 8));
1042     OUT_CS(r300->draw_vbo_offset);
1043     OUT_CS(0);
1044 
1045     assert(r300->vbo);
1046     OUT_CS(0xc0001000); /* PKT3_NOP */
1047     OUT_CS(r300->rws->cs_lookup_buffer(&r300->cs, r300->vbo) * 4);
1048     END_CS;
1049 }
1050 
r300_emit_vertex_stream_state(struct r300_context * r300,unsigned size,void * state)1051 void r300_emit_vertex_stream_state(struct r300_context* r300,
1052                                    unsigned size, void* state)
1053 {
1054     struct r300_vertex_stream_state *streams =
1055         (struct r300_vertex_stream_state*)state;
1056     unsigned i;
1057     CS_LOCALS(r300);
1058 
1059     if (DBG_ON(r300, DBG_PSC)) {
1060         fprintf(stderr, "r300: PSC emit:\n");
1061 
1062         for (i = 0; i < streams->count; i++) {
1063             fprintf(stderr, "    : prog_stream_cntl%d: 0x%08x\n", i,
1064                    streams->vap_prog_stream_cntl[i]);
1065         }
1066 
1067         for (i = 0; i < streams->count; i++) {
1068             fprintf(stderr, "    : prog_stream_cntl_ext%d: 0x%08x\n", i,
1069                    streams->vap_prog_stream_cntl_ext[i]);
1070         }
1071     }
1072 
1073     BEGIN_CS(size);
1074     OUT_CS_REG_SEQ(R300_VAP_PROG_STREAM_CNTL_0, streams->count);
1075     OUT_CS_TABLE(streams->vap_prog_stream_cntl, streams->count);
1076     OUT_CS_REG_SEQ(R300_VAP_PROG_STREAM_CNTL_EXT_0, streams->count);
1077     OUT_CS_TABLE(streams->vap_prog_stream_cntl_ext, streams->count);
1078     END_CS;
1079 }
1080 
r300_emit_pvs_flush(struct r300_context * r300,unsigned size,void * state)1081 void r300_emit_pvs_flush(struct r300_context* r300, unsigned size, void* state)
1082 {
1083     CS_LOCALS(r300);
1084 
1085     BEGIN_CS(size);
1086     OUT_CS_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0x0);
1087     END_CS;
1088 }
1089 
r300_emit_vap_invariant_state(struct r300_context * r300,unsigned size,void * state)1090 void r300_emit_vap_invariant_state(struct r300_context *r300,
1091                                    unsigned size, void *state)
1092 {
1093     CS_LOCALS(r300);
1094     WRITE_CS_TABLE(state, size);
1095 }
1096 
r300_emit_vs_state(struct r300_context * r300,unsigned size,void * state)1097 void r300_emit_vs_state(struct r300_context* r300, unsigned size, void* state)
1098 {
1099     struct r300_vertex_shader_code* vs = ((struct r300_vertex_shader*)state)->shader;
1100     struct r300_vertex_program_code* code = &vs->code;
1101     struct r300_screen* r300screen = r300->screen;
1102     unsigned instruction_count = code->length / 4;
1103 
1104     unsigned vtx_mem_size = r300screen->caps.is_r500 ? 128 : 72;
1105     unsigned input_count = MAX2(util_bitcount(code->InputsRead), 1);
1106     unsigned output_count = MAX2(util_bitcount(code->OutputsWritten), 1);
1107     unsigned temp_count = MAX2(code->num_temporaries, 1);
1108 
1109     unsigned pvs_num_slots = MIN3(vtx_mem_size / input_count,
1110                                   vtx_mem_size / output_count, 10);
1111     unsigned pvs_num_controllers = MIN2(vtx_mem_size / temp_count, 5);
1112 
1113     CS_LOCALS(r300);
1114 
1115     BEGIN_CS(size);
1116 
1117     /* R300_VAP_PVS_CODE_CNTL_0
1118      * R300_VAP_PVS_CONST_CNTL
1119      * R300_VAP_PVS_CODE_CNTL_1
1120      * See the r5xx docs for instructions on how to use these. */
1121     OUT_CS_REG(R300_VAP_PVS_CODE_CNTL_0, R300_PVS_FIRST_INST(0) |
1122 	       R300_PVS_XYZW_VALID_INST(code->last_pos_write) |
1123 	       R300_PVS_LAST_INST(instruction_count - 1));
1124     OUT_CS_REG(R300_VAP_PVS_CODE_CNTL_1, code->last_input_read);
1125 
1126     OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG, 0);
1127     OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, code->length);
1128     OUT_CS_TABLE(code->body.d, code->length);
1129 
1130     OUT_CS_REG(R300_VAP_CNTL, R300_PVS_NUM_SLOTS(pvs_num_slots) |
1131             R300_PVS_NUM_CNTLRS(pvs_num_controllers) |
1132             R300_PVS_NUM_FPUS(r300screen->caps.num_vert_fpus) |
1133             R300_PVS_VF_MAX_VTX_NUM(12) |
1134             (r300->clip_halfz ? R300_DX_CLIP_SPACE_DEF : 0) |
1135             (r300screen->caps.is_r500 ? R500_TCL_STATE_OPTIMIZATION : 0));
1136 
1137     /* Emit flow control instructions.  Even if there are no fc instructions,
1138      * we still need to write the registers to make sure they are cleared. */
1139     OUT_CS_REG(R300_VAP_PVS_FLOW_CNTL_OPC, code->fc_ops);
1140     if (r300screen->caps.is_r500) {
1141         OUT_CS_REG_SEQ(R500_VAP_PVS_FLOW_CNTL_ADDRS_LW_0, R300_VS_MAX_FC_OPS * 2);
1142         OUT_CS_TABLE(code->fc_op_addrs.r500, R300_VS_MAX_FC_OPS * 2);
1143     } else {
1144         OUT_CS_REG_SEQ(R300_VAP_PVS_FLOW_CNTL_ADDRS_0, R300_VS_MAX_FC_OPS);
1145         OUT_CS_TABLE(code->fc_op_addrs.r300, R300_VS_MAX_FC_OPS);
1146     }
1147     OUT_CS_REG_SEQ(R300_VAP_PVS_FLOW_CNTL_LOOP_INDEX_0, R300_VS_MAX_FC_OPS);
1148     OUT_CS_TABLE(code->fc_loop_index, R300_VS_MAX_FC_OPS);
1149 
1150     END_CS;
1151 }
1152 
r300_emit_vs_constants(struct r300_context * r300,unsigned size,void * state)1153 void r300_emit_vs_constants(struct r300_context* r300,
1154                             unsigned size, void *state)
1155 {
1156     unsigned count = r300_vs(r300)->shader->externals_count;
1157     struct r300_constant_buffer *buf = (struct r300_constant_buffer*)state;
1158     struct r300_vertex_shader_code *vs = r300_vs(r300)->shader;
1159     unsigned i;
1160     int imm_first = vs->externals_count;
1161     int imm_end = vs->code.constants.Count;
1162     int imm_count = vs->immediates_count;
1163     CS_LOCALS(r300);
1164 
1165     BEGIN_CS(size);
1166     OUT_CS_REG(R300_VAP_PVS_CONST_CNTL,
1167                R300_PVS_CONST_BASE_OFFSET(buf->buffer_base) |
1168                R300_PVS_MAX_CONST_ADDR(MAX2(imm_end - 1, 0)));
1169     if (vs->externals_count) {
1170         OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG,
1171                    (r300->screen->caps.is_r500 ?
1172                    R500_PVS_CONST_START : R300_PVS_CONST_START) + buf->buffer_base);
1173         OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, count * 4);
1174         if (buf->remap_table){
1175             uint32_t *data = buf->ptr;
1176             for (i = 0; i < count; i++) {
1177                 uint32_t constant[4];
1178                 for (unsigned chan = 0; chan < 4; chan++) {
1179                     constant[chan] = data[buf->remap_table[i].index[chan] * 4 +
1180                                            buf->remap_table[i].swizzle[chan]];
1181                 }
1182                 OUT_CS_TABLE(constant, 4);
1183             }
1184         } else {
1185             OUT_CS_TABLE(buf->ptr, count * 4);
1186         }
1187     }
1188 
1189     /* Emit immediates. */
1190     if (imm_count) {
1191         OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG,
1192                    (r300->screen->caps.is_r500 ?
1193                    R500_PVS_CONST_START : R300_PVS_CONST_START) +
1194                    buf->buffer_base + imm_first);
1195         OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, imm_count * 4);
1196         for (i = imm_first; i < imm_end; i++) {
1197             const float *data = vs->code.constants.Constants[i].u.Immediate;
1198             OUT_CS_TABLE(data, 4);
1199         }
1200     }
1201     END_CS;
1202 }
1203 
r300_emit_viewport_state(struct r300_context * r300,unsigned size,void * state)1204 void r300_emit_viewport_state(struct r300_context* r300,
1205                               unsigned size, void* state)
1206 {
1207     struct r300_viewport_state* viewport = (struct r300_viewport_state*)state;
1208     CS_LOCALS(r300);
1209 
1210     BEGIN_CS(size);
1211     OUT_CS_REG_SEQ(R300_SE_VPORT_XSCALE, 6);
1212     OUT_CS_TABLE(&viewport->xscale, 6);
1213     OUT_CS_REG(R300_VAP_VTE_CNTL, viewport->vte_control);
1214     END_CS;
1215 }
1216 
r300_emit_hiz_clear(struct r300_context * r300,unsigned size,void * state)1217 void r300_emit_hiz_clear(struct r300_context *r300, unsigned size, void *state)
1218 {
1219     struct pipe_framebuffer_state *fb =
1220         (struct pipe_framebuffer_state*)r300->fb_state.state;
1221     struct r300_resource* tex;
1222     CS_LOCALS(r300);
1223 
1224     tex = r300_resource(fb->zsbuf->texture);
1225 
1226     BEGIN_CS(size);
1227     OUT_CS_PKT3(R300_PACKET3_3D_CLEAR_HIZ, 2);
1228     OUT_CS(0);
1229     OUT_CS(tex->tex.hiz_dwords[fb->zsbuf->u.tex.level]);
1230     OUT_CS(r300->hiz_clear_value);
1231     END_CS;
1232 
1233     /* Mark the current zbuffer's hiz ram as in use. */
1234     r300->hiz_in_use = true;
1235     r300->hiz_func = HIZ_FUNC_NONE;
1236     r300_mark_atom_dirty(r300, &r300->hyperz_state);
1237 }
1238 
r300_emit_zmask_clear(struct r300_context * r300,unsigned size,void * state)1239 void r300_emit_zmask_clear(struct r300_context *r300, unsigned size, void *state)
1240 {
1241     struct pipe_framebuffer_state *fb =
1242         (struct pipe_framebuffer_state*)r300->fb_state.state;
1243     struct r300_resource *tex;
1244     CS_LOCALS(r300);
1245 
1246     tex = r300_resource(fb->zsbuf->texture);
1247 
1248     BEGIN_CS(size);
1249     OUT_CS_PKT3(R300_PACKET3_3D_CLEAR_ZMASK, 2);
1250     OUT_CS(0);
1251     OUT_CS(tex->tex.zmask_dwords[fb->zsbuf->u.tex.level]);
1252     OUT_CS(0);
1253     END_CS;
1254 
1255     /* Mark the current zbuffer's zmask as in use. */
1256     r300->zmask_in_use = true;
1257     r300_mark_atom_dirty(r300, &r300->hyperz_state);
1258 }
1259 
r300_emit_cmask_clear(struct r300_context * r300,unsigned size,void * state)1260 void r300_emit_cmask_clear(struct r300_context *r300, unsigned size, void *state)
1261 {
1262     struct pipe_framebuffer_state *fb =
1263         (struct pipe_framebuffer_state*)r300->fb_state.state;
1264     struct r300_resource *tex;
1265     CS_LOCALS(r300);
1266 
1267     tex = r300_resource(fb->cbufs[0]->texture);
1268 
1269     BEGIN_CS(size);
1270     OUT_CS_PKT3(R300_PACKET3_3D_CLEAR_CMASK, 2);
1271     OUT_CS(0);
1272     OUT_CS(tex->tex.cmask_dwords);
1273     OUT_CS(0);
1274     END_CS;
1275 
1276     /* Mark the current zbuffer's zmask as in use. */
1277     r300->cmask_in_use = true;
1278     r300_mark_fb_state_dirty(r300, R300_CHANGED_CMASK_ENABLE);
1279 }
1280 
r300_emit_ztop_state(struct r300_context * r300,unsigned size,void * state)1281 void r300_emit_ztop_state(struct r300_context* r300,
1282                           unsigned size, void* state)
1283 {
1284     struct r300_ztop_state* ztop = (struct r300_ztop_state*)state;
1285     CS_LOCALS(r300);
1286 
1287     BEGIN_CS(size);
1288     OUT_CS_REG(R300_ZB_ZTOP, ztop->z_buffer_top);
1289     END_CS;
1290 }
1291 
r300_emit_texture_cache_inval(struct r300_context * r300,unsigned size,void * state)1292 void r300_emit_texture_cache_inval(struct r300_context* r300, unsigned size, void* state)
1293 {
1294     CS_LOCALS(r300);
1295 
1296     BEGIN_CS(size);
1297     OUT_CS_REG(R300_TX_INVALTAGS, 0);
1298     END_CS;
1299 }
1300 
r300_emit_buffer_validate(struct r300_context * r300,bool do_validate_vertex_buffers,struct pipe_resource * index_buffer)1301 bool r300_emit_buffer_validate(struct r300_context *r300,
1302                                bool do_validate_vertex_buffers,
1303                                struct pipe_resource *index_buffer)
1304 {
1305     struct pipe_framebuffer_state *fb =
1306         (struct pipe_framebuffer_state*)r300->fb_state.state;
1307     struct r300_aa_state *aa = (struct r300_aa_state*)r300->aa_state.state;
1308     struct r300_textures_state *texstate =
1309         (struct r300_textures_state*)r300->textures_state.state;
1310     struct r300_resource *tex;
1311     unsigned i;
1312     bool flushed = false;
1313 
1314 validate:
1315     if (r300->fb_state.dirty) {
1316         /* Color buffers... */
1317         for (i = 0; i < fb->nr_cbufs; i++) {
1318             if (!fb->cbufs[i])
1319                 continue;
1320             tex = r300_resource(fb->cbufs[i]->texture);
1321             assert(tex && tex->buf && "cbuf is marked, but NULL!");
1322             r300->rws->cs_add_buffer(&r300->cs, tex->buf,
1323                                     RADEON_USAGE_READWRITE | RADEON_USAGE_SYNCHRONIZED |
1324                                     (tex->b.nr_samples > 1 ?
1325                                         RADEON_PRIO_COLOR_BUFFER_MSAA :
1326                                         RADEON_PRIO_COLOR_BUFFER),
1327                                     r300_surface(fb->cbufs[i])->domain);
1328         }
1329         /* ...depth buffer... */
1330         if (fb->zsbuf) {
1331             tex = r300_resource(fb->zsbuf->texture);
1332             assert(tex && tex->buf && "zsbuf is marked, but NULL!");
1333             r300->rws->cs_add_buffer(&r300->cs, tex->buf,
1334                                     RADEON_USAGE_READWRITE | RADEON_USAGE_SYNCHRONIZED |
1335                                     (tex->b.nr_samples > 1 ?
1336                                         RADEON_PRIO_DEPTH_BUFFER_MSAA :
1337                                         RADEON_PRIO_DEPTH_BUFFER),
1338                                     r300_surface(fb->zsbuf)->domain);
1339         }
1340     }
1341     /* The AA resolve buffer. */
1342     if (r300->aa_state.dirty) {
1343         if (aa->dest) {
1344             r300->rws->cs_add_buffer(&r300->cs, aa->dest->buf,
1345                                     RADEON_USAGE_WRITE | RADEON_USAGE_SYNCHRONIZED |
1346                                     RADEON_PRIO_COLOR_BUFFER,
1347                                     aa->dest->domain);
1348         }
1349     }
1350     if (r300->textures_state.dirty) {
1351         /* ...textures... */
1352         for (i = 0; i < texstate->count; i++) {
1353             if (!(texstate->tx_enable & (1U << i))) {
1354                 continue;
1355             }
1356 
1357             tex = r300_resource(texstate->sampler_views[i]->base.texture);
1358             r300->rws->cs_add_buffer(&r300->cs, tex->buf,
1359                                      RADEON_USAGE_READ | RADEON_USAGE_SYNCHRONIZED |
1360                                      RADEON_PRIO_SAMPLER_TEXTURE,
1361                                     tex->domain);
1362         }
1363     }
1364     /* ...occlusion query buffer... */
1365     if (r300->query_current)
1366         r300->rws->cs_add_buffer(&r300->cs, r300->query_current->buf,
1367                                  RADEON_USAGE_WRITE | RADEON_USAGE_SYNCHRONIZED |
1368                                  RADEON_PRIO_QUERY,
1369                                  RADEON_DOMAIN_GTT);
1370     /* ...vertex buffer for SWTCL path... */
1371     if (r300->vbo)
1372         r300->rws->cs_add_buffer(&r300->cs, r300->vbo,
1373                                  RADEON_USAGE_READ | RADEON_USAGE_SYNCHRONIZED |
1374                                  RADEON_PRIO_VERTEX_BUFFER,
1375                                  RADEON_DOMAIN_GTT);
1376     /* ...vertex buffers for HWTCL path... */
1377     if (do_validate_vertex_buffers && r300->vertex_arrays_dirty) {
1378         struct pipe_vertex_buffer *vbuf = r300->vertex_buffer;
1379         struct pipe_vertex_buffer *last = r300->vertex_buffer +
1380                                       r300->nr_vertex_buffers;
1381         struct pipe_resource *buf;
1382 
1383         for (; vbuf != last; vbuf++) {
1384             buf = vbuf->buffer.resource;
1385             if (!buf)
1386                 continue;
1387 
1388             r300->rws->cs_add_buffer(&r300->cs, r300_resource(buf)->buf,
1389                                     RADEON_USAGE_READ | RADEON_USAGE_SYNCHRONIZED |
1390                                     RADEON_PRIO_SAMPLER_BUFFER,
1391                                     r300_resource(buf)->domain);
1392         }
1393     }
1394     /* ...and index buffer for HWTCL path. */
1395     if (index_buffer)
1396         r300->rws->cs_add_buffer(&r300->cs, r300_resource(index_buffer)->buf,
1397                                 RADEON_USAGE_READ | RADEON_USAGE_SYNCHRONIZED |
1398                                 RADEON_PRIO_INDEX_BUFFER,
1399                                 r300_resource(index_buffer)->domain);
1400 
1401     /* Now do the validation (flush is called inside cs_validate on failure). */
1402     if (!r300->rws->cs_validate(&r300->cs)) {
1403         /* Ooops, an infinite loop, give up. */
1404         if (flushed)
1405             return false;
1406 
1407         flushed = true;
1408         goto validate;
1409     }
1410 
1411     return true;
1412 }
1413 
r300_get_num_dirty_dwords(struct r300_context * r300)1414 unsigned r300_get_num_dirty_dwords(struct r300_context *r300)
1415 {
1416     struct r300_atom* atom;
1417     unsigned dwords = 0;
1418 
1419     foreach_dirty_atom(r300, atom) {
1420         if (atom->dirty) {
1421             dwords += atom->size;
1422         }
1423     }
1424 
1425     /* let's reserve some more, just in case */
1426     dwords += 32;
1427 
1428     return dwords;
1429 }
1430 
r300_get_num_cs_end_dwords(struct r300_context * r300)1431 unsigned r300_get_num_cs_end_dwords(struct r300_context *r300)
1432 {
1433     unsigned dwords = 0;
1434 
1435     /* Emitted in flush. */
1436     dwords += 26; /* emit_query_end */
1437     dwords += r300->hyperz_state.size + 2; /* emit_hyperz_end + zcache flush */
1438     if (r300->screen->caps.is_r500)
1439         dwords += 2; /* emit_index_bias */
1440     dwords += 3; /* MSPOS */
1441 
1442     return dwords;
1443 }
1444 
1445 /* Emit all dirty state. */
r300_emit_dirty_state(struct r300_context * r300)1446 void r300_emit_dirty_state(struct r300_context* r300)
1447 {
1448     struct r300_atom *atom;
1449 
1450     foreach_dirty_atom(r300, atom) {
1451         if (atom->dirty) {
1452             atom->emit(r300, atom->size, atom->state);
1453             atom->dirty = false;
1454         }
1455     }
1456 
1457     r300->first_dirty = NULL;
1458     r300->last_dirty = NULL;
1459     r300->dirty_hw++;
1460 }
1461