1 /* 2 * Copyright 2008 Corbin Simpson <[email protected]> 3 * SPDX-License-Identifier: MIT 4 */ 5 6 #ifndef R300_CHIPSET_H 7 #define R300_CHIPSET_H 8 9 #include "util/compiler.h" 10 11 /* these are sizes in dwords */ 12 #define R300_HIZ_LIMIT 10240 13 #define RV530_HIZ_LIMIT 15360 14 15 /* rv3xx have only one pipe */ 16 #define PIPE_ZMASK_SIZE 4096 17 #define RV3xx_ZMASK_SIZE 5120 18 19 /* The size of a compressed tile. Each compressed tile takes 2 bits 20 * in the ZMASK RAM, so there is always 16 tiles per one dword. */ 21 enum r300_zmask_compression { 22 R300_ZCOMP_4X4 = 4, 23 R300_ZCOMP_8X8 = 8 24 }; 25 26 /* Structure containing all the possible information about a specific Radeon 27 * in the R3xx, R4xx, and R5xx families. */ 28 struct r300_capabilities { 29 /* Chipset family */ 30 int family; 31 /* The number of vertex floating-point units */ 32 unsigned num_vert_fpus; 33 /* The number of texture units. */ 34 unsigned num_tex_units; 35 /* Whether or not TCL is physically present */ 36 bool has_tcl; 37 /* Some chipsets do not have HiZ RAM - other have varying amounts. */ 38 int hiz_ram; 39 /* Some chipsets have zmask ram per pipe some don't. */ 40 int zmask_ram; 41 /* CMASK is for MSAA colorbuffer compression and fast clear. */ 42 bool has_cmask; 43 /* Compression mode for ZMASK. */ 44 enum r300_zmask_compression z_compress; 45 /* Whether or not this is RV350 or newer, including all r400 and r500 46 * chipsets. The differences compared to the oldest r300 chips are: 47 * - Blend LTE/GTE thresholds 48 * - Better MACRO_SWITCH in texture tiling 49 * - Half float vertex 50 * - More HyperZ optimizations */ 51 bool is_rv350; 52 /* Whether or not this is R400. The differences compared their rv350 53 * cousins are: 54 * - Extended fragment shader registers 55 * - 3DC texture compression (RGTC2) */ 56 bool is_r400; 57 /* Whether or not this is an RV515 or newer; R500s have many differences 58 * that require extra consideration, compared to their rv350 cousins: 59 * - Extra bit of width and height on texture sizes 60 * - Blend color is split across two registers 61 * - Universal Shader (US) block used for fragment shaders 62 * - FP16 blending and multisampling 63 * - Full RGTC texture compression 64 * - 24-bit depth textures 65 * - Stencil back-face reference value 66 * - Ability to render up to 2^24 - 1 vertices with signed index offset */ 67 bool is_r500; 68 /* Whether or not the second pixel pipe is accessed with the high bit */ 69 bool high_second_pipe; 70 /* DXTC texture swizzling. */ 71 bool dxtc_swizzle; 72 /* Whether R500_US_FORMAT0_0 exists (R520-only and depends on DRM). */ 73 bool has_us_format; 74 }; 75 76 void r300_parse_chipset(uint32_t pci_id, struct r300_capabilities* caps); 77 78 #endif /* R300_CHIPSET_H */ 79