1 /* 2 * Copyright 2008 Corbin Simpson <[email protected]> 3 * Copyright 2011 Marek Olšák <[email protected]> 4 * SPDX-License-Identifier: MIT 5 */ 6 7 #include "r300_chipset.h" 8 #include "winsys/radeon_winsys.h" 9 10 #include "util/u_debug.h" 11 #include "util/u_memory.h" 12 #include "util/u_process.h" 13 14 #include <stdio.h> 15 #include <errno.h> 16 17 /* r300_chipset: A file all to itself for deducing the various properties of 18 * Radeons. */ 19 20 /* Parse a PCI ID and fill an r300_capabilities struct with information. */ r300_parse_chipset(uint32_t pci_id,struct r300_capabilities * caps)21void r300_parse_chipset(uint32_t pci_id, struct r300_capabilities* caps) 22 { 23 switch (pci_id) { 24 #define CHIPSET(pci_id, name, chipfamily) \ 25 case pci_id: \ 26 caps->family = CHIP_##chipfamily; \ 27 break; 28 #include "pci_ids/r300_pci_ids.h" 29 #undef CHIPSET 30 31 default: 32 fprintf(stderr, "r300: Warning: Unknown chipset 0x%x\nAborting...", 33 pci_id); 34 abort(); 35 } 36 37 /* Defaults. */ 38 caps->high_second_pipe = false; 39 caps->num_vert_fpus = 0; 40 caps->hiz_ram = 0; 41 caps->zmask_ram = 0; 42 caps->has_cmask = false; 43 44 45 switch (caps->family) { 46 case CHIP_R300: 47 case CHIP_R350: 48 caps->high_second_pipe = true; 49 caps->num_vert_fpus = 4; 50 caps->has_cmask = true; /* guessed because there is also HiZ */ 51 caps->hiz_ram = R300_HIZ_LIMIT; 52 caps->zmask_ram = PIPE_ZMASK_SIZE; 53 break; 54 55 case CHIP_RV350: 56 case CHIP_RV370: 57 caps->high_second_pipe = true; 58 caps->num_vert_fpus = 2; 59 caps->zmask_ram = RV3xx_ZMASK_SIZE; 60 break; 61 62 case CHIP_RV380: 63 caps->high_second_pipe = true; 64 caps->num_vert_fpus = 2; 65 caps->has_cmask = true; /* guessed because there is also HiZ */ 66 caps->hiz_ram = R300_HIZ_LIMIT; 67 caps->zmask_ram = RV3xx_ZMASK_SIZE; 68 break; 69 70 case CHIP_RS400: 71 case CHIP_RS600: 72 case CHIP_RS690: 73 case CHIP_RS740: 74 break; 75 76 case CHIP_RC410: 77 case CHIP_RS480: 78 caps->zmask_ram = RV3xx_ZMASK_SIZE; 79 break; 80 81 case CHIP_R420: 82 case CHIP_R423: 83 case CHIP_R430: 84 case CHIP_R480: 85 case CHIP_R481: 86 case CHIP_RV410: 87 caps->num_vert_fpus = 6; 88 caps->has_cmask = true; /* guessed because there is also HiZ */ 89 caps->hiz_ram = R300_HIZ_LIMIT; 90 caps->zmask_ram = PIPE_ZMASK_SIZE; 91 break; 92 93 case CHIP_R520: 94 caps->num_vert_fpus = 8; 95 caps->has_cmask = true; 96 caps->hiz_ram = R300_HIZ_LIMIT; 97 caps->zmask_ram = PIPE_ZMASK_SIZE; 98 break; 99 100 case CHIP_RV515: 101 caps->num_vert_fpus = 2; 102 caps->has_cmask = true; 103 caps->hiz_ram = R300_HIZ_LIMIT; 104 caps->zmask_ram = PIPE_ZMASK_SIZE; 105 break; 106 107 case CHIP_RV530: 108 caps->num_vert_fpus = 5; 109 caps->has_cmask = true; 110 caps->hiz_ram = RV530_HIZ_LIMIT; 111 caps->zmask_ram = PIPE_ZMASK_SIZE; 112 break; 113 114 case CHIP_R580: 115 case CHIP_RV560: 116 case CHIP_RV570: 117 caps->num_vert_fpus = 8; 118 caps->has_cmask = true; 119 caps->hiz_ram = RV530_HIZ_LIMIT; 120 caps->zmask_ram = PIPE_ZMASK_SIZE; 121 break; 122 } 123 124 caps->num_tex_units = 16; 125 caps->is_r400 = caps->family >= CHIP_R420 && caps->family < CHIP_RV515; 126 caps->is_r500 = caps->family >= CHIP_RV515; 127 caps->is_rv350 = caps->family >= CHIP_RV350; 128 caps->z_compress = caps->is_rv350 ? R300_ZCOMP_8X8 : R300_ZCOMP_4X4; 129 caps->dxtc_swizzle = caps->is_r400 || caps->is_r500; 130 caps->has_us_format = caps->family == CHIP_R520; 131 caps->has_tcl = caps->num_vert_fpus > 0; 132 } 133