xref: /aosp_15_r20/external/mesa3d/src/gallium/drivers/nouveau/nv30/nvfx_vertprog.c (revision 6104692788411f58d303aa86923a9ff6ecaded22) 
1 #include <strings.h>
2 #include "pipe/p_context.h"
3 #include "pipe/p_defines.h"
4 #include "pipe/p_state.h"
5 #include "util/compiler.h"
6 #include "util/u_dynarray.h"
7 #include "util/u_debug.h"
8 #include "util/u_memory.h"
9 
10 #include "pipe/p_shader_tokens.h"
11 #include "tgsi/tgsi_parse.h"
12 #include "tgsi/tgsi_dump.h"
13 
14 #include "draw/draw_context.h"
15 
16 #include "nv_object.xml.h"
17 #include "nouveau_debug.h"
18 #include "nv30/nv30-40_3d.xml.h"
19 #include "nv30/nv30_state.h"
20 
21 /* TODO (at least...):
22  *  1. Indexed consts  + ARL
23  *  3. NV_vp11, NV_vp2, NV_vp3 features
24  *       - extra arith opcodes
25  *       - branching
26  *       - texture sampling
27  *       - indexed attribs
28  *       - indexed results
29  *  4. bugs
30  */
31 
32 #include "nv30/nv30_vertprog.h"
33 #include "nv30/nv40_vertprog.h"
34 
35 struct nvfx_loop_entry {
36    unsigned brk_target;
37    unsigned cont_target;
38 };
39 
40 struct nvfx_vpc {
41    struct pipe_shader_state pipe;
42    struct nv30_vertprog *vp;
43    struct tgsi_shader_info* info;
44 
45    struct nv30_vertprog_exec *vpi;
46 
47    unsigned r_temps;
48    unsigned r_temps_discard;
49    struct nvfx_reg r_result[PIPE_MAX_SHADER_OUTPUTS];
50    struct nvfx_reg *r_address;
51    struct nvfx_reg *r_temp;
52    struct nvfx_reg *r_const;
53    struct nvfx_reg r_0_1;
54 
55    struct nvfx_reg *imm;
56    unsigned nr_imm;
57 
58    int hpos_idx;
59    int cvtx_idx;
60 
61    unsigned is_nv4x;
62 
63    struct util_dynarray label_relocs;
64    struct util_dynarray loop_stack;
65 };
66 
67 static struct nvfx_reg
temp(struct nvfx_vpc * vpc)68 temp(struct nvfx_vpc *vpc)
69 {
70    int idx = ffs(~vpc->r_temps) - 1;
71 
72    if (idx < 0 || (!vpc->is_nv4x && idx >= 16)) {
73       NOUVEAU_ERR("out of temps!!\n");
74       return nvfx_reg(NVFXSR_TEMP, 0);
75    }
76 
77    vpc->r_temps |= (1 << idx);
78    vpc->r_temps_discard |= (1 << idx);
79    return nvfx_reg(NVFXSR_TEMP, idx);
80 }
81 
82 static inline void
release_temps(struct nvfx_vpc * vpc)83 release_temps(struct nvfx_vpc *vpc)
84 {
85    vpc->r_temps &= ~vpc->r_temps_discard;
86    vpc->r_temps_discard = 0;
87 }
88 
89 static struct nvfx_reg
constant(struct nvfx_vpc * vpc,int pipe,float x,float y,float z,float w)90 constant(struct nvfx_vpc *vpc, int pipe, float x, float y, float z, float w)
91 {
92    struct nv30_vertprog *vp = vpc->vp;
93    struct nv30_vertprog_data *vpd;
94    int idx;
95 
96    if (pipe >= 0) {
97       for (idx = 0; idx < vp->nr_consts; idx++) {
98          if (vp->consts[idx].index == pipe)
99             return nvfx_reg(NVFXSR_CONST, idx);
100       }
101    }
102 
103    idx = vp->nr_consts++;
104    vp->consts = realloc(vp->consts, sizeof(*vpd) * vp->nr_consts);
105    vpd = &vp->consts[idx];
106 
107    vpd->index = pipe;
108    vpd->value[0] = x;
109    vpd->value[1] = y;
110    vpd->value[2] = z;
111    vpd->value[3] = w;
112    return nvfx_reg(NVFXSR_CONST, idx);
113 }
114 
115 #define arith(s,t,o,d,m,s0,s1,s2) \
116    nvfx_insn((s), (NVFX_VP_INST_SLOT_##t << 7) | NVFX_VP_INST_##t##_OP_##o, -1, (d), (m), (s0), (s1), (s2))
117 
118 static void
emit_src(struct nvfx_vpc * vpc,uint32_t * hw,int pos,struct nvfx_src src)119 emit_src(struct nvfx_vpc *vpc, uint32_t *hw,
120          int pos, struct nvfx_src src)
121 {
122    struct nv30_vertprog *vp = vpc->vp;
123    uint32_t sr = 0;
124    struct nvfx_relocation reloc;
125 
126    switch (src.reg.type) {
127    case NVFXSR_TEMP:
128       sr |= (NVFX_VP(SRC_REG_TYPE_TEMP) << NVFX_VP(SRC_REG_TYPE_SHIFT));
129       sr |= (src.reg.index << NVFX_VP(SRC_TEMP_SRC_SHIFT));
130       break;
131    case NVFXSR_INPUT:
132       sr |= (NVFX_VP(SRC_REG_TYPE_INPUT) <<
133              NVFX_VP(SRC_REG_TYPE_SHIFT));
134       vp->ir |= (1 << src.reg.index);
135       hw[1] |= (src.reg.index << NVFX_VP(INST_INPUT_SRC_SHIFT));
136       break;
137    case NVFXSR_CONST:
138       sr |= (NVFX_VP(SRC_REG_TYPE_CONST) <<
139              NVFX_VP(SRC_REG_TYPE_SHIFT));
140       if (src.reg.index < 256 && src.reg.index >= -256) {
141          reloc.location = vp->nr_insns - 1;
142          reloc.target = src.reg.index;
143          util_dynarray_append(&vp->const_relocs, struct nvfx_relocation, reloc);
144       } else {
145          hw[1] |= (src.reg.index << NVFX_VP(INST_CONST_SRC_SHIFT)) &
146                NVFX_VP(INST_CONST_SRC_MASK);
147       }
148       break;
149    case NVFXSR_NONE:
150       sr |= (NVFX_VP(SRC_REG_TYPE_INPUT) <<
151              NVFX_VP(SRC_REG_TYPE_SHIFT));
152       break;
153    default:
154       assert(0);
155    }
156 
157    if (src.negate)
158       sr |= NVFX_VP(SRC_NEGATE);
159 
160    if (src.abs)
161       hw[0] |= (1 << (21 + pos));
162 
163    sr |= ((src.swz[0] << NVFX_VP(SRC_SWZ_X_SHIFT)) |
164           (src.swz[1] << NVFX_VP(SRC_SWZ_Y_SHIFT)) |
165           (src.swz[2] << NVFX_VP(SRC_SWZ_Z_SHIFT)) |
166           (src.swz[3] << NVFX_VP(SRC_SWZ_W_SHIFT)));
167 
168    if(src.indirect) {
169       if(src.reg.type == NVFXSR_CONST)
170          hw[3] |= NVFX_VP(INST_INDEX_CONST);
171       else if(src.reg.type == NVFXSR_INPUT)
172          hw[0] |= NVFX_VP(INST_INDEX_INPUT);
173       else
174          assert(0);
175 
176       if(src.indirect_reg)
177          hw[0] |= NVFX_VP(INST_ADDR_REG_SELECT_1);
178       hw[0] |= src.indirect_swz << NVFX_VP(INST_ADDR_SWZ_SHIFT);
179    }
180 
181    switch (pos) {
182    case 0:
183       hw[1] |= ((sr & NVFX_VP(SRC0_HIGH_MASK)) >>
184            NVFX_VP(SRC0_HIGH_SHIFT)) << NVFX_VP(INST_SRC0H_SHIFT);
185       hw[2] |= (sr & NVFX_VP(SRC0_LOW_MASK)) <<
186            NVFX_VP(INST_SRC0L_SHIFT);
187       break;
188    case 1:
189       hw[2] |= sr << NVFX_VP(INST_SRC1_SHIFT);
190       break;
191    case 2:
192       hw[2] |= ((sr & NVFX_VP(SRC2_HIGH_MASK)) >>
193            NVFX_VP(SRC2_HIGH_SHIFT)) << NVFX_VP(INST_SRC2H_SHIFT);
194       hw[3] |= (sr & NVFX_VP(SRC2_LOW_MASK)) <<
195            NVFX_VP(INST_SRC2L_SHIFT);
196       break;
197    default:
198       assert(0);
199    }
200 }
201 
202 static void
emit_dst(struct nvfx_vpc * vpc,uint32_t * hw,int slot,struct nvfx_reg dst)203 emit_dst(struct nvfx_vpc *vpc, uint32_t *hw,
204          int slot, struct nvfx_reg dst)
205 {
206    struct nv30_vertprog *vp = vpc->vp;
207 
208    switch (dst.type) {
209    case NVFXSR_NONE:
210       if(!vpc->is_nv4x)
211          hw[0] |= NV30_VP_INST_DEST_TEMP_ID_MASK;
212       else {
213          hw[3] |= NV40_VP_INST_DEST_MASK;
214          if (slot == 0)
215             hw[0] |= NV40_VP_INST_VEC_DEST_TEMP_MASK;
216          else
217             hw[3] |= NV40_VP_INST_SCA_DEST_TEMP_MASK;
218       }
219       break;
220    case NVFXSR_TEMP:
221       if(!vpc->is_nv4x)
222          hw[0] |= (dst.index << NV30_VP_INST_DEST_TEMP_ID_SHIFT);
223       else {
224          hw[3] |= NV40_VP_INST_DEST_MASK;
225          if (slot == 0)
226             hw[0] |= (dst.index << NV40_VP_INST_VEC_DEST_TEMP_SHIFT);
227          else
228             hw[3] |= (dst.index << NV40_VP_INST_SCA_DEST_TEMP_SHIFT);
229       }
230       break;
231    case NVFXSR_OUTPUT:
232       /* TODO: this may be wrong because on nv30 COL0 and BFC0 are swapped */
233       if(vpc->is_nv4x) {
234          switch (dst.index) {
235          case NV30_VP_INST_DEST_CLP(0):
236             dst.index = NVFX_VP(INST_DEST_FOGC);
237             vp->or   |= (1 << 6);
238             break;
239          case NV30_VP_INST_DEST_CLP(1):
240             dst.index = NVFX_VP(INST_DEST_FOGC);
241             vp->or   |= (1 << 7);
242             break;
243          case NV30_VP_INST_DEST_CLP(2):
244             dst.index = NVFX_VP(INST_DEST_FOGC);
245             vp->or   |= (1 << 8);
246             break;
247          case NV30_VP_INST_DEST_CLP(3):
248             dst.index = NVFX_VP(INST_DEST_PSZ);
249             vp->or   |= (1 << 9);
250             break;
251          case NV30_VP_INST_DEST_CLP(4):
252             dst.index = NVFX_VP(INST_DEST_PSZ);
253             vp->or   |= (1 << 10);
254             break;
255          case NV30_VP_INST_DEST_CLP(5):
256             dst.index = NVFX_VP(INST_DEST_PSZ);
257             vp->or   |= (1 << 11);
258             break;
259          case NV40_VP_INST_DEST_COL0: vp->or |= (1 << 0); break;
260          case NV40_VP_INST_DEST_COL1: vp->or |= (1 << 1); break;
261          case NV40_VP_INST_DEST_BFC0: vp->or |= (1 << 2); break;
262          case NV40_VP_INST_DEST_BFC1: vp->or |= (1 << 3); break;
263          case NV40_VP_INST_DEST_FOGC: vp->or |= (1 << 4); break;
264          case NV40_VP_INST_DEST_PSZ : vp->or |= (1 << 5); break;
265          }
266       }
267 
268       if(!vpc->is_nv4x) {
269          hw[3] |= (dst.index << NV30_VP_INST_DEST_SHIFT);
270          hw[0] |= NV30_VP_INST_VEC_DEST_TEMP_MASK;
271 
272          /*XXX: no way this is entirely correct, someone needs to
273           *     figure out what exactly it is.
274           */
275          hw[3] |= 0x800;
276       } else {
277          hw[3] |= (dst.index << NV40_VP_INST_DEST_SHIFT);
278          if (slot == 0) {
279             hw[0] |= NV40_VP_INST_VEC_RESULT;
280             hw[0] |= NV40_VP_INST_VEC_DEST_TEMP_MASK;
281          } else {
282             hw[3] |= NV40_VP_INST_SCA_RESULT;
283             hw[3] |= NV40_VP_INST_SCA_DEST_TEMP_MASK;
284          }
285       }
286       break;
287    default:
288       assert(0);
289    }
290 }
291 
292 static void
nvfx_vp_emit(struct nvfx_vpc * vpc,struct nvfx_insn insn)293 nvfx_vp_emit(struct nvfx_vpc *vpc, struct nvfx_insn insn)
294 {
295    struct nv30_vertprog *vp = vpc->vp;
296    unsigned slot = insn.op >> 7;
297    unsigned op = insn.op & 0x7f;
298    uint32_t *hw;
299 
300    vp->insns = realloc(vp->insns, ++vp->nr_insns * sizeof(*vpc->vpi));
301    vpc->vpi = &vp->insns[vp->nr_insns - 1];
302    memset(vpc->vpi, 0, sizeof(*vpc->vpi));
303 
304    hw = vpc->vpi->data;
305 
306    if (insn.cc_test != NVFX_COND_TR)
307       hw[0] |= NVFX_VP(INST_COND_TEST_ENABLE);
308    hw[0] |= (insn.cc_test << NVFX_VP(INST_COND_SHIFT));
309    hw[0] |= ((insn.cc_swz[0] << NVFX_VP(INST_COND_SWZ_X_SHIFT)) |
310              (insn.cc_swz[1] << NVFX_VP(INST_COND_SWZ_Y_SHIFT)) |
311              (insn.cc_swz[2] << NVFX_VP(INST_COND_SWZ_Z_SHIFT)) |
312              (insn.cc_swz[3] << NVFX_VP(INST_COND_SWZ_W_SHIFT)));
313    if(insn.cc_update)
314       hw[0] |= NVFX_VP(INST_COND_UPDATE_ENABLE);
315 
316    if(insn.sat) {
317       assert(vpc->is_nv4x);
318       if(vpc->is_nv4x)
319          hw[0] |= NV40_VP_INST_SATURATE;
320    }
321 
322    if(!vpc->is_nv4x) {
323       if(slot == 0)
324          hw[1] |= (op << NV30_VP_INST_VEC_OPCODE_SHIFT);
325       else {
326          hw[0] |= ((op >> 4) << NV30_VP_INST_SCA_OPCODEH_SHIFT);
327          hw[1] |= ((op & 0xf) << NV30_VP_INST_SCA_OPCODEL_SHIFT);
328       }
329 //      hw[3] |= NVFX_VP(INST_SCA_DEST_TEMP_MASK);
330 //      hw[3] |= (mask << NVFX_VP(INST_VEC_WRITEMASK_SHIFT));
331 
332       if (insn.dst.type == NVFXSR_OUTPUT) {
333          if (slot)
334             hw[3] |= (insn.mask << NV30_VP_INST_SDEST_WRITEMASK_SHIFT);
335          else
336             hw[3] |= (insn.mask << NV30_VP_INST_VDEST_WRITEMASK_SHIFT);
337       } else {
338          if (slot)
339             hw[3] |= (insn.mask << NV30_VP_INST_STEMP_WRITEMASK_SHIFT);
340          else
341             hw[3] |= (insn.mask << NV30_VP_INST_VTEMP_WRITEMASK_SHIFT);
342       }
343     } else {
344       if (slot == 0) {
345          hw[1] |= (op << NV40_VP_INST_VEC_OPCODE_SHIFT);
346          hw[3] |= NV40_VP_INST_SCA_DEST_TEMP_MASK;
347          hw[3] |= (insn.mask << NV40_VP_INST_VEC_WRITEMASK_SHIFT);
348        } else {
349          hw[1] |= (op << NV40_VP_INST_SCA_OPCODE_SHIFT);
350          hw[0] |= NV40_VP_INST_VEC_DEST_TEMP_MASK ;
351          hw[3] |= (insn.mask << NV40_VP_INST_SCA_WRITEMASK_SHIFT);
352       }
353    }
354 
355    emit_dst(vpc, hw, slot, insn.dst);
356    emit_src(vpc, hw, 0, insn.src[0]);
357    emit_src(vpc, hw, 1, insn.src[1]);
358    emit_src(vpc, hw, 2, insn.src[2]);
359 
360 //   if(insn.src[0].indirect || op == NVFX_VP_INST_VEC_OP_ARL)
361 //      hw[3] |= NV40_VP_INST_SCA_RESULT;
362 }
363 
364 static inline struct nvfx_src
tgsi_src(struct nvfx_vpc * vpc,const struct tgsi_full_src_register * fsrc)365 tgsi_src(struct nvfx_vpc *vpc, const struct tgsi_full_src_register *fsrc) {
366    struct nvfx_src src;
367 
368    switch (fsrc->Register.File) {
369    case TGSI_FILE_INPUT:
370       src.reg = nvfx_reg(NVFXSR_INPUT, fsrc->Register.Index);
371       break;
372    case TGSI_FILE_CONSTANT:
373       if(fsrc->Register.Indirect) {
374          src.reg = vpc->r_const[0];
375          src.reg.index = fsrc->Register.Index;
376       } else {
377          src.reg = vpc->r_const[fsrc->Register.Index];
378       }
379       break;
380    case TGSI_FILE_IMMEDIATE:
381       src.reg = vpc->imm[fsrc->Register.Index];
382       break;
383    case TGSI_FILE_TEMPORARY:
384       src.reg = vpc->r_temp[fsrc->Register.Index];
385       break;
386    default:
387       NOUVEAU_ERR("bad src file\n");
388       src.reg.index = 0;
389       src.reg.type = -1;
390       break;
391    }
392 
393    src.abs = fsrc->Register.Absolute;
394    src.negate = fsrc->Register.Negate;
395    src.swz[0] = fsrc->Register.SwizzleX;
396    src.swz[1] = fsrc->Register.SwizzleY;
397    src.swz[2] = fsrc->Register.SwizzleZ;
398    src.swz[3] = fsrc->Register.SwizzleW;
399    src.indirect = 0;
400    src.indirect_reg = 0;
401    src.indirect_swz = 0;
402 
403    if(fsrc->Register.Indirect) {
404       if(fsrc->Indirect.File == TGSI_FILE_ADDRESS &&
405          (fsrc->Register.File == TGSI_FILE_CONSTANT ||
406           fsrc->Register.File == TGSI_FILE_INPUT)) {
407          src.indirect = 1;
408          src.indirect_reg = fsrc->Indirect.Index;
409          src.indirect_swz = fsrc->Indirect.Swizzle;
410       } else {
411          src.reg.index = 0;
412          src.reg.type = -1;
413       }
414    }
415 
416    return src;
417 }
418 
419 static inline struct nvfx_reg
tgsi_dst(struct nvfx_vpc * vpc,const struct tgsi_full_dst_register * fdst)420 tgsi_dst(struct nvfx_vpc *vpc, const struct tgsi_full_dst_register *fdst) {
421    struct nvfx_reg dst;
422 
423    switch (fdst->Register.File) {
424    case TGSI_FILE_NULL:
425       dst = nvfx_reg(NVFXSR_NONE, 0);
426       break;
427    case TGSI_FILE_OUTPUT:
428       dst = vpc->r_result[fdst->Register.Index];
429       break;
430    case TGSI_FILE_TEMPORARY:
431       dst = vpc->r_temp[fdst->Register.Index];
432       break;
433    case TGSI_FILE_ADDRESS:
434       dst = vpc->r_address[fdst->Register.Index];
435       break;
436    default:
437       NOUVEAU_ERR("bad dst file %i\n", fdst->Register.File);
438       dst.index = 0;
439       dst.type = 0;
440       break;
441    }
442 
443    return dst;
444 }
445 
446 static inline int
tgsi_mask(uint tgsi)447 tgsi_mask(uint tgsi)
448 {
449    int mask = 0;
450 
451    if (tgsi & TGSI_WRITEMASK_X) mask |= NVFX_VP_MASK_X;
452    if (tgsi & TGSI_WRITEMASK_Y) mask |= NVFX_VP_MASK_Y;
453    if (tgsi & TGSI_WRITEMASK_Z) mask |= NVFX_VP_MASK_Z;
454    if (tgsi & TGSI_WRITEMASK_W) mask |= NVFX_VP_MASK_W;
455    return mask;
456 }
457 
458 static bool
nvfx_vertprog_parse_instruction(struct nvfx_vpc * vpc,unsigned idx,const struct tgsi_full_instruction * finst)459 nvfx_vertprog_parse_instruction(struct nvfx_vpc *vpc,
460             unsigned idx, const struct tgsi_full_instruction *finst)
461 {
462    struct nvfx_src src[3], tmp;
463    struct nvfx_reg dst;
464    struct nvfx_reg final_dst;
465    struct nvfx_src none = nvfx_src(nvfx_reg(NVFXSR_NONE, 0));
466    struct nvfx_insn insn;
467    struct nvfx_relocation reloc;
468    struct nvfx_loop_entry loop;
469    bool sat = false;
470    int mask;
471    int ai = -1, ci = -1, ii = -1;
472    int i;
473    unsigned sub_depth = 0;
474 
475    for (i = 0; i < finst->Instruction.NumSrcRegs; i++) {
476       const struct tgsi_full_src_register *fsrc;
477 
478       fsrc = &finst->Src[i];
479       if (fsrc->Register.File == TGSI_FILE_TEMPORARY) {
480          src[i] = tgsi_src(vpc, fsrc);
481       }
482    }
483 
484    for (i = 0; i < finst->Instruction.NumSrcRegs; i++) {
485       const struct tgsi_full_src_register *fsrc;
486 
487       fsrc = &finst->Src[i];
488 
489       switch (fsrc->Register.File) {
490       case TGSI_FILE_INPUT:
491          if (ai == -1 || ai == fsrc->Register.Index) {
492             ai = fsrc->Register.Index;
493             src[i] = tgsi_src(vpc, fsrc);
494          } else {
495             src[i] = nvfx_src(temp(vpc));
496             nvfx_vp_emit(vpc, arith(0, VEC, MOV, src[i].reg, NVFX_VP_MASK_ALL,
497                          tgsi_src(vpc, fsrc), none, none));
498          }
499          break;
500       case TGSI_FILE_CONSTANT:
501          if ((ci == -1 && ii == -1) ||
502              ci == fsrc->Register.Index) {
503             ci = fsrc->Register.Index;
504             src[i] = tgsi_src(vpc, fsrc);
505          } else {
506             src[i] = nvfx_src(temp(vpc));
507             nvfx_vp_emit(vpc, arith(0, VEC, MOV, src[i].reg, NVFX_VP_MASK_ALL,
508                          tgsi_src(vpc, fsrc), none, none));
509          }
510          break;
511       case TGSI_FILE_IMMEDIATE:
512          if ((ci == -1 && ii == -1) ||
513              ii == fsrc->Register.Index) {
514             ii = fsrc->Register.Index;
515             src[i] = tgsi_src(vpc, fsrc);
516          } else {
517             src[i] = nvfx_src(temp(vpc));
518             nvfx_vp_emit(vpc, arith(0, VEC, MOV, src[i].reg, NVFX_VP_MASK_ALL,
519                          tgsi_src(vpc, fsrc), none, none));
520          }
521          break;
522       case TGSI_FILE_TEMPORARY:
523          /* handled above */
524          break;
525       default:
526          NOUVEAU_ERR("bad src file\n");
527          return false;
528       }
529    }
530 
531    for (i = 0; i < finst->Instruction.NumSrcRegs; i++) {
532       if(src[i].reg.type < 0)
533          return false;
534    }
535 
536    if(finst->Dst[0].Register.File == TGSI_FILE_ADDRESS &&
537       finst->Instruction.Opcode != TGSI_OPCODE_ARL)
538       return false;
539 
540    final_dst = dst  = tgsi_dst(vpc, &finst->Dst[0]);
541    mask = tgsi_mask(finst->Dst[0].Register.WriteMask);
542    if(finst->Instruction.Saturate) {
543       assert(finst->Instruction.Opcode != TGSI_OPCODE_ARL);
544       if (vpc->is_nv4x)
545          sat = true;
546       else
547       if(dst.type != NVFXSR_TEMP)
548          dst = temp(vpc);
549    }
550 
551    switch (finst->Instruction.Opcode) {
552    case TGSI_OPCODE_ADD:
553       nvfx_vp_emit(vpc, arith(sat, VEC, ADD, dst, mask, src[0], none, src[1]));
554       break;
555    case TGSI_OPCODE_ARL:
556       nvfx_vp_emit(vpc, arith(0, VEC, ARL, dst, mask, src[0], none, none));
557       break;
558    case TGSI_OPCODE_CEIL:
559       tmp = nvfx_src(temp(vpc));
560       nvfx_vp_emit(vpc, arith(0, VEC, FLR, tmp.reg, mask, neg(src[0]), none, none));
561       nvfx_vp_emit(vpc, arith(sat, VEC, MOV, dst, mask, neg(tmp), none, none));
562       break;
563    case TGSI_OPCODE_CMP:
564       insn = arith(0, VEC, MOV, none.reg, mask, src[0], none, none);
565       insn.cc_update = 1;
566       nvfx_vp_emit(vpc, insn);
567 
568       insn = arith(sat, VEC, MOV, dst, mask, src[2], none, none);
569       insn.cc_test = NVFX_COND_GE;
570       nvfx_vp_emit(vpc, insn);
571 
572       insn = arith(sat, VEC, MOV, dst, mask, src[1], none, none);
573       insn.cc_test = NVFX_COND_LT;
574       nvfx_vp_emit(vpc, insn);
575       break;
576    case TGSI_OPCODE_COS:
577       nvfx_vp_emit(vpc, arith(sat, SCA, COS, dst, mask, none, none, src[0]));
578       break;
579    case TGSI_OPCODE_DP2:
580       tmp = nvfx_src(temp(vpc));
581       nvfx_vp_emit(vpc, arith(0, VEC, MUL, tmp.reg, NVFX_VP_MASK_X | NVFX_VP_MASK_Y, src[0], src[1], none));
582       nvfx_vp_emit(vpc, arith(sat, VEC, ADD, dst, mask, swz(tmp, X, X, X, X), none, swz(tmp, Y, Y, Y, Y)));
583       break;
584    case TGSI_OPCODE_DP3:
585       nvfx_vp_emit(vpc, arith(sat, VEC, DP3, dst, mask, src[0], src[1], none));
586       break;
587    case TGSI_OPCODE_DP4:
588       nvfx_vp_emit(vpc, arith(sat, VEC, DP4, dst, mask, src[0], src[1], none));
589       break;
590    case TGSI_OPCODE_DST:
591       nvfx_vp_emit(vpc, arith(sat, VEC, DST, dst, mask, src[0], src[1], none));
592       break;
593    case TGSI_OPCODE_EX2:
594       nvfx_vp_emit(vpc, arith(sat, SCA, EX2, dst, mask, none, none, src[0]));
595       break;
596    case TGSI_OPCODE_EXP:
597       nvfx_vp_emit(vpc, arith(sat, SCA, EXP, dst, mask, none, none, src[0]));
598       break;
599    case TGSI_OPCODE_FLR:
600       nvfx_vp_emit(vpc, arith(sat, VEC, FLR, dst, mask, src[0], none, none));
601       break;
602    case TGSI_OPCODE_FRC:
603       nvfx_vp_emit(vpc, arith(sat, VEC, FRC, dst, mask, src[0], none, none));
604       break;
605    case TGSI_OPCODE_LG2:
606       nvfx_vp_emit(vpc, arith(sat, SCA, LG2, dst, mask, none, none, src[0]));
607       break;
608    case TGSI_OPCODE_LIT:
609       nvfx_vp_emit(vpc, arith(sat, SCA, LIT, dst, mask, none, none, src[0]));
610       break;
611    case TGSI_OPCODE_LOG:
612       nvfx_vp_emit(vpc, arith(sat, SCA, LOG, dst, mask, none, none, src[0]));
613       break;
614    case TGSI_OPCODE_LRP:
615       tmp = nvfx_src(temp(vpc));
616       nvfx_vp_emit(vpc, arith(0, VEC, MAD, tmp.reg, mask, neg(src[0]), src[2], src[2]));
617       nvfx_vp_emit(vpc, arith(sat, VEC, MAD, dst, mask, src[0], src[1], tmp));
618       break;
619    case TGSI_OPCODE_MAD:
620       nvfx_vp_emit(vpc, arith(sat, VEC, MAD, dst, mask, src[0], src[1], src[2]));
621       break;
622    case TGSI_OPCODE_MAX:
623       nvfx_vp_emit(vpc, arith(sat, VEC, MAX, dst, mask, src[0], src[1], none));
624       break;
625    case TGSI_OPCODE_MIN:
626       nvfx_vp_emit(vpc, arith(sat, VEC, MIN, dst, mask, src[0], src[1], none));
627       break;
628    case TGSI_OPCODE_MOV:
629       nvfx_vp_emit(vpc, arith(sat, VEC, MOV, dst, mask, src[0], none, none));
630       break;
631    case TGSI_OPCODE_MUL:
632       nvfx_vp_emit(vpc, arith(sat, VEC, MUL, dst, mask, src[0], src[1], none));
633       break;
634    case TGSI_OPCODE_NOP:
635       break;
636    case TGSI_OPCODE_POW:
637       tmp = nvfx_src(temp(vpc));
638       nvfx_vp_emit(vpc, arith(0, SCA, LG2, tmp.reg, NVFX_VP_MASK_X, none, none, swz(src[0], X, X, X, X)));
639       nvfx_vp_emit(vpc, arith(0, VEC, MUL, tmp.reg, NVFX_VP_MASK_X, swz(tmp, X, X, X, X), swz(src[1], X, X, X, X), none));
640       nvfx_vp_emit(vpc, arith(sat, SCA, EX2, dst, mask, none, none, swz(tmp, X, X, X, X)));
641       break;
642    case TGSI_OPCODE_RCP:
643       nvfx_vp_emit(vpc, arith(sat, SCA, RCP, dst, mask, none, none, src[0]));
644       break;
645    case TGSI_OPCODE_RSQ:
646       nvfx_vp_emit(vpc, arith(sat, SCA, RSQ, dst, mask, none, none, abs(src[0])));
647       break;
648    case TGSI_OPCODE_SEQ:
649       nvfx_vp_emit(vpc, arith(sat, VEC, SEQ, dst, mask, src[0], src[1], none));
650       break;
651    case TGSI_OPCODE_SGE:
652       nvfx_vp_emit(vpc, arith(sat, VEC, SGE, dst, mask, src[0], src[1], none));
653       break;
654    case TGSI_OPCODE_SGT:
655       nvfx_vp_emit(vpc, arith(sat, VEC, SGT, dst, mask, src[0], src[1], none));
656       break;
657    case TGSI_OPCODE_SIN:
658       nvfx_vp_emit(vpc, arith(sat, SCA, SIN, dst, mask, none, none, src[0]));
659       break;
660    case TGSI_OPCODE_SLE:
661       nvfx_vp_emit(vpc, arith(sat, VEC, SLE, dst, mask, src[0], src[1], none));
662       break;
663    case TGSI_OPCODE_SLT:
664       nvfx_vp_emit(vpc, arith(sat, VEC, SLT, dst, mask, src[0], src[1], none));
665       break;
666    case TGSI_OPCODE_SNE:
667       nvfx_vp_emit(vpc, arith(sat, VEC, SNE, dst, mask, src[0], src[1], none));
668       break;
669    case TGSI_OPCODE_SSG:
670       nvfx_vp_emit(vpc, arith(sat, VEC, SSG, dst, mask, src[0], none, none));
671       break;
672    case TGSI_OPCODE_TRUNC:
673       tmp = nvfx_src(temp(vpc));
674       insn = arith(0, VEC, MOV, none.reg, mask, src[0], none, none);
675       insn.cc_update = 1;
676       nvfx_vp_emit(vpc, insn);
677 
678       nvfx_vp_emit(vpc, arith(0, VEC, FLR, tmp.reg, mask, abs(src[0]), none, none));
679       nvfx_vp_emit(vpc, arith(sat, VEC, MOV, dst, mask, tmp, none, none));
680 
681       insn = arith(sat, VEC, MOV, dst, mask, neg(tmp), none, none);
682       insn.cc_test = NVFX_COND_LT;
683       nvfx_vp_emit(vpc, insn);
684       break;
685    case TGSI_OPCODE_IF:
686       insn = arith(0, VEC, MOV, none.reg, NVFX_VP_MASK_X, src[0], none, none);
687       insn.cc_update = 1;
688       nvfx_vp_emit(vpc, insn);
689 
690       reloc.location = vpc->vp->nr_insns;
691       reloc.target = finst->Label.Label + 1;
692       util_dynarray_append(&vpc->label_relocs, struct nvfx_relocation, reloc);
693 
694       insn = arith(0, SCA, BRA, none.reg, 0, none, none, none);
695       insn.cc_test = NVFX_COND_EQ;
696       insn.cc_swz[0] = insn.cc_swz[1] = insn.cc_swz[2] = insn.cc_swz[3] = 0;
697       nvfx_vp_emit(vpc, insn);
698       break;
699    case TGSI_OPCODE_ELSE:
700    case TGSI_OPCODE_CAL:
701       reloc.location = vpc->vp->nr_insns;
702       reloc.target = finst->Label.Label;
703       util_dynarray_append(&vpc->label_relocs, struct nvfx_relocation, reloc);
704 
705       if(finst->Instruction.Opcode == TGSI_OPCODE_CAL)
706          insn = arith(0, SCA, CAL, none.reg, 0, none, none, none);
707       else
708          insn = arith(0, SCA, BRA, none.reg, 0, none, none, none);
709       nvfx_vp_emit(vpc, insn);
710       break;
711    case TGSI_OPCODE_RET:
712       if(sub_depth || !vpc->vp->enabled_ucps) {
713          tmp = none;
714          tmp.swz[0] = tmp.swz[1] = tmp.swz[2] = tmp.swz[3] = 0;
715          nvfx_vp_emit(vpc, arith(0, SCA, RET, none.reg, 0, none, none, tmp));
716       } else {
717          reloc.location = vpc->vp->nr_insns;
718          reloc.target = vpc->info->num_instructions;
719          util_dynarray_append(&vpc->label_relocs, struct nvfx_relocation, reloc);
720          nvfx_vp_emit(vpc, arith(0, SCA, BRA, none.reg, 0, none, none, none));
721       }
722       break;
723    case TGSI_OPCODE_BGNSUB:
724       ++sub_depth;
725       break;
726    case TGSI_OPCODE_ENDSUB:
727       --sub_depth;
728       break;
729    case TGSI_OPCODE_ENDIF:
730       /* nothing to do here */
731       break;
732    case TGSI_OPCODE_BGNLOOP:
733       loop.cont_target = idx;
734       loop.brk_target = finst->Label.Label + 1;
735       util_dynarray_append(&vpc->loop_stack, struct nvfx_loop_entry, loop);
736       break;
737    case TGSI_OPCODE_ENDLOOP:
738       loop = util_dynarray_pop(&vpc->loop_stack, struct nvfx_loop_entry);
739 
740       reloc.location = vpc->vp->nr_insns;
741       reloc.target = loop.cont_target;
742       util_dynarray_append(&vpc->label_relocs, struct nvfx_relocation, reloc);
743 
744       nvfx_vp_emit(vpc, arith(0, SCA, BRA, none.reg, 0, none, none, none));
745       break;
746    case TGSI_OPCODE_CONT:
747       loop = util_dynarray_top(&vpc->loop_stack, struct nvfx_loop_entry);
748 
749       reloc.location = vpc->vp->nr_insns;
750       reloc.target = loop.cont_target;
751       util_dynarray_append(&vpc->label_relocs, struct nvfx_relocation, reloc);
752 
753       nvfx_vp_emit(vpc, arith(0, SCA, BRA, none.reg, 0, none, none, none));
754       break;
755    case TGSI_OPCODE_BRK:
756       loop = util_dynarray_top(&vpc->loop_stack, struct nvfx_loop_entry);
757 
758       reloc.location = vpc->vp->nr_insns;
759       reloc.target = loop.brk_target;
760       util_dynarray_append(&vpc->label_relocs, struct nvfx_relocation, reloc);
761 
762       nvfx_vp_emit(vpc, arith(0, SCA, BRA, none.reg, 0, none, none, none));
763       break;
764    case TGSI_OPCODE_END:
765       assert(!sub_depth);
766       if(vpc->vp->enabled_ucps) {
767          if(idx != (vpc->info->num_instructions - 1)) {
768             reloc.location = vpc->vp->nr_insns;
769             reloc.target = vpc->info->num_instructions;
770             util_dynarray_append(&vpc->label_relocs, struct nvfx_relocation, reloc);
771             nvfx_vp_emit(vpc, arith(0, SCA, BRA, none.reg, 0, none, none, none));
772          }
773       } else {
774          if(vpc->vp->nr_insns)
775             vpc->vp->insns[vpc->vp->nr_insns - 1].data[3] |= NVFX_VP_INST_LAST;
776          nvfx_vp_emit(vpc, arith(0, VEC, NOP, none.reg, 0, none, none, none));
777          vpc->vp->insns[vpc->vp->nr_insns - 1].data[3] |= NVFX_VP_INST_LAST;
778       }
779       break;
780    default:
781       NOUVEAU_ERR("invalid opcode %d\n", finst->Instruction.Opcode);
782       return false;
783    }
784 
785    if(finst->Instruction.Saturate && !vpc->is_nv4x) {
786       if (!vpc->r_0_1.type)
787          vpc->r_0_1 = constant(vpc, -1, 0, 1, 0, 0);
788       nvfx_vp_emit(vpc, arith(0, VEC, MAX, dst, mask, nvfx_src(dst), swz(nvfx_src(vpc->r_0_1), X, X, X, X), none));
789       nvfx_vp_emit(vpc, arith(0, VEC, MIN, final_dst, mask, nvfx_src(dst), swz(nvfx_src(vpc->r_0_1), Y, Y, Y, Y), none));
790    }
791 
792    release_temps(vpc);
793    return true;
794 }
795 
796 static bool
nvfx_vertprog_parse_decl_output(struct nvfx_vpc * vpc,const struct tgsi_full_declaration * fdec)797 nvfx_vertprog_parse_decl_output(struct nvfx_vpc *vpc,
798                                 const struct tgsi_full_declaration *fdec)
799 {
800    unsigned num_texcoords = vpc->is_nv4x ? 10 : 8;
801    unsigned idx = fdec->Range.First;
802    unsigned semantic_index = fdec->Semantic.Index;
803    int hw = 0, i;
804 
805    switch (fdec->Semantic.Name) {
806    case TGSI_SEMANTIC_POSITION:
807       hw = NVFX_VP(INST_DEST_POS);
808       vpc->hpos_idx = idx;
809       break;
810    case TGSI_SEMANTIC_CLIPVERTEX:
811       vpc->r_result[idx] = temp(vpc);
812       vpc->r_temps_discard = 0;
813       vpc->cvtx_idx = idx;
814       return true;
815    case TGSI_SEMANTIC_COLOR:
816       if (fdec->Semantic.Index == 0) {
817          hw = NVFX_VP(INST_DEST_COL0);
818       } else
819       if (fdec->Semantic.Index == 1) {
820          hw = NVFX_VP(INST_DEST_COL1);
821       } else {
822          NOUVEAU_ERR("bad colour semantic index\n");
823          return false;
824       }
825       break;
826    case TGSI_SEMANTIC_BCOLOR:
827       if (fdec->Semantic.Index == 0) {
828          hw = NVFX_VP(INST_DEST_BFC0);
829       } else
830       if (fdec->Semantic.Index == 1) {
831          hw = NVFX_VP(INST_DEST_BFC1);
832       } else {
833          NOUVEAU_ERR("bad bcolour semantic index\n");
834          return false;
835       }
836       break;
837    case TGSI_SEMANTIC_FOG:
838       hw = NVFX_VP(INST_DEST_FOGC);
839       break;
840    case TGSI_SEMANTIC_PSIZE:
841       hw = NVFX_VP(INST_DEST_PSZ);
842       break;
843    case TGSI_SEMANTIC_GENERIC:
844       /* this is really an identifier for VP/FP linkage */
845       semantic_index += 8;
846       FALLTHROUGH;
847    case TGSI_SEMANTIC_TEXCOORD:
848       for (i = 0; i < num_texcoords; i++) {
849          if (vpc->vp->texcoord[i] == semantic_index) {
850             hw = NVFX_VP(INST_DEST_TC(i));
851             break;
852          }
853       }
854 
855       if (i == num_texcoords) {
856          vpc->r_result[idx] = nvfx_reg(NVFXSR_NONE, 0);
857          return true;
858       }
859       break;
860    case TGSI_SEMANTIC_EDGEFLAG:
861       vpc->r_result[idx] = nvfx_reg(NVFXSR_NONE, 0);
862       return true;
863    default:
864       NOUVEAU_ERR("bad output semantic\n");
865       return false;
866    }
867 
868    vpc->r_result[idx] = nvfx_reg(NVFXSR_OUTPUT, hw);
869    return true;
870 }
871 
872 static bool
nvfx_vertprog_prepare(struct nvfx_vpc * vpc)873 nvfx_vertprog_prepare(struct nvfx_vpc *vpc)
874 {
875    struct tgsi_parse_context p;
876    int high_const = -1, high_temp = -1, high_addr = -1, nr_imm = 0, i;
877 
878    tgsi_parse_init(&p, vpc->pipe.tokens);
879    while (!tgsi_parse_end_of_tokens(&p)) {
880       const union tgsi_full_token *tok = &p.FullToken;
881 
882       tgsi_parse_token(&p);
883       switch(tok->Token.Type) {
884       case TGSI_TOKEN_TYPE_IMMEDIATE:
885          nr_imm++;
886          break;
887       case TGSI_TOKEN_TYPE_DECLARATION:
888       {
889          const struct tgsi_full_declaration *fdec;
890 
891          fdec = &p.FullToken.FullDeclaration;
892          switch (fdec->Declaration.File) {
893          case TGSI_FILE_TEMPORARY:
894             if (fdec->Range.Last > high_temp) {
895                high_temp =
896                   fdec->Range.Last;
897             }
898             break;
899          case TGSI_FILE_ADDRESS:
900             if (fdec->Range.Last > high_addr) {
901                high_addr =
902                   fdec->Range.Last;
903             }
904             break;
905          case TGSI_FILE_CONSTANT:
906             if (fdec->Range.Last > high_const) {
907                high_const =
908                      fdec->Range.Last;
909             }
910             break;
911          case TGSI_FILE_OUTPUT:
912             if (!nvfx_vertprog_parse_decl_output(vpc, fdec))
913                return false;
914             break;
915          default:
916             break;
917          }
918       }
919          break;
920       default:
921          break;
922       }
923    }
924    tgsi_parse_free(&p);
925 
926    if (nr_imm) {
927       vpc->imm = CALLOC(nr_imm, sizeof(struct nvfx_reg));
928       assert(vpc->imm);
929    }
930 
931    if (++high_temp) {
932       vpc->r_temp = CALLOC(high_temp, sizeof(struct nvfx_reg));
933       for (i = 0; i < high_temp; i++)
934          vpc->r_temp[i] = temp(vpc);
935    }
936 
937    if (++high_addr) {
938       vpc->r_address = CALLOC(high_addr, sizeof(struct nvfx_reg));
939       for (i = 0; i < high_addr; i++)
940          vpc->r_address[i] = nvfx_reg(NVFXSR_TEMP, i);
941    }
942 
943    if(++high_const) {
944       vpc->r_const = CALLOC(high_const, sizeof(struct nvfx_reg));
945       for (i = 0; i < high_const; i++)
946          vpc->r_const[i] = constant(vpc, i, 0, 0, 0, 0);
947    }
948 
949    vpc->r_temps_discard = 0;
950    return true;
951 }
952 
953 DEBUG_GET_ONCE_BOOL_OPTION(nvfx_dump_vp, "NVFX_DUMP_VP", false)
954 
955 bool
_nvfx_vertprog_translate(uint16_t oclass,struct nv30_vertprog * vp)956 _nvfx_vertprog_translate(uint16_t oclass, struct nv30_vertprog *vp)
957 {
958    struct tgsi_parse_context parse;
959    struct nvfx_vpc *vpc = NULL;
960    struct nvfx_src none = nvfx_src(nvfx_reg(NVFXSR_NONE, 0));
961    struct util_dynarray insns;
962    int i, ucps;
963 
964    vp->translated = false;
965    vp->nr_insns = 0;
966    vp->nr_consts = 0;
967 
968    vpc = CALLOC_STRUCT(nvfx_vpc);
969    if (!vpc)
970       return false;
971    vpc->is_nv4x = (oclass >= NV40_3D_CLASS) ? ~0 : 0;
972    vpc->vp   = vp;
973    vpc->pipe = vp->pipe;
974    vpc->info = &vp->info;
975    vpc->cvtx_idx = -1;
976 
977    if (!nvfx_vertprog_prepare(vpc)) {
978       FREE(vpc);
979       return false;
980    }
981 
982    /* Redirect post-transform vertex position to a temp if user clip
983     * planes are enabled.  We need to append code to the vtxprog
984     * to handle clip planes later.
985     */
986    if (vp->enabled_ucps && vpc->cvtx_idx < 0)  {
987       vpc->r_result[vpc->hpos_idx] = temp(vpc);
988       vpc->r_temps_discard = 0;
989       vpc->cvtx_idx = vpc->hpos_idx;
990    }
991 
992    util_dynarray_init(&insns, NULL);
993 
994    tgsi_parse_init(&parse, vp->pipe.tokens);
995    while (!tgsi_parse_end_of_tokens(&parse)) {
996       tgsi_parse_token(&parse);
997 
998       switch (parse.FullToken.Token.Type) {
999       case TGSI_TOKEN_TYPE_IMMEDIATE:
1000       {
1001          const struct tgsi_full_immediate *imm;
1002 
1003          imm = &parse.FullToken.FullImmediate;
1004          assert(imm->Immediate.DataType == TGSI_IMM_FLOAT32);
1005          assert(imm->Immediate.NrTokens == 4 + 1);
1006          vpc->imm[vpc->nr_imm++] =
1007             constant(vpc, -1,
1008                 imm->u[0].Float,
1009                 imm->u[1].Float,
1010                 imm->u[2].Float,
1011                 imm->u[3].Float);
1012       }
1013          break;
1014       case TGSI_TOKEN_TYPE_INSTRUCTION:
1015       {
1016          const struct tgsi_full_instruction *finst;
1017          unsigned idx = insns.size >> 2;
1018          util_dynarray_append(&insns, unsigned, vp->nr_insns);
1019          finst = &parse.FullToken.FullInstruction;
1020          if (!nvfx_vertprog_parse_instruction(vpc, idx, finst))
1021             goto out;
1022       }
1023          break;
1024       default:
1025          break;
1026       }
1027    }
1028 
1029    util_dynarray_append(&insns, unsigned, vp->nr_insns);
1030 
1031    for(unsigned i = 0; i < vpc->label_relocs.size; i += sizeof(struct nvfx_relocation))
1032    {
1033       struct nvfx_relocation* label_reloc = (struct nvfx_relocation*)((char*)vpc->label_relocs.data + i);
1034       struct nvfx_relocation hw_reloc;
1035 
1036       hw_reloc.location = label_reloc->location;
1037       hw_reloc.target = ((unsigned*)insns.data)[label_reloc->target];
1038 
1039       //debug_printf("hw %u -> tgsi %u = hw %u\n", hw_reloc.location, label_reloc->target, hw_reloc.target);
1040 
1041       util_dynarray_append(&vp->branch_relocs, struct nvfx_relocation, hw_reloc);
1042    }
1043    util_dynarray_fini(&insns);
1044    util_dynarray_trim(&vp->branch_relocs);
1045 
1046    /* XXX: what if we add a RET before?!  make sure we jump here...*/
1047 
1048    /* Write out HPOS if it was redirected to a temp earlier */
1049    if (vpc->r_result[vpc->hpos_idx].type != NVFXSR_OUTPUT) {
1050       struct nvfx_reg hpos = nvfx_reg(NVFXSR_OUTPUT,
1051                   NVFX_VP(INST_DEST_POS));
1052       struct nvfx_src htmp = nvfx_src(vpc->r_result[vpc->hpos_idx]);
1053 
1054       nvfx_vp_emit(vpc, arith(0, VEC, MOV, hpos, NVFX_VP_MASK_ALL, htmp, none, none));
1055    }
1056 
1057    /* Insert code to handle user clip planes */
1058    ucps = vp->enabled_ucps;
1059    while (ucps) {
1060       int i = ffs(ucps) - 1; ucps &= ~(1 << i);
1061       struct nvfx_reg cdst = nvfx_reg(NVFXSR_OUTPUT, NV30_VP_INST_DEST_CLP(i));
1062       struct nvfx_src ceqn = nvfx_src(nvfx_reg(NVFXSR_CONST, 512 + i));
1063       struct nvfx_src htmp = nvfx_src(vpc->r_result[vpc->cvtx_idx]);
1064       unsigned mask;
1065 
1066       if(vpc->is_nv4x)
1067       {
1068          switch (i) {
1069          case 0: case 3: mask = NVFX_VP_MASK_Y; break;
1070          case 1: case 4: mask = NVFX_VP_MASK_Z; break;
1071          case 2: case 5: mask = NVFX_VP_MASK_W; break;
1072          default:
1073             NOUVEAU_ERR("invalid clip dist #%d\n", i);
1074             goto out;
1075          }
1076       }
1077       else
1078          mask = NVFX_VP_MASK_X;
1079 
1080       nvfx_vp_emit(vpc, arith(0, VEC, DP4, cdst, mask, htmp, ceqn, none));
1081    }
1082 
1083    if (vpc->vp->nr_insns)
1084       vpc->vp->insns[vpc->vp->nr_insns - 1].data[3] |= NVFX_VP_INST_LAST;
1085 
1086    if(debug_get_option_nvfx_dump_vp())
1087    {
1088       debug_printf("\n");
1089       tgsi_dump(vpc->pipe.tokens, 0);
1090 
1091       debug_printf("\n%s vertex program:\n", vpc->is_nv4x ? "nv4x" : "nv3x");
1092       for (i = 0; i < vp->nr_insns; i++)
1093          debug_printf("%3u: %08x %08x %08x %08x\n", i, vp->insns[i].data[0], vp->insns[i].data[1], vp->insns[i].data[2], vp->insns[i].data[3]);
1094       debug_printf("\n");
1095    }
1096 
1097    vp->translated = true;
1098 
1099 out:
1100    tgsi_parse_free(&parse);
1101    if (vpc) {
1102       util_dynarray_fini(&vpc->label_relocs);
1103       util_dynarray_fini(&vpc->loop_stack);
1104       FREE(vpc->r_temp);
1105       FREE(vpc->r_address);
1106       FREE(vpc->r_const);
1107       FREE(vpc->imm);
1108       FREE(vpc);
1109    }
1110 
1111    return vp->translated;
1112 }
1113