1 /*
2 * Copyright © 2012 Rob Clark <[email protected]>
3 * SPDX-License-Identifier: MIT
4 *
5 * Authors:
6 * Rob Clark <[email protected]>
7 */
8
9 #include "pipe/p_defines.h"
10 #include "pipe/p_screen.h"
11 #include "pipe/p_state.h"
12
13 #include "util/format/u_format.h"
14 #include "util/format/u_format_s3tc.h"
15 #include "util/u_debug.h"
16 #include "util/u_inlines.h"
17 #include "util/u_memory.h"
18 #include "util/u_screen.h"
19 #include "util/u_string.h"
20 #include "util/xmlconfig.h"
21
22 #include "util/os_time.h"
23
24 #include <errno.h>
25 #include <stdio.h>
26 #include <stdlib.h>
27 #include "drm-uapi/drm_fourcc.h"
28 #include <sys/sysinfo.h>
29
30 #include "freedreno_fence.h"
31 #include "freedreno_perfetto.h"
32 #include "freedreno_query.h"
33 #include "freedreno_resource.h"
34 #include "freedreno_screen.h"
35 #include "freedreno_util.h"
36
37 #include "a2xx/fd2_screen.h"
38 #include "a3xx/fd3_screen.h"
39 #include "a4xx/fd4_screen.h"
40 #include "a5xx/fd5_screen.h"
41 #include "a6xx/fd6_screen.h"
42
43 /* for fd_get_driver/device_uuid() */
44 #include "common/freedreno_uuid.h"
45
46 #include "a2xx/ir2.h"
47 #include "ir3/ir3_descriptor.h"
48 #include "ir3/ir3_gallium.h"
49 #include "ir3/ir3_nir.h"
50
51 /* clang-format off */
52 static const struct debug_named_value fd_debug_options[] = {
53 {"msgs", FD_DBG_MSGS, "Print debug messages"},
54 {"disasm", FD_DBG_DISASM, "Dump TGSI and adreno shader disassembly (a2xx only, see IR3_SHADER_DEBUG)"},
55 {"dclear", FD_DBG_DCLEAR, "Mark all state dirty after clear"},
56 {"ddraw", FD_DBG_DDRAW, "Mark all state dirty after draw"},
57 {"noscis", FD_DBG_NOSCIS, "Disable scissor optimization"},
58 {"direct", FD_DBG_DIRECT, "Force inline (SS_DIRECT) state loads"},
59 {"gmem", FD_DBG_GMEM, "Use gmem rendering when it is permitted"},
60 {"perf", FD_DBG_PERF, "Enable performance warnings"},
61 {"nobin", FD_DBG_NOBIN, "Disable hw binning"},
62 {"sysmem", FD_DBG_SYSMEM, "Use sysmem only rendering (no tiling)"},
63 {"serialc", FD_DBG_SERIALC, "Disable asynchronous shader compile"},
64 {"shaderdb", FD_DBG_SHADERDB, "Enable shaderdb output"},
65 {"flush", FD_DBG_FLUSH, "Force flush after every draw"},
66 {"inorder", FD_DBG_INORDER, "Disable reordering for draws/blits"},
67 {"bstat", FD_DBG_BSTAT, "Print batch stats at context destroy"},
68 {"nogrow", FD_DBG_NOGROW, "Disable \"growable\" cmdstream buffers, even if kernel supports it"},
69 {"lrz", FD_DBG_LRZ, "Enable experimental LRZ support (a5xx)"},
70 {"noindirect",FD_DBG_NOINDR, "Disable hw indirect draws (emulate on CPU)"},
71 {"noblit", FD_DBG_NOBLIT, "Disable blitter (fallback to generic blit path)"},
72 {"hiprio", FD_DBG_HIPRIO, "Force high-priority context"},
73 {"ttile", FD_DBG_TTILE, "Enable texture tiling (a2xx/a3xx/a5xx)"},
74 {"perfcntrs", FD_DBG_PERFC, "Expose performance counters"},
75 {"noubwc", FD_DBG_NOUBWC, "Disable UBWC for all internal buffers"},
76 {"nolrz", FD_DBG_NOLRZ, "Disable LRZ (a6xx)"},
77 {"notile", FD_DBG_NOTILE, "Disable tiling for all internal buffers"},
78 {"layout", FD_DBG_LAYOUT, "Dump resource layouts"},
79 {"nofp16", FD_DBG_NOFP16, "Disable mediump precision lowering"},
80 {"nohw", FD_DBG_NOHW, "Disable submitting commands to the HW"},
81 {"nosbin", FD_DBG_NOSBIN, "Execute GMEM bins in raster order instead of 'S' pattern"},
82 {"stomp", FD_DBG_STOMP, "Enable register stomper"},
83 DEBUG_NAMED_VALUE_END
84 };
85 /* clang-format on */
86
87 DEBUG_GET_ONCE_FLAGS_OPTION(fd_mesa_debug, "FD_MESA_DEBUG", fd_debug_options, 0)
88
89 int fd_mesa_debug = 0;
90 bool fd_binning_enabled = true;
91
92 static const char *
fd_screen_get_name(struct pipe_screen * pscreen)93 fd_screen_get_name(struct pipe_screen *pscreen)
94 {
95 return fd_dev_name(fd_screen(pscreen)->dev_id);
96 }
97
98 static const char *
fd_screen_get_vendor(struct pipe_screen * pscreen)99 fd_screen_get_vendor(struct pipe_screen *pscreen)
100 {
101 return "freedreno";
102 }
103
104 static const char *
fd_screen_get_device_vendor(struct pipe_screen * pscreen)105 fd_screen_get_device_vendor(struct pipe_screen *pscreen)
106 {
107 return "Qualcomm";
108 }
109
110 static void
fd_get_sample_pixel_grid(struct pipe_screen * pscreen,unsigned sample_count,unsigned * out_width,unsigned * out_height)111 fd_get_sample_pixel_grid(struct pipe_screen *pscreen, unsigned sample_count,
112 unsigned *out_width, unsigned *out_height)
113 {
114 *out_width = 1;
115 *out_height = 1;
116 }
117
118 static uint64_t
fd_screen_get_timestamp(struct pipe_screen * pscreen)119 fd_screen_get_timestamp(struct pipe_screen *pscreen)
120 {
121 struct fd_screen *screen = fd_screen(pscreen);
122
123 if (screen->has_timestamp) {
124 uint64_t n;
125 fd_pipe_get_param(screen->pipe, FD_TIMESTAMP, &n);
126 return ticks_to_ns(n);
127 } else {
128 int64_t cpu_time = os_time_get_nano();
129 return cpu_time + screen->cpu_gpu_time_delta;
130 }
131 }
132
133 static void
fd_screen_destroy(struct pipe_screen * pscreen)134 fd_screen_destroy(struct pipe_screen *pscreen)
135 {
136 struct fd_screen *screen = fd_screen(pscreen);
137
138 if (screen->aux_ctx)
139 screen->aux_ctx->destroy(screen->aux_ctx);
140
141 if (screen->tess_bo)
142 fd_bo_del(screen->tess_bo);
143
144 if (screen->pipe)
145 fd_pipe_del(screen->pipe);
146
147 if (screen->dev) {
148 fd_device_purge(screen->dev);
149 fd_device_del(screen->dev);
150 }
151
152 if (screen->ro)
153 screen->ro->destroy(screen->ro);
154
155 fd_bc_fini(&screen->batch_cache);
156 fd_gmem_screen_fini(pscreen);
157
158 slab_destroy_parent(&screen->transfer_pool);
159
160 simple_mtx_destroy(&screen->lock);
161
162 util_idalloc_mt_fini(&screen->buffer_ids);
163
164 u_transfer_helper_destroy(pscreen->transfer_helper);
165
166 if (screen->compiler)
167 ir3_screen_fini(pscreen);
168
169 free(screen->perfcntr_queries);
170 free(screen);
171 }
172
173 static uint64_t
get_memory_size(struct fd_screen * screen)174 get_memory_size(struct fd_screen *screen)
175 {
176 uint64_t system_memory;
177
178 if (!os_get_total_physical_memory(&system_memory))
179 return 0;
180 if (fd_device_version(screen->dev) >= FD_VERSION_VA_SIZE) {
181 uint64_t va_size;
182 if (!fd_pipe_get_param(screen->pipe, FD_VA_SIZE, &va_size)) {
183 system_memory = MIN2(system_memory, va_size);
184 }
185 }
186
187 return system_memory;
188 }
189
190 static void
fd_query_memory_info(struct pipe_screen * pscreen,struct pipe_memory_info * info)191 fd_query_memory_info(struct pipe_screen *pscreen,
192 struct pipe_memory_info *info)
193 {
194 unsigned mem = get_memory_size(fd_screen(pscreen)) >> 10;
195
196 memset(info, 0, sizeof(*info));
197
198 info->total_device_memory = mem;
199 info->avail_device_memory = mem;
200 }
201
202
203 /*
204 TODO either move caps to a2xx/a3xx specific code, or maybe have some
205 tables for things that differ if the delta is not too much..
206 */
207 static int
fd_screen_get_param(struct pipe_screen * pscreen,enum pipe_cap param)208 fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
209 {
210 struct fd_screen *screen = fd_screen(pscreen);
211
212 /* this is probably not totally correct.. but it's a start: */
213 switch (param) {
214 /* Supported features (boolean caps). */
215 case PIPE_CAP_NPOT_TEXTURES:
216 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
217 case PIPE_CAP_ANISOTROPIC_FILTER:
218 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
219 case PIPE_CAP_TEXTURE_SWIZZLE:
220 case PIPE_CAP_FS_COORD_ORIGIN_UPPER_LEFT:
221 case PIPE_CAP_SEAMLESS_CUBE_MAP:
222 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
223 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
224 case PIPE_CAP_STRING_MARKER:
225 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
226 case PIPE_CAP_TEXTURE_BARRIER:
227 case PIPE_CAP_INVALIDATE_BUFFER:
228 case PIPE_CAP_GLSL_TESS_LEVELS_AS_INPUTS:
229 case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE:
230 case PIPE_CAP_GL_SPIRV:
231 case PIPE_CAP_FBFETCH_COHERENT:
232 case PIPE_CAP_HAS_CONST_BW:
233 return 1;
234
235 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
236 case PIPE_CAP_MULTI_DRAW_INDIRECT:
237 case PIPE_CAP_DRAW_PARAMETERS:
238 case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
239 case PIPE_CAP_DEPTH_BOUNDS_TEST:
240 return is_a6xx(screen);
241
242 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
243 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
244 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
245 return is_a2xx(screen);
246
247 case PIPE_CAP_FS_COORD_PIXEL_CENTER_INTEGER:
248 return is_a2xx(screen);
249 case PIPE_CAP_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
250 return !is_a2xx(screen);
251
252 case PIPE_CAP_PACKED_UNIFORMS:
253 return !is_a2xx(screen);
254
255 case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
256 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
257 return screen->has_robustness;
258
259 case PIPE_CAP_COMPUTE:
260 return has_compute(screen);
261
262 case PIPE_CAP_TEXTURE_TRANSFER_MODES:
263 if (screen->gen >= 6)
264 return PIPE_TEXTURE_TRANSFER_BLIT;
265 return 0;
266
267 case PIPE_CAP_PCI_GROUP:
268 case PIPE_CAP_PCI_BUS:
269 case PIPE_CAP_PCI_DEVICE:
270 case PIPE_CAP_PCI_FUNCTION:
271 return 0;
272
273 case PIPE_CAP_SUPPORTED_PRIM_MODES:
274 case PIPE_CAP_SUPPORTED_PRIM_MODES_WITH_RESTART:
275 return screen->primtypes_mask;
276
277 case PIPE_CAP_FRAGMENT_SHADER_TEXTURE_LOD:
278 case PIPE_CAP_FRAGMENT_SHADER_DERIVATIVES:
279 case PIPE_CAP_PRIMITIVE_RESTART:
280 case PIPE_CAP_PRIMITIVE_RESTART_FIXED_INDEX:
281 case PIPE_CAP_VS_INSTANCEID:
282 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
283 case PIPE_CAP_INDEP_BLEND_ENABLE:
284 case PIPE_CAP_INDEP_BLEND_FUNC:
285 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
286 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
287 case PIPE_CAP_CONDITIONAL_RENDER:
288 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
289 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
290 case PIPE_CAP_CLIP_HALFZ:
291 return is_a3xx(screen) || is_a4xx(screen) || is_a5xx(screen) ||
292 is_a6xx(screen);
293
294 case PIPE_CAP_FAKE_SW_MSAA:
295 return !fd_screen_get_param(pscreen, PIPE_CAP_TEXTURE_MULTISAMPLE);
296
297 case PIPE_CAP_TEXTURE_MULTISAMPLE:
298 case PIPE_CAP_IMAGE_STORE_FORMATTED:
299 case PIPE_CAP_IMAGE_LOAD_FORMATTED:
300 return is_a5xx(screen) || is_a6xx(screen);
301
302 case PIPE_CAP_SURFACE_SAMPLE_COUNT:
303 return is_a6xx(screen);
304
305 case PIPE_CAP_DEPTH_CLIP_DISABLE:
306 return is_a3xx(screen) || is_a4xx(screen) || is_a6xx(screen);
307
308 case PIPE_CAP_POST_DEPTH_COVERAGE:
309 case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE:
310 case PIPE_CAP_DEMOTE_TO_HELPER_INVOCATION:
311 return is_a6xx(screen);
312
313 case PIPE_CAP_SAMPLER_REDUCTION_MINMAX:
314 case PIPE_CAP_SAMPLER_REDUCTION_MINMAX_ARB:
315 return is_a6xx(screen) && screen->info->a6xx.has_sampler_minmax;
316
317 case PIPE_CAP_PROGRAMMABLE_SAMPLE_LOCATIONS:
318 return is_a6xx(screen) && screen->info->a6xx.has_sample_locations;
319
320 case PIPE_CAP_POLYGON_OFFSET_CLAMP:
321 return is_a4xx(screen) || is_a5xx(screen) || is_a6xx(screen);
322
323 case PIPE_CAP_PREFER_IMM_ARRAYS_AS_CONSTBUF:
324 return 0;
325
326 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
327 if (is_a3xx(screen))
328 return 16;
329 if (is_a4xx(screen) || is_a5xx(screen) || is_a6xx(screen))
330 return 64;
331 return 0;
332 case PIPE_CAP_MAX_TEXEL_BUFFER_ELEMENTS_UINT:
333 /* We could possibly emulate more by pretending 2d/rect textures and
334 * splitting high bits of index into 2nd dimension..
335 */
336 if (is_a3xx(screen))
337 return A3XX_MAX_TEXEL_BUFFER_ELEMENTS_UINT;
338
339 /* Note that the Vulkan blob on a540 and 640 report a
340 * maxTexelBufferElements of just 65536 (the GLES3.2 and Vulkan
341 * minimum).
342 */
343 if (is_a4xx(screen) || is_a5xx(screen) || is_a6xx(screen))
344 return A4XX_MAX_TEXEL_BUFFER_ELEMENTS_UINT;
345
346 return 0;
347
348 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
349 return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_FREEDRENO;
350
351 case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
352 case PIPE_CAP_CUBE_MAP_ARRAY:
353 case PIPE_CAP_SAMPLER_VIEW_TARGET:
354 case PIPE_CAP_TEXTURE_QUERY_LOD:
355 return is_a4xx(screen) || is_a5xx(screen) || is_a6xx(screen);
356
357 case PIPE_CAP_START_INSTANCE:
358 /* Note that a5xx can do this, it just can't (at least with
359 * current firmware) do draw_indirect with base_instance.
360 * Since draw_indirect is needed sooner (gles31 and gl40 vs
361 * gl42), hide base_instance on a5xx. :-/
362 */
363 return is_a4xx(screen) || is_a6xx(screen);
364
365 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
366 return 64;
367
368 case PIPE_CAP_INT64:
369 case PIPE_CAP_DOUBLES:
370 return is_ir3(screen);
371
372 case PIPE_CAP_GLSL_FEATURE_LEVEL:
373 case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
374 if (is_a6xx(screen))
375 return 460;
376 else if (is_ir3(screen))
377 return 140;
378 else
379 return 120;
380
381 case PIPE_CAP_ESSL_FEATURE_LEVEL:
382 if (is_a4xx(screen) || is_a5xx(screen) || is_a6xx(screen))
383 return 320;
384 if (is_ir3(screen))
385 return 300;
386 return 120;
387
388 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
389 if (is_a6xx(screen))
390 return 64;
391 if (is_a5xx(screen))
392 return 4;
393 if (is_a4xx(screen))
394 return 4;
395 return 0;
396
397 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
398 if (is_a4xx(screen) || is_a5xx(screen) || is_a6xx(screen))
399 return 4;
400 return 0;
401
402 /* TODO if we need this, do it in nir/ir3 backend to avoid breaking
403 * precompile: */
404 case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
405 return 0;
406
407 case PIPE_CAP_FBFETCH:
408 if (fd_device_version(screen->dev) >= FD_VERSION_GMEM_BASE &&
409 is_a6xx(screen))
410 return screen->max_rts;
411 return 0;
412 case PIPE_CAP_SAMPLE_SHADING:
413 if (is_a6xx(screen))
414 return 1;
415 return 0;
416
417 case PIPE_CAP_CONTEXT_PRIORITY_MASK:
418 return screen->priority_mask;
419
420 case PIPE_CAP_DRAW_INDIRECT:
421 if (is_a4xx(screen) || is_a5xx(screen) || is_a6xx(screen))
422 return 1;
423 return 0;
424
425 case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
426 if (is_a4xx(screen) || is_a5xx(screen) || is_a6xx(screen))
427 return 1;
428 return 0;
429
430 case PIPE_CAP_LOAD_CONSTBUF:
431 /* name is confusing, but this turns on std430 packing */
432 if (is_ir3(screen))
433 return 1;
434 return 0;
435
436 case PIPE_CAP_NIR_IMAGES_AS_DEREF:
437 return 0;
438
439 case PIPE_CAP_VS_LAYER_VIEWPORT:
440 case PIPE_CAP_TES_LAYER_VIEWPORT:
441 return is_a6xx(screen);
442
443 case PIPE_CAP_MAX_VIEWPORTS:
444 if (is_a6xx(screen))
445 return 16;
446 return 1;
447
448 case PIPE_CAP_MAX_VARYINGS:
449 return is_a6xx(screen) ? 31 : 16;
450
451 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
452 /* We don't really have a limit on this, it all goes into the main
453 * memory buffer. Needs to be at least 120 / 4 (minimum requirement
454 * for GL_MAX_TESS_PATCH_COMPONENTS).
455 */
456 return 128;
457
458 case PIPE_CAP_MAX_TEXTURE_UPLOAD_MEMORY_BUDGET:
459 return 64 * 1024 * 1024;
460
461 case PIPE_CAP_SHAREABLE_SHADERS:
462 if (is_ir3(screen))
463 return 1;
464 return 0;
465
466 /* Geometry shaders.. */
467 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
468 return 256;
469 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
470 return 2048;
471 case PIPE_CAP_MAX_GS_INVOCATIONS:
472 return 32;
473
474 /* Only a2xx has the half-border clamp mode in HW, just have mesa/st lower
475 * it for later HW.
476 */
477 case PIPE_CAP_GL_CLAMP:
478 return is_a2xx(screen);
479
480 case PIPE_CAP_CLIP_PLANES:
481 /* Gens that support GS, have GS lowered into a quasi-VS which confuses
482 * the frontend clip-plane lowering. So we handle this in the backend
483 *
484 */
485 if (pscreen->get_shader_param(pscreen, PIPE_SHADER_GEOMETRY,
486 PIPE_SHADER_CAP_MAX_INSTRUCTIONS))
487 return 1;
488
489 /* On a3xx, there is HW support for GL user clip planes that
490 * occasionally has to fall back to shader key-based lowering to clip
491 * distances in the VS, and we don't support clip distances so that is
492 * always shader-based lowering in the FS.
493 *
494 * On a4xx, there is no HW support for clip planes, so they are
495 * always lowered to clip distances. We also lack SW support for the
496 * HW's clip distances in HW, so we do shader-based lowering in the FS
497 * in the driver backend.
498 *
499 * On a5xx-a6xx, we have the HW clip distances hooked up, so we just let
500 * mesa/st lower desktop GL's clip planes to clip distances in the last
501 * vertex shader stage.
502 *
503 * NOTE: but see comment above about geometry shaders
504 */
505 return !is_a5xx(screen);
506
507 /* Stream output. */
508 case PIPE_CAP_MAX_VERTEX_STREAMS:
509 if (is_a6xx(screen)) /* has SO + GS */
510 return PIPE_MAX_SO_BUFFERS;
511 return 0;
512 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
513 if (is_ir3(screen))
514 return PIPE_MAX_SO_BUFFERS;
515 return 0;
516 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
517 case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
518 case PIPE_CAP_FS_POSITION_IS_SYSVAL:
519 case PIPE_CAP_TGSI_TEXCOORD:
520 case PIPE_CAP_SHADER_ARRAY_COMPONENTS:
521 case PIPE_CAP_TEXTURE_QUERY_SAMPLES:
522 case PIPE_CAP_FS_FINE_DERIVATIVE:
523 if (is_ir3(screen))
524 return 1;
525 return 0;
526 case PIPE_CAP_SHADER_GROUP_VOTE:
527 return is_a6xx(screen);
528 case PIPE_CAP_FS_FACE_IS_INTEGER_SYSVAL:
529 return 1;
530 case PIPE_CAP_FS_POINT_IS_SYSVAL:
531 return is_a2xx(screen);
532 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
533 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
534 if (is_ir3(screen))
535 return 16 * 4; /* should only be shader out limit? */
536 return 0;
537
538 /* Texturing. */
539 case PIPE_CAP_MAX_TEXTURE_2D_SIZE:
540 if (is_a6xx(screen) || is_a5xx(screen) || is_a4xx(screen))
541 return 16384;
542 else
543 return 8192;
544 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
545 if (is_a6xx(screen) || is_a5xx(screen) || is_a4xx(screen))
546 return 15;
547 else
548 return 14;
549
550 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
551 if (is_a3xx(screen))
552 return 11;
553 return 12;
554
555 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
556 if (is_a6xx(screen))
557 return 2048;
558 return (is_a3xx(screen) || is_a4xx(screen) || is_a5xx(screen))
559 ? 256
560 : 0;
561
562 /* Render targets. */
563 case PIPE_CAP_MAX_RENDER_TARGETS:
564 return screen->max_rts;
565 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
566 return (is_a3xx(screen) || is_a6xx(screen)) ? 1 : 0;
567
568 /* Queries. */
569 case PIPE_CAP_OCCLUSION_QUERY:
570 return is_a3xx(screen) || is_a4xx(screen) || is_a5xx(screen) ||
571 is_a6xx(screen);
572 case PIPE_CAP_QUERY_TIMESTAMP:
573 case PIPE_CAP_QUERY_TIME_ELAPSED:
574 /* only a4xx, requires new enough kernel so we know max_freq: */
575 return (screen->max_freq > 0) &&
576 (is_a4xx(screen) || is_a5xx(screen) || is_a6xx(screen));
577 case PIPE_CAP_TIMER_RESOLUTION:
578 return ticks_to_ns(1);
579 case PIPE_CAP_QUERY_BUFFER_OBJECT:
580 case PIPE_CAP_QUERY_SO_OVERFLOW:
581 case PIPE_CAP_QUERY_PIPELINE_STATISTICS_SINGLE:
582 return is_a6xx(screen);
583
584 case PIPE_CAP_VENDOR_ID:
585 return 0x5143;
586 case PIPE_CAP_DEVICE_ID:
587 return 0xFFFFFFFF;
588 case PIPE_CAP_ACCELERATED:
589 return 1;
590
591 case PIPE_CAP_VIDEO_MEMORY:
592 return (int)(get_memory_size(screen) >> 20);
593
594 case PIPE_CAP_QUERY_MEMORY_INFO: /* Enables GL_ATI_meminfo */
595 return get_memory_size(screen) != 0;
596
597 case PIPE_CAP_UMA:
598 return 1;
599 case PIPE_CAP_MEMOBJ:
600 return fd_device_version(screen->dev) >= FD_VERSION_MEMORY_FD;
601 case PIPE_CAP_NATIVE_FENCE_FD:
602 return fd_device_version(screen->dev) >= FD_VERSION_FENCE_FD;
603 case PIPE_CAP_FENCE_SIGNAL:
604 return screen->has_syncobj;
605 case PIPE_CAP_CULL_DISTANCE:
606 return is_a6xx(screen);
607 case PIPE_CAP_SHADER_STENCIL_EXPORT:
608 return is_a6xx(screen);
609 case PIPE_CAP_TWO_SIDED_COLOR:
610 return 0;
611 case PIPE_CAP_THROTTLE:
612 return screen->driconf.enable_throttling;
613 default:
614 return u_pipe_screen_get_param_defaults(pscreen, param);
615 }
616 }
617
618 static float
fd_screen_get_paramf(struct pipe_screen * pscreen,enum pipe_capf param)619 fd_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
620 {
621 switch (param) {
622 case PIPE_CAPF_MIN_LINE_WIDTH:
623 case PIPE_CAPF_MIN_LINE_WIDTH_AA:
624 case PIPE_CAPF_MIN_POINT_SIZE:
625 case PIPE_CAPF_MIN_POINT_SIZE_AA:
626 return 1;
627 case PIPE_CAPF_POINT_SIZE_GRANULARITY:
628 case PIPE_CAPF_LINE_WIDTH_GRANULARITY:
629 return 0.1f;
630 case PIPE_CAPF_MAX_LINE_WIDTH:
631 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
632 return 127.0f;
633 case PIPE_CAPF_MAX_POINT_SIZE:
634 case PIPE_CAPF_MAX_POINT_SIZE_AA:
635 return 4092.0f;
636 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
637 return 16.0f;
638 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
639 return 15.0f;
640 case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
641 case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
642 case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
643 return 0.0f;
644 }
645 mesa_loge("unknown paramf %d", param);
646 return 0;
647 }
648
649 static int
fd_screen_get_shader_param(struct pipe_screen * pscreen,enum pipe_shader_type shader,enum pipe_shader_cap param)650 fd_screen_get_shader_param(struct pipe_screen *pscreen,
651 enum pipe_shader_type shader,
652 enum pipe_shader_cap param)
653 {
654 struct fd_screen *screen = fd_screen(pscreen);
655
656 switch (shader) {
657 case PIPE_SHADER_FRAGMENT:
658 case PIPE_SHADER_VERTEX:
659 break;
660 case PIPE_SHADER_TESS_CTRL:
661 case PIPE_SHADER_TESS_EVAL:
662 case PIPE_SHADER_GEOMETRY:
663 if (is_a6xx(screen))
664 break;
665 return 0;
666 case PIPE_SHADER_COMPUTE:
667 if (has_compute(screen))
668 break;
669 return 0;
670 case PIPE_SHADER_TASK:
671 case PIPE_SHADER_MESH:
672 return 0;
673 default:
674 mesa_loge("unknown shader type %d", shader);
675 return 0;
676 }
677
678 /* this is probably not totally correct.. but it's a start: */
679 switch (param) {
680 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
681 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
682 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
683 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
684 return 16384;
685 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
686 return 8; /* XXX */
687 case PIPE_SHADER_CAP_MAX_INPUTS:
688 if (shader == PIPE_SHADER_GEOMETRY && is_a6xx(screen))
689 return 16;
690 return is_a6xx(screen) ?
691 (screen->info->a6xx.vs_max_inputs_count) : 16;
692 case PIPE_SHADER_CAP_MAX_OUTPUTS:
693 return is_a6xx(screen) ? 32 : 16;
694 case PIPE_SHADER_CAP_MAX_TEMPS:
695 return 64; /* Max native temporaries. */
696 case PIPE_SHADER_CAP_MAX_CONST_BUFFER0_SIZE:
697 /* NOTE: seems to be limit for a3xx is actually 512 but
698 * split between VS and FS. Use lower limit of 256 to
699 * avoid getting into impossible situations:
700 */
701 return ((is_a3xx(screen) || is_a4xx(screen) || is_a5xx(screen) ||
702 is_a6xx(screen))
703 ? 4096
704 : 64) *
705 sizeof(float[4]);
706 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
707 return is_ir3(screen) ? 16 : 1;
708 case PIPE_SHADER_CAP_CONT_SUPPORTED:
709 return 1;
710 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
711 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
712 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
713 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
714 /* a2xx compiler doesn't handle indirect: */
715 return is_ir3(screen) ? 1 : 0;
716 case PIPE_SHADER_CAP_SUBROUTINES:
717 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
718 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
719 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
720 return 0;
721 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
722 return 1;
723 case PIPE_SHADER_CAP_INTEGERS:
724 return is_ir3(screen) ? 1 : 0;
725 case PIPE_SHADER_CAP_INT64_ATOMICS:
726 case PIPE_SHADER_CAP_FP16_DERIVATIVES:
727 case PIPE_SHADER_CAP_FP16_CONST_BUFFERS:
728 case PIPE_SHADER_CAP_GLSL_16BIT_CONSTS:
729 return 0;
730 case PIPE_SHADER_CAP_INT16:
731 case PIPE_SHADER_CAP_FP16:
732 return (
733 (is_a5xx(screen) || is_a6xx(screen)) &&
734 (shader == PIPE_SHADER_COMPUTE || shader == PIPE_SHADER_FRAGMENT) &&
735 !FD_DBG(NOFP16));
736 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
737 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
738 return 16;
739 case PIPE_SHADER_CAP_SUPPORTED_IRS:
740 return (1 << PIPE_SHADER_IR_NIR) |
741 COND(has_compute(screen) && (shader == PIPE_SHADER_COMPUTE),
742 (1 << PIPE_SHADER_IR_NIR_SERIALIZED)) |
743 /* tgsi_to_nir doesn't support all stages: */
744 COND((shader == PIPE_SHADER_VERTEX) ||
745 (shader == PIPE_SHADER_FRAGMENT) ||
746 (shader == PIPE_SHADER_COMPUTE),
747 (1 << PIPE_SHADER_IR_TGSI));
748 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
749 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
750 if (is_a6xx(screen)) {
751 if (param == PIPE_SHADER_CAP_MAX_SHADER_BUFFERS) {
752 return IR3_BINDLESS_SSBO_COUNT;
753 } else {
754 return IR3_BINDLESS_IMAGE_COUNT;
755 }
756 } else if (is_a4xx(screen) || is_a5xx(screen) || is_a6xx(screen)) {
757 /* a5xx (and a4xx for that matter) has one state-block
758 * for compute-shader SSBO's and another that is shared
759 * by VS/HS/DS/GS/FS.. so to simplify things for now
760 * just advertise SSBOs for FS and CS. We could possibly
761 * do what blob does, and partition the space for
762 * VS/HS/DS/GS/FS. The blob advertises:
763 *
764 * GL_MAX_VERTEX_SHADER_STORAGE_BLOCKS: 4
765 * GL_MAX_GEOMETRY_SHADER_STORAGE_BLOCKS: 4
766 * GL_MAX_TESS_CONTROL_SHADER_STORAGE_BLOCKS: 4
767 * GL_MAX_TESS_EVALUATION_SHADER_STORAGE_BLOCKS: 4
768 * GL_MAX_FRAGMENT_SHADER_STORAGE_BLOCKS: 4
769 * GL_MAX_COMPUTE_SHADER_STORAGE_BLOCKS: 24
770 * GL_MAX_COMBINED_SHADER_STORAGE_BLOCKS: 24
771 *
772 * I think that way we could avoid having to patch shaders
773 * for actual SSBO indexes by using a static partitioning.
774 *
775 * Note same state block is used for images and buffers,
776 * but images also need texture state for read access
777 * (isam/isam.3d)
778 */
779 switch (shader) {
780 case PIPE_SHADER_FRAGMENT:
781 case PIPE_SHADER_COMPUTE:
782 return 24;
783 default:
784 return 0;
785 }
786 }
787 return 0;
788 }
789 mesa_loge("unknown shader param %d", param);
790 return 0;
791 }
792
793 /* TODO depending on how much the limits differ for a3xx/a4xx, maybe move this
794 * into per-generation backend?
795 */
796 static int
fd_get_compute_param(struct pipe_screen * pscreen,enum pipe_shader_ir ir_type,enum pipe_compute_cap param,void * ret)797 fd_get_compute_param(struct pipe_screen *pscreen, enum pipe_shader_ir ir_type,
798 enum pipe_compute_cap param, void *ret)
799 {
800 struct fd_screen *screen = fd_screen(pscreen);
801 const char *const ir = "ir3";
802
803 if (!has_compute(screen))
804 return 0;
805
806 struct ir3_compiler *compiler = screen->compiler;
807
808 #define RET(x) \
809 do { \
810 if (ret) \
811 memcpy(ret, x, sizeof(x)); \
812 return sizeof(x); \
813 } while (0)
814
815 switch (param) {
816 case PIPE_COMPUTE_CAP_ADDRESS_BITS:
817 if (screen->gen >= 5)
818 RET((uint32_t[]){64});
819 RET((uint32_t[]){32});
820
821 case PIPE_COMPUTE_CAP_IR_TARGET:
822 if (ret)
823 sprintf(ret, "%s", ir);
824 return strlen(ir) * sizeof(char);
825
826 case PIPE_COMPUTE_CAP_GRID_DIMENSION:
827 RET((uint64_t[]){3});
828
829 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
830 RET(((uint64_t[]){65535, 65535, 65535}));
831
832 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
833 RET(((uint64_t[]){1024, 1024, 64}));
834
835 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
836 RET((uint64_t[]){1024});
837
838 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
839 RET((uint64_t[]){screen->ram_size});
840
841 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
842 RET((uint64_t[]){screen->info->cs_shared_mem_size});
843
844 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
845 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
846 RET((uint64_t[]){4096});
847
848 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
849 RET((uint64_t[]){screen->ram_size});
850
851 case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
852 RET((uint32_t[]){screen->max_freq / 1000000});
853
854 case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
855 RET((uint32_t[]){9999}); // TODO
856
857 case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
858 RET((uint32_t[]){1});
859
860 case PIPE_COMPUTE_CAP_SUBGROUP_SIZES:
861 RET((uint32_t[]){32}); // TODO
862
863 case PIPE_COMPUTE_CAP_MAX_SUBGROUPS:
864 RET((uint32_t[]){0}); // TODO
865
866 case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
867 RET((uint64_t[]){ compiler->max_variable_workgroup_size });
868 }
869
870 return 0;
871 }
872
873 static const void *
fd_get_compiler_options(struct pipe_screen * pscreen,enum pipe_shader_ir ir,enum pipe_shader_type shader)874 fd_get_compiler_options(struct pipe_screen *pscreen, enum pipe_shader_ir ir,
875 enum pipe_shader_type shader)
876 {
877 struct fd_screen *screen = fd_screen(pscreen);
878
879 if (is_ir3(screen))
880 return ir3_get_compiler_options(screen->compiler);
881
882 return ir2_get_compiler_options();
883 }
884
885 static struct disk_cache *
fd_get_disk_shader_cache(struct pipe_screen * pscreen)886 fd_get_disk_shader_cache(struct pipe_screen *pscreen)
887 {
888 struct fd_screen *screen = fd_screen(pscreen);
889
890 if (is_ir3(screen)) {
891 struct ir3_compiler *compiler = screen->compiler;
892 return compiler->disk_cache;
893 }
894
895 return NULL;
896 }
897
898 bool
fd_screen_bo_get_handle(struct pipe_screen * pscreen,struct fd_bo * bo,struct renderonly_scanout * scanout,unsigned stride,struct winsys_handle * whandle)899 fd_screen_bo_get_handle(struct pipe_screen *pscreen, struct fd_bo *bo,
900 struct renderonly_scanout *scanout, unsigned stride,
901 struct winsys_handle *whandle)
902 {
903 struct fd_screen *screen = fd_screen(pscreen);
904
905 whandle->stride = stride;
906
907 if (whandle->type == WINSYS_HANDLE_TYPE_SHARED) {
908 return fd_bo_get_name(bo, &whandle->handle) == 0;
909 } else if (whandle->type == WINSYS_HANDLE_TYPE_KMS) {
910 if (screen->ro) {
911 return renderonly_get_handle(scanout, whandle);
912 } else {
913 uint32_t handle = fd_bo_handle(bo);
914 if (!handle)
915 return false;
916 whandle->handle = handle;
917 return true;
918 }
919 } else if (whandle->type == WINSYS_HANDLE_TYPE_FD) {
920 int fd = fd_bo_dmabuf(bo);
921 if (fd < 0)
922 return false;
923 whandle->handle = fd;
924 return true;
925 } else {
926 return false;
927 }
928 }
929
930 static bool
is_format_supported(struct pipe_screen * pscreen,enum pipe_format format,uint64_t modifier)931 is_format_supported(struct pipe_screen *pscreen,
932 enum pipe_format format,
933 uint64_t modifier)
934 {
935 struct fd_screen *screen = fd_screen(pscreen);
936 if (screen->is_format_supported)
937 return screen->is_format_supported(pscreen, format, modifier);
938 return modifier == DRM_FORMAT_MOD_LINEAR;
939 }
940
941 static void
fd_screen_query_dmabuf_modifiers(struct pipe_screen * pscreen,enum pipe_format format,int max,uint64_t * modifiers,unsigned int * external_only,int * count)942 fd_screen_query_dmabuf_modifiers(struct pipe_screen *pscreen,
943 enum pipe_format format, int max,
944 uint64_t *modifiers,
945 unsigned int *external_only, int *count)
946 {
947 const uint64_t all_modifiers[] = {
948 DRM_FORMAT_MOD_LINEAR,
949 DRM_FORMAT_MOD_QCOM_COMPRESSED,
950 DRM_FORMAT_MOD_QCOM_TILED3,
951 };
952
953 int num = 0;
954
955 for (int i = 0; i < ARRAY_SIZE(all_modifiers); i++) {
956 if (!is_format_supported(pscreen, format, all_modifiers[i]))
957 continue;
958
959 if (num < max) {
960 if (modifiers)
961 modifiers[num] = all_modifiers[i];
962
963 if (external_only)
964 external_only[num] = false;
965 }
966
967 num++;
968 }
969
970 *count = num;
971 }
972
973 static bool
fd_screen_is_dmabuf_modifier_supported(struct pipe_screen * pscreen,uint64_t modifier,enum pipe_format format,bool * external_only)974 fd_screen_is_dmabuf_modifier_supported(struct pipe_screen *pscreen,
975 uint64_t modifier,
976 enum pipe_format format,
977 bool *external_only)
978 {
979 return is_format_supported(pscreen, format, modifier);
980 }
981
982 struct fd_bo *
fd_screen_bo_from_handle(struct pipe_screen * pscreen,struct winsys_handle * whandle)983 fd_screen_bo_from_handle(struct pipe_screen *pscreen,
984 struct winsys_handle *whandle)
985 {
986 struct fd_screen *screen = fd_screen(pscreen);
987 struct fd_bo *bo;
988
989 if (whandle->type == WINSYS_HANDLE_TYPE_SHARED) {
990 bo = fd_bo_from_name(screen->dev, whandle->handle);
991 } else if (whandle->type == WINSYS_HANDLE_TYPE_KMS) {
992 bo = fd_bo_from_handle(screen->dev, whandle->handle, 0);
993 } else if (whandle->type == WINSYS_HANDLE_TYPE_FD) {
994 bo = fd_bo_from_dmabuf(screen->dev, whandle->handle);
995 } else {
996 DBG("Attempt to import unsupported handle type %d", whandle->type);
997 return NULL;
998 }
999
1000 if (!bo) {
1001 DBG("ref name 0x%08x failed", whandle->handle);
1002 return NULL;
1003 }
1004
1005 return bo;
1006 }
1007
1008 static void
_fd_fence_ref(struct pipe_screen * pscreen,struct pipe_fence_handle ** ptr,struct pipe_fence_handle * pfence)1009 _fd_fence_ref(struct pipe_screen *pscreen, struct pipe_fence_handle **ptr,
1010 struct pipe_fence_handle *pfence)
1011 {
1012 fd_pipe_fence_ref(ptr, pfence);
1013 }
1014
1015 static void
fd_screen_get_device_uuid(struct pipe_screen * pscreen,char * uuid)1016 fd_screen_get_device_uuid(struct pipe_screen *pscreen, char *uuid)
1017 {
1018 struct fd_screen *screen = fd_screen(pscreen);
1019
1020 fd_get_device_uuid(uuid, screen->dev_id);
1021 }
1022
1023 static void
fd_screen_get_driver_uuid(struct pipe_screen * pscreen,char * uuid)1024 fd_screen_get_driver_uuid(struct pipe_screen *pscreen, char *uuid)
1025 {
1026 fd_get_driver_uuid(uuid);
1027 }
1028
1029 static int
fd_screen_get_fd(struct pipe_screen * pscreen)1030 fd_screen_get_fd(struct pipe_screen *pscreen)
1031 {
1032 struct fd_screen *screen = fd_screen(pscreen);
1033 return fd_device_fd(screen->dev);
1034 }
1035
1036 struct pipe_screen *
fd_screen_create(int fd,const struct pipe_screen_config * config,struct renderonly * ro)1037 fd_screen_create(int fd,
1038 const struct pipe_screen_config *config,
1039 struct renderonly *ro)
1040 {
1041 struct fd_device *dev = fd_device_new_dup(fd);
1042 if (!dev)
1043 return NULL;
1044
1045 struct fd_screen *screen = CALLOC_STRUCT(fd_screen);
1046 struct pipe_screen *pscreen;
1047 uint64_t val;
1048
1049 fd_mesa_debug = debug_get_option_fd_mesa_debug();
1050
1051 if (FD_DBG(NOBIN))
1052 fd_binning_enabled = false;
1053
1054 if (!screen)
1055 return NULL;
1056
1057 #ifdef HAVE_PERFETTO
1058 fd_perfetto_init();
1059 #endif
1060
1061 util_gpuvis_init();
1062
1063 pscreen = &screen->base;
1064
1065 screen->dev = dev;
1066 screen->ro = ro;
1067
1068 // maybe this should be in context?
1069 screen->pipe = fd_pipe_new(screen->dev, FD_PIPE_3D);
1070 if (!screen->pipe) {
1071 DBG("could not create 3d pipe");
1072 goto fail;
1073 }
1074
1075 if (fd_pipe_get_param(screen->pipe, FD_GMEM_SIZE, &val)) {
1076 DBG("could not get GMEM size");
1077 goto fail;
1078 }
1079 screen->gmemsize_bytes = debug_get_num_option("FD_MESA_GMEM", val);
1080
1081 if (fd_device_version(dev) >= FD_VERSION_GMEM_BASE) {
1082 fd_pipe_get_param(screen->pipe, FD_GMEM_BASE, &screen->gmem_base);
1083 }
1084
1085 if (fd_pipe_get_param(screen->pipe, FD_MAX_FREQ, &val)) {
1086 DBG("could not get gpu freq");
1087 /* this limits what performance related queries are
1088 * supported but is not fatal
1089 */
1090 screen->max_freq = 0;
1091 } else {
1092 screen->max_freq = val;
1093 }
1094
1095 if (fd_pipe_get_param(screen->pipe, FD_TIMESTAMP, &val) == 0)
1096 screen->has_timestamp = true;
1097
1098 screen->dev_id = fd_pipe_dev_id(screen->pipe);
1099
1100 if (fd_pipe_get_param(screen->pipe, FD_GPU_ID, &val)) {
1101 DBG("could not get gpu-id");
1102 goto fail;
1103 }
1104 screen->gpu_id = val;
1105
1106 if (fd_pipe_get_param(screen->pipe, FD_CHIP_ID, &val)) {
1107 DBG("could not get chip-id");
1108 /* older kernels may not have this property: */
1109 unsigned core = screen->gpu_id / 100;
1110 unsigned major = (screen->gpu_id % 100) / 10;
1111 unsigned minor = screen->gpu_id % 10;
1112 unsigned patch = 0; /* assume the worst */
1113 val = (patch & 0xff) | ((minor & 0xff) << 8) | ((major & 0xff) << 16) |
1114 ((core & 0xff) << 24);
1115 }
1116 screen->chip_id = val;
1117 screen->gen = fd_dev_gen(screen->dev_id);
1118
1119 if (fd_pipe_get_param(screen->pipe, FD_NR_PRIORITIES, &val)) {
1120 DBG("could not get # of rings");
1121 screen->priority_mask = 0;
1122 } else {
1123 /* # of rings equates to number of unique priority values: */
1124 screen->priority_mask = (1 << val) - 1;
1125
1126 /* Lowest numerical value (ie. zero) is highest priority: */
1127 screen->prio_high = 0;
1128
1129 /* Highest numerical value is lowest priority: */
1130 screen->prio_low = val - 1;
1131
1132 /* Pick midpoint for normal priority.. note that whatever the
1133 * range of possible priorities, since we divide by 2 the
1134 * result will either be an integer or an integer plus 0.5,
1135 * in which case it will round down to an integer, so int
1136 * division will give us an appropriate result in either
1137 * case:
1138 */
1139 screen->prio_norm = val / 2;
1140 }
1141
1142 if (fd_device_version(dev) >= FD_VERSION_ROBUSTNESS)
1143 screen->has_robustness = true;
1144
1145 screen->has_syncobj = fd_has_syncobj(screen->dev);
1146
1147 /* parse driconf configuration now for device specific overrides: */
1148 driParseConfigFiles(config->options, config->options_info, 0, "msm",
1149 NULL, fd_dev_name(screen->dev_id), NULL, 0, NULL, 0);
1150
1151 screen->driconf.conservative_lrz =
1152 !driQueryOptionb(config->options, "disable_conservative_lrz");
1153 screen->driconf.enable_throttling =
1154 !driQueryOptionb(config->options, "disable_throttling");
1155 screen->driconf.dual_color_blend_by_location =
1156 driQueryOptionb(config->options, "dual_color_blend_by_location");
1157
1158 struct sysinfo si;
1159 sysinfo(&si);
1160 screen->ram_size = si.totalram;
1161
1162 DBG("Pipe Info:");
1163 DBG(" GPU-id: %s", fd_dev_name(screen->dev_id));
1164 DBG(" Chip-id: 0x%016"PRIx64, screen->chip_id);
1165 DBG(" GMEM size: 0x%08x", screen->gmemsize_bytes);
1166
1167 const struct fd_dev_info info = fd_dev_info(screen->dev_id);
1168 if (!info.chip) {
1169 mesa_loge("unsupported GPU: a%03d", screen->gpu_id);
1170 goto fail;
1171 }
1172
1173 screen->dev_info = info;
1174 screen->info = &screen->dev_info;
1175
1176 /* explicitly checking for GPU revisions that are known to work. This
1177 * may be overly conservative for a3xx, where spoofing the gpu_id with
1178 * the blob driver seems to generate identical cmdstream dumps. But
1179 * on a2xx, there seem to be small differences between the GPU revs
1180 * so it is probably better to actually test first on real hardware
1181 * before enabling:
1182 *
1183 * If you have a different adreno version, feel free to add it to one
1184 * of the cases below and see what happens. And if it works, please
1185 * send a patch ;-)
1186 */
1187 switch (screen->gen) {
1188 case 2:
1189 fd2_screen_init(pscreen);
1190 break;
1191 case 3:
1192 fd3_screen_init(pscreen);
1193 break;
1194 case 4:
1195 fd4_screen_init(pscreen);
1196 break;
1197 case 5:
1198 fd5_screen_init(pscreen);
1199 break;
1200 case 6:
1201 case 7:
1202 fd6_screen_init(pscreen);
1203 break;
1204 default:
1205 mesa_loge("unsupported GPU generation: a%uxx", screen->gen);
1206 goto fail;
1207 }
1208
1209 /* fdN_screen_init() should set this: */
1210 assert(screen->primtypes);
1211 screen->primtypes_mask = 0;
1212 for (unsigned i = 0; i <= MESA_PRIM_COUNT; i++)
1213 if (screen->primtypes[i])
1214 screen->primtypes_mask |= (1 << i);
1215
1216 if (FD_DBG(PERFC)) {
1217 screen->perfcntr_groups =
1218 fd_perfcntrs(screen->dev_id, &screen->num_perfcntr_groups);
1219 }
1220
1221 /* NOTE: don't enable if we have too old of a kernel to support
1222 * growable cmdstream buffers, since memory requirement for cmdstream
1223 * buffers would be too much otherwise.
1224 */
1225 if (fd_device_version(dev) >= FD_VERSION_UNLIMITED_CMDS)
1226 screen->reorder = !FD_DBG(INORDER);
1227
1228 fd_bc_init(&screen->batch_cache);
1229
1230 list_inithead(&screen->context_list);
1231
1232 util_idalloc_mt_init_tc(&screen->buffer_ids);
1233
1234 (void)simple_mtx_init(&screen->lock, mtx_plain);
1235
1236 pscreen->destroy = fd_screen_destroy;
1237 pscreen->get_screen_fd = fd_screen_get_fd;
1238 pscreen->query_memory_info = fd_query_memory_info;
1239 pscreen->get_param = fd_screen_get_param;
1240 pscreen->get_paramf = fd_screen_get_paramf;
1241 pscreen->get_shader_param = fd_screen_get_shader_param;
1242 pscreen->get_compute_param = fd_get_compute_param;
1243 pscreen->get_compiler_options = fd_get_compiler_options;
1244 pscreen->get_disk_shader_cache = fd_get_disk_shader_cache;
1245
1246 fd_resource_screen_init(pscreen);
1247 fd_query_screen_init(pscreen);
1248 fd_gmem_screen_init(pscreen);
1249
1250 pscreen->get_name = fd_screen_get_name;
1251 pscreen->get_vendor = fd_screen_get_vendor;
1252 pscreen->get_device_vendor = fd_screen_get_device_vendor;
1253
1254 pscreen->get_sample_pixel_grid = fd_get_sample_pixel_grid;
1255
1256 pscreen->get_timestamp = fd_screen_get_timestamp;
1257
1258 pscreen->fence_reference = _fd_fence_ref;
1259 pscreen->fence_finish = fd_pipe_fence_finish;
1260 pscreen->fence_get_fd = fd_pipe_fence_get_fd;
1261
1262 pscreen->query_dmabuf_modifiers = fd_screen_query_dmabuf_modifiers;
1263 pscreen->is_dmabuf_modifier_supported =
1264 fd_screen_is_dmabuf_modifier_supported;
1265
1266 pscreen->get_device_uuid = fd_screen_get_device_uuid;
1267 pscreen->get_driver_uuid = fd_screen_get_driver_uuid;
1268
1269 slab_create_parent(&screen->transfer_pool, sizeof(struct fd_transfer), 16);
1270
1271 simple_mtx_init(&screen->aux_ctx_lock, mtx_plain);
1272
1273 return pscreen;
1274
1275 fail:
1276 fd_screen_destroy(pscreen);
1277 return NULL;
1278 }
1279
1280 struct fd_context *
fd_screen_aux_context_get(struct pipe_screen * pscreen)1281 fd_screen_aux_context_get(struct pipe_screen *pscreen)
1282 {
1283 struct fd_screen *screen = fd_screen(pscreen);
1284
1285 simple_mtx_lock(&screen->aux_ctx_lock);
1286
1287 if (!screen->aux_ctx) {
1288 screen->aux_ctx = pscreen->context_create(pscreen, NULL, 0);
1289 }
1290
1291 return fd_context(screen->aux_ctx);
1292 }
1293
1294 void
fd_screen_aux_context_put(struct pipe_screen * pscreen)1295 fd_screen_aux_context_put(struct pipe_screen *pscreen)
1296 {
1297 struct fd_screen *screen = fd_screen(pscreen);
1298
1299 screen->aux_ctx->flush(screen->aux_ctx, NULL, 0);
1300 simple_mtx_unlock(&screen->aux_ctx_lock);
1301 }
1302