xref: /aosp_15_r20/external/mesa3d/src/gallium/drivers/freedreno/freedreno_perfetto.h (revision 6104692788411f58d303aa86923a9ff6ecaded22)
1 /*
2  * Copyright © 2021 Google, Inc.
3  * SPDX-License-Identifier: MIT
4  */
5 
6 #ifndef FREEDRENO_PERFETTO_H_
7 #define FREEDRENO_PERFETTO_H_
8 
9 #ifdef __cplusplus
10 extern "C" {
11 #endif
12 
13 #ifdef HAVE_PERFETTO
14 
15 /**
16  * Render-stage id's
17  */
18 enum fd_stage_id {
19    SURFACE_STAGE_ID, /* Surface is a sort of meta-stage for render-target info */
20    BINNING_STAGE_ID,
21    GMEM_STAGE_ID,
22    BYPASS_STAGE_ID,
23    BLIT_STAGE_ID,
24    COMPUTE_STAGE_ID,
25    CLEAR_STAGE_ID,
26    TILE_LOAD_STAGE_ID,
27    TILE_STORE_STAGE_ID,
28    STATE_RESTORE_STAGE_ID,
29    VSC_OVERFLOW_STAGE_ID,
30    PROLOGUE_STAGE_ID,
31 
32    NUM_STAGES
33 };
34 
35 static const struct {
36    const char *name;
37    const char *desc;
38 } stages[] = {
39    [SURFACE_STAGE_ID] = {"Surface"},
40    [BINNING_STAGE_ID] = {"Binning", "Perform Visibility pass and determine target bins"},
41    [GMEM_STAGE_ID]    = {"Render", "Rendering to GMEM"},
42    [BYPASS_STAGE_ID]  = {"Render", "Rendering to system memory"},
43    [BLIT_STAGE_ID]    = {"Blit", "Performing a Blit operation"},
44    [COMPUTE_STAGE_ID] = {"Compute", "Compute job"},
45    [CLEAR_STAGE_ID]   = {"Clear", "Clear (sysmem) or per-tile clear (GMEM)"},
46    [TILE_LOAD_STAGE_ID]  = {"Tile Load", "Per tile load (system memory to GMEM)"},
47    [TILE_STORE_STAGE_ID] = {"Tile Store", "Per tile store (GMEM to system memory)"},
48    [STATE_RESTORE_STAGE_ID] = {"State Restore", "Setup at the beginning of new cmdstream buffer"},
49    [VSC_OVERFLOW_STAGE_ID] = {"VSC Overflow Test", ""},
50    [PROLOGUE_STAGE_ID] = {"Prologue", "Preemble cmdstream (executed once before first tile)"},
51 };
52 
53 /**
54  * Queue-id's
55  */
56 enum {
57    DEFAULT_HW_QUEUE_ID,
58 };
59 
60 static const struct {
61    const char *name;
62    const char *desc;
63 } queues[] = {
64    [DEFAULT_HW_QUEUE_ID] = {"GPU Queue 0", "Default Adreno Hardware Queue"},
65 };
66 
67 /**
68  * The u_trace tracepoints which are used to capture GPU timestamps and
69  * trigger perfetto events tend to come in begin/end pairs (ie. start
70  * and end of binning pass, etc), but perfetto wants one event for the
71  * whole pass.  So we need to buffer up some state at the "begin" trae
72  * callback, and then emit the perfetto event at the "end" event based
73  * on previously recorded timestamp/data.  This struct is where we can
74  * accumulate that state.
75  */
76 struct fd_perfetto_state {
77    uint64_t start_ts[NUM_STAGES];
78 
79    /*
80     * Surface state for the renderpass:
81     */
82    uint32_t submit_id;
83    enum pipe_format cbuf0_format : 16;
84    enum pipe_format zs_format : 16;
85    uint16_t width;
86    uint16_t height;
87    uint8_t mrts;
88    uint8_t samples;
89    uint16_t nbins;
90    uint16_t binw;
91    uint16_t binh;
92    // TODO # of draws and possibly estimated cost might be useful addition..
93 
94    /*
95     * Compute state for grids:
96     */
97    uint8_t indirect;
98    uint8_t work_dim;
99    uint16_t local_size_x;
100    uint16_t local_size_y;
101    uint16_t local_size_z;
102    uint32_t num_groups_x;
103    uint32_t num_groups_y;
104    uint32_t num_groups_z;
105    uint32_t shader_id;
106 };
107 
108 void fd_perfetto_init(void);
109 
110 struct fd_context;
111 void fd_perfetto_submit(struct fd_context *ctx);
112 
113 #endif
114 
115 #ifdef __cplusplus
116 }
117 #endif
118 
119 #endif /* FREEDRENO_PERFETTO_H_ */
120