1 /* 2 * Copyright © 2016 Rob Clark <[email protected]> 3 * SPDX-License-Identifier: MIT 4 * 5 * Authors: 6 * Rob Clark <[email protected]> 7 */ 8 9 #include "pipe/p_state.h" 10 #include "util/u_memory.h" 11 #include "util/u_string.h" 12 13 #include "fd5_context.h" 14 #include "fd5_format.h" 15 #include "fd5_zsa.h" 16 17 void * fd5_zsa_state_create(struct pipe_context * pctx,const struct pipe_depth_stencil_alpha_state * cso)18fd5_zsa_state_create(struct pipe_context *pctx, 19 const struct pipe_depth_stencil_alpha_state *cso) 20 { 21 struct fd5_zsa_stateobj *so; 22 23 so = CALLOC_STRUCT(fd5_zsa_stateobj); 24 if (!so) 25 return NULL; 26 27 so->base = *cso; 28 29 switch (cso->depth_func) { 30 case PIPE_FUNC_LESS: 31 case PIPE_FUNC_LEQUAL: 32 so->gras_lrz_cntl = A5XX_GRAS_LRZ_CNTL_ENABLE; 33 break; 34 35 case PIPE_FUNC_GREATER: 36 case PIPE_FUNC_GEQUAL: 37 so->gras_lrz_cntl = 38 A5XX_GRAS_LRZ_CNTL_ENABLE | A5XX_GRAS_LRZ_CNTL_GREATER; 39 break; 40 41 default: 42 /* LRZ not enabled */ 43 so->gras_lrz_cntl = 0; 44 break; 45 } 46 47 if (!(cso->stencil->enabled || cso->alpha_enabled || !cso->depth_writemask)) 48 so->lrz_write = true; 49 50 so->rb_depth_cntl |= 51 A5XX_RB_DEPTH_CNTL_ZFUNC(cso->depth_func); /* maps 1:1 */ 52 53 if (cso->depth_enabled) 54 so->rb_depth_cntl |= 55 A5XX_RB_DEPTH_CNTL_Z_TEST_ENABLE | A5XX_RB_DEPTH_CNTL_Z_READ_ENABLE; 56 57 if (cso->depth_writemask) 58 so->rb_depth_cntl |= A5XX_RB_DEPTH_CNTL_Z_WRITE_ENABLE; 59 60 if (cso->stencil[0].enabled) { 61 const struct pipe_stencil_state *s = &cso->stencil[0]; 62 63 so->rb_stencil_control |= 64 A5XX_RB_STENCIL_CONTROL_STENCIL_READ | 65 A5XX_RB_STENCIL_CONTROL_STENCIL_ENABLE | 66 A5XX_RB_STENCIL_CONTROL_FUNC(s->func) | /* maps 1:1 */ 67 A5XX_RB_STENCIL_CONTROL_FAIL(fd_stencil_op(s->fail_op)) | 68 A5XX_RB_STENCIL_CONTROL_ZPASS(fd_stencil_op(s->zpass_op)) | 69 A5XX_RB_STENCIL_CONTROL_ZFAIL(fd_stencil_op(s->zfail_op)); 70 so->rb_stencilrefmask |= 71 A5XX_RB_STENCILREFMASK_STENCILWRITEMASK(s->writemask) | 72 A5XX_RB_STENCILREFMASK_STENCILMASK(s->valuemask); 73 74 if (cso->stencil[1].enabled) { 75 const struct pipe_stencil_state *bs = &cso->stencil[1]; 76 77 so->rb_stencil_control |= 78 A5XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF | 79 A5XX_RB_STENCIL_CONTROL_FUNC_BF(bs->func) | /* maps 1:1 */ 80 A5XX_RB_STENCIL_CONTROL_FAIL_BF(fd_stencil_op(bs->fail_op)) | 81 A5XX_RB_STENCIL_CONTROL_ZPASS_BF(fd_stencil_op(bs->zpass_op)) | 82 A5XX_RB_STENCIL_CONTROL_ZFAIL_BF(fd_stencil_op(bs->zfail_op)); 83 so->rb_stencilrefmask_bf |= 84 A5XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(bs->writemask) | 85 A5XX_RB_STENCILREFMASK_BF_STENCILMASK(bs->valuemask); 86 } 87 } 88 89 if (cso->alpha_enabled) { 90 uint32_t ref = cso->alpha_ref_value * 255.0f; 91 so->rb_alpha_control = 92 A5XX_RB_ALPHA_CONTROL_ALPHA_TEST | 93 A5XX_RB_ALPHA_CONTROL_ALPHA_REF(ref) | 94 A5XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC(cso->alpha_func); 95 // so->rb_depth_control |= 96 // A5XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE; 97 } 98 99 return so; 100 } 101