1 /*
2 * Copyright © 2017 Rob Clark <[email protected]>
3 * SPDX-License-Identifier: MIT
4 *
5 * Authors:
6 * Rob Clark <[email protected]>
7 */
8
9 #include "freedreno_blitter.h"
10 #include "freedreno_resource.h"
11
12 #include "fd5_blitter.h"
13 #include "fd5_emit.h"
14 #include "fd5_format.h"
15
16 /* Make sure none of the requested dimensions extend beyond the size of the
17 * resource. Not entirely sure why this happens, but sometimes it does, and
18 * w/ 2d blt doesn't have wrap modes like a sampler, so force those cases
19 * back to u_blitter
20 */
21 static bool
ok_dims(const struct pipe_resource * r,const struct pipe_box * b,int lvl)22 ok_dims(const struct pipe_resource *r, const struct pipe_box *b, int lvl)
23 {
24 return (b->x >= 0) && (b->x + b->width <= u_minify(r->width0, lvl)) &&
25 (b->y >= 0) && (b->y + b->height <= u_minify(r->height0, lvl)) &&
26 (b->z >= 0) && (b->z + b->depth <= u_minify(r->depth0, lvl));
27 }
28
29 /* Not sure if format restrictions differ for src and dst, or if
30 * they only matter when src fmt != dst fmt.. but there appear to
31 * be *some* limitations so let's just start rejecting stuff that
32 * piglit complains about
33 */
34 static bool
ok_format(enum pipe_format fmt)35 ok_format(enum pipe_format fmt)
36 {
37 if (util_format_is_compressed(fmt))
38 return false;
39
40 switch (fmt) {
41 case PIPE_FORMAT_R10G10B10A2_SSCALED:
42 case PIPE_FORMAT_R10G10B10A2_SNORM:
43 case PIPE_FORMAT_B10G10R10A2_USCALED:
44 case PIPE_FORMAT_B10G10R10A2_SSCALED:
45 case PIPE_FORMAT_B10G10R10A2_SNORM:
46 case PIPE_FORMAT_R10G10B10A2_UNORM:
47 case PIPE_FORMAT_R10G10B10A2_USCALED:
48 case PIPE_FORMAT_B10G10R10A2_UNORM:
49 case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
50 case PIPE_FORMAT_B10G10R10A2_UINT:
51 case PIPE_FORMAT_R10G10B10A2_UINT:
52 return false;
53 default:
54 break;
55 }
56
57 if (fd5_pipe2color(fmt) == RB5_NONE)
58 return false;
59
60 return true;
61 }
62
63 static bool
can_do_blit(const struct pipe_blit_info * info)64 can_do_blit(const struct pipe_blit_info *info)
65 {
66 /* I think we can do scaling, but not in z dimension since that would
67 * require blending..
68 */
69 if (info->dst.box.depth != info->src.box.depth)
70 return false;
71
72 if (!ok_format(info->dst.format))
73 return false;
74
75 if (!ok_format(info->src.format))
76 return false;
77
78 /* hw ignores {SRC,DST}_INFO.COLOR_SWAP if {SRC,DST}_INFO.TILE_MODE
79 * is set (not linear). We can kind of get around that when tiling/
80 * untiling by setting both src and dst COLOR_SWAP=WZYX, but that
81 * means the formats must match:
82 */
83 if ((fd_resource(info->dst.resource)->layout.tile_mode ||
84 fd_resource(info->src.resource)->layout.tile_mode) &&
85 info->dst.format != info->src.format)
86 return false;
87
88 /* until we figure out a few more registers: */
89 if ((info->dst.box.width != info->src.box.width) ||
90 (info->dst.box.height != info->src.box.height))
91 return false;
92
93 /* src box can be inverted, which we don't support.. dst box cannot: */
94 if ((info->src.box.width < 0) || (info->src.box.height < 0))
95 return false;
96
97 if (!ok_dims(info->src.resource, &info->src.box, info->src.level))
98 return false;
99
100 if (!ok_dims(info->dst.resource, &info->dst.box, info->dst.level))
101 return false;
102
103 assert(info->dst.box.width >= 0);
104 assert(info->dst.box.height >= 0);
105 assert(info->dst.box.depth >= 0);
106
107 if ((info->dst.resource->nr_samples > 1) ||
108 (info->src.resource->nr_samples > 1))
109 return false;
110
111 if (info->scissor_enable)
112 return false;
113
114 if (info->window_rectangle_include)
115 return false;
116
117 if (info->render_condition_enable)
118 return false;
119
120 if (info->alpha_blend)
121 return false;
122
123 if (info->filter != PIPE_TEX_FILTER_NEAREST)
124 return false;
125
126 if (info->mask != util_format_get_mask(info->src.format))
127 return false;
128
129 if (info->mask != util_format_get_mask(info->dst.format))
130 return false;
131
132 return true;
133 }
134
135 static void
emit_setup(struct fd_ringbuffer * ring)136 emit_setup(struct fd_ringbuffer *ring)
137 {
138 OUT_PKT4(ring, REG_A5XX_RB_RENDER_CNTL, 1);
139 OUT_RING(ring, 0x00000008);
140
141 OUT_PKT4(ring, REG_A5XX_RB_2D_BLIT_CNTL, 1);
142 OUT_RING(ring, 0x86000000); /* RB_2D_BLIT_CNTL */
143
144 OUT_PKT4(ring, REG_A5XX_GRAS_2D_BLIT_CNTL, 1);
145 OUT_RING(ring, 0x86000000); /* 2D_BLIT_CNTL */
146
147 OUT_PKT4(ring, REG_A5XX_UNKNOWN_2184, 1);
148 OUT_RING(ring, 0x00000009); /* UNKNOWN_2184 */
149
150 OUT_PKT4(ring, REG_A5XX_RB_CNTL, 1);
151 OUT_RING(ring, A5XX_RB_CNTL_BYPASS);
152
153 OUT_PKT4(ring, REG_A5XX_RB_MODE_CNTL, 1);
154 OUT_RING(ring, 0x00000004); /* RB_MODE_CNTL */
155
156 OUT_PKT4(ring, REG_A5XX_SP_MODE_CNTL, 1);
157 OUT_RING(ring, 0x0000000c); /* SP_MODE_CNTL */
158
159 OUT_PKT4(ring, REG_A5XX_TPL1_MODE_CNTL, 1);
160 OUT_RING(ring, 0x00000344); /* TPL1_MODE_CNTL */
161
162 OUT_PKT4(ring, REG_A5XX_HLSQ_MODE_CNTL, 1);
163 OUT_RING(ring, 0x00000002); /* HLSQ_MODE_CNTL */
164
165 OUT_PKT4(ring, REG_A5XX_GRAS_CL_CNTL, 1);
166 OUT_RING(ring, 0x00000181); /* GRAS_CL_CNTL */
167 }
168
169 /* buffers need to be handled specially since x/width can exceed the bounds
170 * supported by hw.. if necessary decompose into (potentially) two 2D blits
171 */
172 static void
emit_blit_buffer(struct fd_ringbuffer * ring,const struct pipe_blit_info * info)173 emit_blit_buffer(struct fd_ringbuffer *ring, const struct pipe_blit_info *info)
174 {
175 const struct pipe_box *sbox = &info->src.box;
176 const struct pipe_box *dbox = &info->dst.box;
177 struct fd_resource *src, *dst;
178 unsigned sshift, dshift;
179
180 src = fd_resource(info->src.resource);
181 dst = fd_resource(info->dst.resource);
182
183 assert(src->layout.cpp == 1);
184 assert(dst->layout.cpp == 1);
185 assert(info->src.resource->format == info->dst.resource->format);
186 assert((sbox->y == 0) && (sbox->height == 1));
187 assert((dbox->y == 0) && (dbox->height == 1));
188 assert((sbox->z == 0) && (sbox->depth == 1));
189 assert((dbox->z == 0) && (dbox->depth == 1));
190 assert(sbox->width == dbox->width);
191 assert(info->src.level == 0);
192 assert(info->dst.level == 0);
193
194 /*
195 * Buffers can have dimensions bigger than max width, remap into
196 * multiple 1d blits to fit within max dimension
197 *
198 * Note that blob uses .ARRAY_PITCH=128 for blitting buffers, which
199 * seems to prevent overfetch related faults. Not quite sure what
200 * the deal is there.
201 *
202 * Low 6 bits of SRC/DST addresses need to be zero (ie. address
203 * aligned to 64) so we need to shift src/dst x1/x2 to make up the
204 * difference. On top of already splitting up the blit so width
205 * isn't > 16k.
206 *
207 * We perhaps could do a bit better, if src and dst are aligned but
208 * in the worst case this means we have to split the copy up into
209 * 16k (0x4000) minus 64 (0x40).
210 */
211
212 sshift = sbox->x & 0x3f;
213 dshift = dbox->x & 0x3f;
214
215 for (unsigned off = 0; off < sbox->width; off += (0x4000 - 0x40)) {
216 unsigned soff, doff, w, p;
217
218 soff = (sbox->x + off) & ~0x3f;
219 doff = (dbox->x + off) & ~0x3f;
220
221 w = MIN2(sbox->width - off, (0x4000 - 0x40));
222 p = align(w, 64);
223
224 assert((soff + w) <= fd_bo_size(src->bo));
225 assert((doff + w) <= fd_bo_size(dst->bo));
226
227 OUT_PKT7(ring, CP_SET_RENDER_MODE, 1);
228 OUT_RING(ring, CP_SET_RENDER_MODE_0_MODE(BLIT2D));
229
230 /*
231 * Emit source:
232 */
233 OUT_PKT4(ring, REG_A5XX_RB_2D_SRC_INFO, 9);
234 OUT_RING(ring, A5XX_RB_2D_SRC_INFO_COLOR_FORMAT(RB5_R8_UNORM) |
235 A5XX_RB_2D_SRC_INFO_TILE_MODE(TILE5_LINEAR) |
236 A5XX_RB_2D_SRC_INFO_COLOR_SWAP(WZYX));
237 OUT_RELOC(ring, src->bo, soff, 0, 0); /* RB_2D_SRC_LO/HI */
238 OUT_RING(ring, A5XX_RB_2D_SRC_SIZE_PITCH(p) |
239 A5XX_RB_2D_SRC_SIZE_ARRAY_PITCH(128));
240 OUT_RING(ring, 0x00000000);
241 OUT_RING(ring, 0x00000000);
242 OUT_RING(ring, 0x00000000);
243 OUT_RING(ring, 0x00000000);
244 OUT_RING(ring, 0x00000000);
245
246 OUT_PKT4(ring, REG_A5XX_GRAS_2D_SRC_INFO, 1);
247 OUT_RING(ring, A5XX_GRAS_2D_SRC_INFO_COLOR_FORMAT(RB5_R8_UNORM) |
248 A5XX_GRAS_2D_SRC_INFO_COLOR_SWAP(WZYX));
249
250 /*
251 * Emit destination:
252 */
253 OUT_PKT4(ring, REG_A5XX_RB_2D_DST_INFO, 9);
254 OUT_RING(ring, A5XX_RB_2D_DST_INFO_COLOR_FORMAT(RB5_R8_UNORM) |
255 A5XX_RB_2D_DST_INFO_TILE_MODE(TILE5_LINEAR) |
256 A5XX_RB_2D_DST_INFO_COLOR_SWAP(WZYX));
257 OUT_RELOC(ring, dst->bo, doff, 0, 0); /* RB_2D_DST_LO/HI */
258 OUT_RING(ring, A5XX_RB_2D_DST_SIZE_PITCH(p) |
259 A5XX_RB_2D_DST_SIZE_ARRAY_PITCH(128));
260 OUT_RING(ring, 0x00000000);
261 OUT_RING(ring, 0x00000000);
262 OUT_RING(ring, 0x00000000);
263 OUT_RING(ring, 0x00000000);
264 OUT_RING(ring, 0x00000000);
265
266 OUT_PKT4(ring, REG_A5XX_GRAS_2D_DST_INFO, 1);
267 OUT_RING(ring, A5XX_GRAS_2D_DST_INFO_COLOR_FORMAT(RB5_R8_UNORM) |
268 A5XX_GRAS_2D_DST_INFO_COLOR_SWAP(WZYX));
269
270 /*
271 * Blit command:
272 */
273 OUT_PKT7(ring, CP_BLIT, 5);
274 OUT_RING(ring, CP_BLIT_0_OP(BLIT_OP_COPY));
275 OUT_RING(ring, CP_BLIT_1_SRC_X1(sshift) | CP_BLIT_1_SRC_Y1(0));
276 OUT_RING(ring, CP_BLIT_2_SRC_X2(sshift + w - 1) | CP_BLIT_2_SRC_Y2(0));
277 OUT_RING(ring, CP_BLIT_3_DST_X1(dshift) | CP_BLIT_3_DST_Y1(0));
278 OUT_RING(ring, CP_BLIT_4_DST_X2(dshift + w - 1) | CP_BLIT_4_DST_Y2(0));
279
280 OUT_PKT7(ring, CP_SET_RENDER_MODE, 1);
281 OUT_RING(ring, CP_SET_RENDER_MODE_0_MODE(END2D));
282
283 OUT_WFI5(ring);
284 }
285 }
286
287 static void
emit_blit(struct fd_ringbuffer * ring,const struct pipe_blit_info * info)288 emit_blit(struct fd_ringbuffer *ring, const struct pipe_blit_info *info)
289 {
290 const struct pipe_box *sbox = &info->src.box;
291 const struct pipe_box *dbox = &info->dst.box;
292 struct fd_resource *src, *dst;
293 enum a5xx_color_fmt sfmt, dfmt;
294 enum a5xx_tile_mode stile, dtile;
295 enum a3xx_color_swap sswap, dswap;
296 unsigned spitch, dpitch;
297 unsigned sx1, sy1, sx2, sy2;
298 unsigned dx1, dy1, dx2, dy2;
299
300 src = fd_resource(info->src.resource);
301 dst = fd_resource(info->dst.resource);
302
303 sfmt = fd5_pipe2color(info->src.format);
304 dfmt = fd5_pipe2color(info->dst.format);
305
306 stile = fd_resource_tile_mode(info->src.resource, info->src.level);
307 dtile = fd_resource_tile_mode(info->dst.resource, info->dst.level);
308
309 sswap = fd5_pipe2swap(info->src.format);
310 dswap = fd5_pipe2swap(info->dst.format);
311
312 spitch = fd_resource_pitch(src, info->src.level);
313 dpitch = fd_resource_pitch(dst, info->dst.level);
314
315 /* if dtile, then dswap ignored by hw, and likewise if stile then sswap
316 * ignored by hw.. but in this case we have already rejected the blit
317 * if src and dst formats differ, so juse use WZYX for both src and
318 * dst swap mode (so we don't change component order)
319 */
320 if (stile || dtile) {
321 assert(info->src.format == info->dst.format);
322 sswap = dswap = WZYX;
323 }
324
325 sx1 = sbox->x;
326 sy1 = sbox->y;
327 sx2 = sbox->x + sbox->width - 1;
328 sy2 = sbox->y + sbox->height - 1;
329
330 dx1 = dbox->x;
331 dy1 = dbox->y;
332 dx2 = dbox->x + dbox->width - 1;
333 dy2 = dbox->y + dbox->height - 1;
334
335 uint32_t sarray_pitch = fd_resource_layer_stride(src, info->src.level);
336 uint32_t darray_pitch = fd_resource_layer_stride(dst, info->dst.level);
337
338 for (unsigned i = 0; i < info->dst.box.depth; i++) {
339 unsigned soff = fd_resource_offset(src, info->src.level, sbox->z + i);
340 unsigned doff = fd_resource_offset(dst, info->dst.level, dbox->z + i);
341
342 assert((soff + (sbox->height * spitch)) <= fd_bo_size(src->bo));
343 assert((doff + (dbox->height * dpitch)) <= fd_bo_size(dst->bo));
344
345 OUT_PKT7(ring, CP_SET_RENDER_MODE, 1);
346 OUT_RING(ring, CP_SET_RENDER_MODE_0_MODE(BLIT2D));
347
348 /*
349 * Emit source:
350 */
351 OUT_PKT4(ring, REG_A5XX_RB_2D_SRC_INFO, 9);
352 OUT_RING(ring, A5XX_RB_2D_SRC_INFO_COLOR_FORMAT(sfmt) |
353 A5XX_RB_2D_SRC_INFO_TILE_MODE(stile) |
354 A5XX_RB_2D_SRC_INFO_COLOR_SWAP(sswap));
355 OUT_RELOC(ring, src->bo, soff, 0, 0); /* RB_2D_SRC_LO/HI */
356 OUT_RING(ring, A5XX_RB_2D_SRC_SIZE_PITCH(spitch) |
357 A5XX_RB_2D_SRC_SIZE_ARRAY_PITCH(sarray_pitch));
358 OUT_RING(ring, 0x00000000);
359 OUT_RING(ring, 0x00000000);
360 OUT_RING(ring, 0x00000000);
361 OUT_RING(ring, 0x00000000);
362 OUT_RING(ring, 0x00000000);
363
364 OUT_PKT4(ring, REG_A5XX_GRAS_2D_SRC_INFO, 1);
365 OUT_RING(ring, A5XX_GRAS_2D_SRC_INFO_COLOR_FORMAT(sfmt) |
366 A5XX_GRAS_2D_SRC_INFO_TILE_MODE(stile) |
367 A5XX_GRAS_2D_SRC_INFO_COLOR_SWAP(sswap));
368
369 /*
370 * Emit destination:
371 */
372 OUT_PKT4(ring, REG_A5XX_RB_2D_DST_INFO, 9);
373 OUT_RING(ring, A5XX_RB_2D_DST_INFO_COLOR_FORMAT(dfmt) |
374 A5XX_RB_2D_DST_INFO_TILE_MODE(dtile) |
375 A5XX_RB_2D_DST_INFO_COLOR_SWAP(dswap));
376 OUT_RELOC(ring, dst->bo, doff, 0, 0); /* RB_2D_DST_LO/HI */
377 OUT_RING(ring, A5XX_RB_2D_DST_SIZE_PITCH(dpitch) |
378 A5XX_RB_2D_DST_SIZE_ARRAY_PITCH(darray_pitch));
379 OUT_RING(ring, 0x00000000);
380 OUT_RING(ring, 0x00000000);
381 OUT_RING(ring, 0x00000000);
382 OUT_RING(ring, 0x00000000);
383 OUT_RING(ring, 0x00000000);
384
385 OUT_PKT4(ring, REG_A5XX_GRAS_2D_DST_INFO, 1);
386 OUT_RING(ring, A5XX_GRAS_2D_DST_INFO_COLOR_FORMAT(dfmt) |
387 A5XX_GRAS_2D_DST_INFO_TILE_MODE(dtile) |
388 A5XX_GRAS_2D_DST_INFO_COLOR_SWAP(dswap));
389
390 /*
391 * Blit command:
392 */
393 OUT_PKT7(ring, CP_BLIT, 5);
394 OUT_RING(ring, CP_BLIT_0_OP(BLIT_OP_COPY));
395 OUT_RING(ring, CP_BLIT_1_SRC_X1(sx1) | CP_BLIT_1_SRC_Y1(sy1));
396 OUT_RING(ring, CP_BLIT_2_SRC_X2(sx2) | CP_BLIT_2_SRC_Y2(sy2));
397 OUT_RING(ring, CP_BLIT_3_DST_X1(dx1) | CP_BLIT_3_DST_Y1(dy1));
398 OUT_RING(ring, CP_BLIT_4_DST_X2(dx2) | CP_BLIT_4_DST_Y2(dy2));
399
400 OUT_PKT7(ring, CP_SET_RENDER_MODE, 1);
401 OUT_RING(ring, CP_SET_RENDER_MODE_0_MODE(END2D));
402 }
403 }
404
405 bool
fd5_blitter_blit(struct fd_context * ctx,const struct pipe_blit_info * info)406 fd5_blitter_blit(struct fd_context *ctx,
407 const struct pipe_blit_info *info) assert_dt
408 {
409 struct fd_batch *batch;
410
411 if (!can_do_blit(info)) {
412 return false;
413 }
414
415 struct fd_resource *src = fd_resource(info->src.resource);
416 struct fd_resource *dst = fd_resource(info->dst.resource);
417
418 batch = fd_bc_alloc_batch(ctx, true);
419
420 fd_screen_lock(ctx->screen);
421
422 fd_batch_resource_read(batch, src);
423 fd_batch_resource_write(batch, dst);
424
425 fd_screen_unlock(ctx->screen);
426
427 DBG_BLIT(info, batch);
428
429 fd_batch_update_queries(batch);
430
431 emit_setup(batch->draw);
432
433 if ((info->src.resource->target == PIPE_BUFFER) &&
434 (info->dst.resource->target == PIPE_BUFFER)) {
435 assert(fd_resource(info->src.resource)->layout.tile_mode == TILE5_LINEAR);
436 assert(fd_resource(info->dst.resource)->layout.tile_mode == TILE5_LINEAR);
437 emit_blit_buffer(batch->draw, info);
438 } else {
439 /* I don't *think* we need to handle blits between buffer <-> !buffer */
440 assert(info->src.resource->target != PIPE_BUFFER);
441 assert(info->dst.resource->target != PIPE_BUFFER);
442 emit_blit(batch->draw, info);
443 }
444
445 fd_batch_needs_flush(batch);
446
447 fd_batch_flush(batch);
448 fd_batch_reference(&batch, NULL);
449
450 /* Acc query state will have been dirtied by our fd_batch_update_queries, so
451 * the ctx->batch may need to turn its queries back on.
452 */
453 fd_context_dirty(ctx, FD_DIRTY_QUERY);
454
455 return true;
456 }
457
458 unsigned
fd5_tile_mode(const struct pipe_resource * tmpl)459 fd5_tile_mode(const struct pipe_resource *tmpl)
460 {
461 /* basically just has to be a format we can blit, so uploads/downloads
462 * via linear staging buffer works:
463 */
464 if (ok_format(tmpl->format))
465 return TILE5_3;
466
467 return TILE5_LINEAR;
468 }
469