1 /*
2 * Copyright © 2014 Rob Clark <[email protected]>
3 * SPDX-License-Identifier: MIT
4 *
5 * Authors:
6 * Rob Clark <[email protected]>
7 */
8
9 #ifndef FD4_DRAW_H_
10 #define FD4_DRAW_H_
11
12 #include "pipe/p_context.h"
13
14 #include "freedreno_draw.h"
15
16 void fd4_draw_init(struct pipe_context *pctx);
17
18 /* draw packet changed on a4xx, so cannot reuse one from a2xx/a3xx.. */
19
20 static inline uint32_t
DRAW4(enum pc_di_primtype prim_type,enum pc_di_src_sel source_select,enum a4xx_index_size index_size,enum pc_di_vis_cull_mode vis_cull_mode)21 DRAW4(enum pc_di_primtype prim_type, enum pc_di_src_sel source_select,
22 enum a4xx_index_size index_size, enum pc_di_vis_cull_mode vis_cull_mode)
23 {
24 return CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(prim_type) |
25 CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(source_select) |
26 CP_DRAW_INDX_OFFSET_0_INDEX_SIZE(index_size) |
27 CP_DRAW_INDX_OFFSET_0_VIS_CULL(vis_cull_mode);
28 }
29
30 static inline void
fd4_draw(struct fd_batch * batch,struct fd_ringbuffer * ring,enum pc_di_primtype primtype,enum pc_di_vis_cull_mode vismode,enum pc_di_src_sel src_sel,uint32_t count,uint32_t instances,enum a4xx_index_size idx_type,uint32_t max_indices,uint32_t idx_offset,struct pipe_resource * idx_buffer)31 fd4_draw(struct fd_batch *batch, struct fd_ringbuffer *ring,
32 enum pc_di_primtype primtype, enum pc_di_vis_cull_mode vismode,
33 enum pc_di_src_sel src_sel, uint32_t count, uint32_t instances,
34 enum a4xx_index_size idx_type, uint32_t max_indices,
35 uint32_t idx_offset, struct pipe_resource *idx_buffer)
36 {
37 /* for debug after a lock up, write a unique counter value
38 * to scratch7 for each draw, to make it easier to match up
39 * register dumps to cmdstream. The combination of IB
40 * (scratch6) and DRAW is enough to "triangulate" the
41 * particular draw that caused lockup.
42 */
43 emit_marker(ring, 7);
44
45 OUT_PKT3(ring, CP_DRAW_INDX_OFFSET, idx_buffer ? 6 : 3);
46 if (vismode == USE_VISIBILITY) {
47 /* leave vis mode blank for now, it will be patched up when
48 * we know if we are binning or not
49 */
50 OUT_RINGP(ring, DRAW4(primtype, src_sel, idx_type, 0),
51 &batch->draw_patches);
52 } else {
53 OUT_RING(ring, DRAW4(primtype, src_sel, idx_type, vismode));
54 }
55 OUT_RING(ring, instances); /* NumInstances */
56 OUT_RING(ring, count); /* NumIndices */
57 if (idx_buffer) {
58 OUT_RING(ring, 0x0); /* XXX */
59 OUT_RELOC(ring, fd_resource(idx_buffer)->bo, idx_offset, 0, 0);
60 OUT_RING(ring, max_indices);
61 }
62
63 emit_marker(ring, 7);
64
65 fd_reset_wfi(batch);
66 }
67
68 static inline void
fd4_draw_emit(struct fd_batch * batch,struct fd_ringbuffer * ring,enum pc_di_primtype primtype,enum pc_di_vis_cull_mode vismode,const struct pipe_draw_info * info,const struct pipe_draw_indirect_info * indirect,const struct pipe_draw_start_count_bias * draw,unsigned index_offset)69 fd4_draw_emit(struct fd_batch *batch, struct fd_ringbuffer *ring,
70 enum pc_di_primtype primtype, enum pc_di_vis_cull_mode vismode,
71 const struct pipe_draw_info *info,
72 const struct pipe_draw_indirect_info *indirect,
73 const struct pipe_draw_start_count_bias *draw, unsigned index_offset)
74 {
75 struct pipe_resource *idx_buffer = NULL;
76 enum a4xx_index_size idx_type;
77 enum pc_di_src_sel src_sel;
78 uint32_t idx_size, idx_offset;
79
80 if (indirect && indirect->buffer) {
81 struct fd_resource *ind = fd_resource(indirect->buffer);
82
83 emit_marker(ring, 7);
84
85 if (info->index_size) {
86 struct pipe_resource *idx = info->index.resource;
87
88 OUT_PKT3(ring, CP_DRAW_INDX_INDIRECT, 4);
89 OUT_RINGP(ring,
90 DRAW4(primtype, DI_SRC_SEL_DMA,
91 fd4_size2indextype(info->index_size), 0),
92 &batch->draw_patches);
93 OUT_RELOC(ring, fd_resource(idx)->bo, index_offset, 0, 0);
94 OUT_RING(ring, A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE(idx->width0 -
95 index_offset));
96 OUT_RELOC(ring, ind->bo, indirect->offset, 0, 0);
97 } else {
98 OUT_PKT3(ring, CP_DRAW_INDIRECT, 2);
99 OUT_RINGP(ring, DRAW4(primtype, DI_SRC_SEL_AUTO_INDEX, 0, 0),
100 &batch->draw_patches);
101 OUT_RELOC(ring, ind->bo, indirect->offset, 0, 0);
102 }
103
104 emit_marker(ring, 7);
105 fd_reset_wfi(batch);
106
107 return;
108 }
109
110 if (info->index_size) {
111 assert(!info->has_user_indices);
112
113 idx_buffer = info->index.resource;
114 idx_type = fd4_size2indextype(info->index_size);
115 idx_size = info->index_size * draw->count;
116 idx_offset = index_offset + draw->start * info->index_size;
117 src_sel = DI_SRC_SEL_DMA;
118 } else {
119 idx_buffer = NULL;
120 idx_type = INDEX4_SIZE_32_BIT;
121 idx_size = 0;
122 idx_offset = 0;
123 src_sel = DI_SRC_SEL_AUTO_INDEX;
124 }
125
126 fd4_draw(batch, ring, primtype, vismode, src_sel, draw->count,
127 info->instance_count, idx_type, idx_size, idx_offset, idx_buffer);
128 }
129
130 #endif /* FD4_DRAW_H_ */
131