1 /*
2 * Copyright © 2012-2013 Rob Clark <[email protected]>
3 * SPDX-License-Identifier: MIT
4 *
5 * Authors:
6 * Rob Clark <[email protected]>
7 */
8
9 #include "pipe/p_state.h"
10 #include "util/u_inlines.h"
11 #include "util/u_memory.h"
12 #include "util/u_string.h"
13
14 #include "fd2_texture.h"
15 #include "fd2_util.h"
16
17 static enum sq_tex_clamp
tex_clamp(unsigned wrap)18 tex_clamp(unsigned wrap)
19 {
20 switch (wrap) {
21 case PIPE_TEX_WRAP_REPEAT:
22 return SQ_TEX_WRAP;
23 case PIPE_TEX_WRAP_CLAMP:
24 return SQ_TEX_CLAMP_HALF_BORDER;
25 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
26 return SQ_TEX_CLAMP_LAST_TEXEL;
27 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
28 return SQ_TEX_CLAMP_BORDER;
29 case PIPE_TEX_WRAP_MIRROR_REPEAT:
30 return SQ_TEX_MIRROR;
31 case PIPE_TEX_WRAP_MIRROR_CLAMP:
32 return SQ_TEX_MIRROR_ONCE_HALF_BORDER;
33 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
34 return SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
35 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
36 return SQ_TEX_MIRROR_ONCE_BORDER;
37 default:
38 DBG("invalid wrap: %u", wrap);
39 return 0;
40 }
41 }
42
43 static enum sq_tex_filter
tex_filter(unsigned filter)44 tex_filter(unsigned filter)
45 {
46 switch (filter) {
47 case PIPE_TEX_FILTER_NEAREST:
48 return SQ_TEX_FILTER_POINT;
49 case PIPE_TEX_FILTER_LINEAR:
50 return SQ_TEX_FILTER_BILINEAR;
51 default:
52 DBG("invalid filter: %u", filter);
53 return 0;
54 }
55 }
56
57 static enum sq_tex_filter
mip_filter(unsigned filter)58 mip_filter(unsigned filter)
59 {
60 switch (filter) {
61 case PIPE_TEX_MIPFILTER_NONE:
62 return SQ_TEX_FILTER_BASEMAP;
63 case PIPE_TEX_MIPFILTER_NEAREST:
64 return SQ_TEX_FILTER_POINT;
65 case PIPE_TEX_MIPFILTER_LINEAR:
66 return SQ_TEX_FILTER_BILINEAR;
67 default:
68 DBG("invalid filter: %u", filter);
69 return 0;
70 }
71 }
72
73 static void *
fd2_sampler_state_create(struct pipe_context * pctx,const struct pipe_sampler_state * cso)74 fd2_sampler_state_create(struct pipe_context *pctx,
75 const struct pipe_sampler_state *cso)
76 {
77 struct fd2_sampler_stateobj *so = CALLOC_STRUCT(fd2_sampler_stateobj);
78
79 if (!so)
80 return NULL;
81
82 so->base = *cso;
83
84 /* TODO
85 * cso->max_anisotropy
86 * cso->unnormalized_coords (dealt with by shader for rect textures?)
87 */
88
89 /* SQ_TEX0_PITCH() must be OR'd in later when we know the bound texture: */
90 so->tex0 = A2XX_SQ_TEX_0_CLAMP_X(tex_clamp(cso->wrap_s)) |
91 A2XX_SQ_TEX_0_CLAMP_Y(tex_clamp(cso->wrap_t)) |
92 A2XX_SQ_TEX_0_CLAMP_Z(tex_clamp(cso->wrap_r));
93
94 so->tex3 = A2XX_SQ_TEX_3_XY_MAG_FILTER(tex_filter(cso->mag_img_filter)) |
95 A2XX_SQ_TEX_3_XY_MIN_FILTER(tex_filter(cso->min_img_filter)) |
96 A2XX_SQ_TEX_3_MIP_FILTER(mip_filter(cso->min_mip_filter));
97
98 so->tex4 = 0;
99 if (cso->min_mip_filter != PIPE_TEX_MIPFILTER_NONE)
100 so->tex4 = A2XX_SQ_TEX_4_LOD_BIAS(cso->lod_bias);
101
102 return so;
103 }
104
105 static void
fd2_sampler_states_bind(struct pipe_context * pctx,enum pipe_shader_type shader,unsigned start,unsigned nr,void ** hwcso)106 fd2_sampler_states_bind(struct pipe_context *pctx, enum pipe_shader_type shader,
107 unsigned start, unsigned nr, void **hwcso) in_dt
108 {
109 if (!hwcso)
110 nr = 0;
111
112 if (shader == PIPE_SHADER_FRAGMENT) {
113 struct fd_context *ctx = fd_context(pctx);
114
115 /* on a2xx, since there is a flat address space for textures/samplers,
116 * a change in # of fragment textures/samplers will trigger patching and
117 * re-emitting the vertex shader:
118 */
119 if (nr != ctx->tex[PIPE_SHADER_FRAGMENT].num_samplers)
120 ctx->dirty |= FD_DIRTY_TEXSTATE;
121 }
122
123 fd_sampler_states_bind(pctx, shader, start, nr, hwcso);
124 }
125
126 static enum sq_tex_dimension
tex_dimension(unsigned target)127 tex_dimension(unsigned target)
128 {
129 switch (target) {
130 default:
131 unreachable("Unsupported target");
132 case PIPE_TEXTURE_1D:
133 assert(0); /* TODO */
134 return SQ_TEX_DIMENSION_1D;
135 case PIPE_TEXTURE_RECT:
136 case PIPE_TEXTURE_2D:
137 return SQ_TEX_DIMENSION_2D;
138 case PIPE_TEXTURE_3D:
139 assert(0); /* TODO */
140 return SQ_TEX_DIMENSION_3D;
141 case PIPE_TEXTURE_CUBE:
142 return SQ_TEX_DIMENSION_CUBE;
143 }
144 }
145
146 static struct pipe_sampler_view *
fd2_sampler_view_create(struct pipe_context * pctx,struct pipe_resource * prsc,const struct pipe_sampler_view * cso)147 fd2_sampler_view_create(struct pipe_context *pctx, struct pipe_resource *prsc,
148 const struct pipe_sampler_view *cso)
149 {
150 struct fd2_pipe_sampler_view *so = CALLOC_STRUCT(fd2_pipe_sampler_view);
151 struct fd_resource *rsc = fd_resource(prsc);
152 struct surface_format fmt = fd2_pipe2surface(cso->format);
153
154 if (!so)
155 return NULL;
156
157 so->base = *cso;
158 pipe_reference(NULL, &prsc->reference);
159 so->base.texture = prsc;
160 so->base.reference.count = 1;
161 so->base.context = pctx;
162
163 so->tex0 = A2XX_SQ_TEX_0_SIGN_X(fmt.sign) | A2XX_SQ_TEX_0_SIGN_Y(fmt.sign) |
164 A2XX_SQ_TEX_0_SIGN_Z(fmt.sign) | A2XX_SQ_TEX_0_SIGN_W(fmt.sign) |
165 A2XX_SQ_TEX_0_PITCH(fdl2_pitch_pixels(&rsc->layout, 0) *
166 util_format_get_blockwidth(prsc->format)) |
167 COND(rsc->layout.tile_mode, A2XX_SQ_TEX_0_TILED);
168 so->tex1 = A2XX_SQ_TEX_1_FORMAT(fmt.format) |
169 A2XX_SQ_TEX_1_CLAMP_POLICY(SQ_TEX_CLAMP_POLICY_OGL);
170 so->tex2 = A2XX_SQ_TEX_2_HEIGHT(prsc->height0 - 1) |
171 A2XX_SQ_TEX_2_WIDTH(prsc->width0 - 1);
172 so->tex3 = A2XX_SQ_TEX_3_NUM_FORMAT(fmt.num_format) |
173 fd2_tex_swiz(cso->format, cso->swizzle_r, cso->swizzle_g,
174 cso->swizzle_b, cso->swizzle_a) |
175 A2XX_SQ_TEX_3_EXP_ADJUST(fmt.exp_adjust);
176
177 so->tex4 = A2XX_SQ_TEX_4_MIP_MIN_LEVEL(fd_sampler_first_level(cso)) |
178 A2XX_SQ_TEX_4_MIP_MAX_LEVEL(fd_sampler_last_level(cso));
179
180 so->tex5 = A2XX_SQ_TEX_5_DIMENSION(tex_dimension(prsc->target));
181
182 return &so->base;
183 }
184
185 static void
fd2_set_sampler_views(struct pipe_context * pctx,enum pipe_shader_type shader,unsigned start,unsigned nr,unsigned unbind_num_trailing_slots,bool take_ownership,struct pipe_sampler_view ** views)186 fd2_set_sampler_views(struct pipe_context *pctx, enum pipe_shader_type shader,
187 unsigned start, unsigned nr,
188 unsigned unbind_num_trailing_slots,
189 bool take_ownership,
190 struct pipe_sampler_view **views) in_dt
191 {
192 if (shader == PIPE_SHADER_FRAGMENT) {
193 struct fd_context *ctx = fd_context(pctx);
194
195 /* on a2xx, since there is a flat address space for textures/samplers,
196 * a change in # of fragment textures/samplers will trigger patching and
197 * re-emitting the vertex shader:
198 */
199 if (nr != ctx->tex[PIPE_SHADER_FRAGMENT].num_textures)
200 ctx->dirty |= FD_DIRTY_TEXSTATE;
201 }
202
203 fd_set_sampler_views(pctx, shader, start, nr, unbind_num_trailing_slots,
204 take_ownership, views);
205 }
206
207 /* map gallium sampler-id to hw const-idx.. adreno uses a flat address
208 * space of samplers (const-idx), so we need to map the gallium sampler-id
209 * which is per-shader to a global const-idx space.
210 *
211 * Fragment shader sampler maps directly to const-idx, and vertex shader
212 * is offset by the # of fragment shader samplers. If the # of fragment
213 * shader samplers changes, this shifts the vertex shader indexes.
214 *
215 * TODO maybe we can do frag shader 0..N and vert shader N..0 to avoid
216 * this??
217 */
218 unsigned
fd2_get_const_idx(struct fd_context * ctx,struct fd_texture_stateobj * tex,unsigned samp_id)219 fd2_get_const_idx(struct fd_context *ctx, struct fd_texture_stateobj *tex,
220 unsigned samp_id) assert_dt
221 {
222 if (tex == &ctx->tex[PIPE_SHADER_FRAGMENT])
223 return samp_id;
224 return samp_id + ctx->tex[PIPE_SHADER_FRAGMENT].num_samplers;
225 }
226
227 void
fd2_texture_init(struct pipe_context * pctx)228 fd2_texture_init(struct pipe_context *pctx)
229 {
230 pctx->create_sampler_state = fd2_sampler_state_create;
231 pctx->bind_sampler_states = fd2_sampler_states_bind;
232 pctx->create_sampler_view = fd2_sampler_view_create;
233 pctx->set_sampler_views = fd2_set_sampler_views;
234 }
235