1 /*
2 * Copyright (c) 2012-2015 Etnaviv Project
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sub license,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the
12 * next paragraph) shall be included in all copies or substantial portions
13 * of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Wladimir J. van der Laan <[email protected]>
25 */
26
27 #include "etnaviv_texture_state.h"
28
29 #include "hw/common.xml.h"
30
31 #include "etnaviv_clear_blit.h"
32 #include "etnaviv_context.h"
33 #include "etnaviv_emit.h"
34 #include "etnaviv_format.h"
35 #include "etnaviv_texture.h"
36 #include "etnaviv_translate.h"
37 #include "util/u_inlines.h"
38 #include "util/u_memory.h"
39
40 #include "drm-uapi/drm_fourcc.h"
41
42 struct etna_sampler_state {
43 struct pipe_sampler_state base;
44
45 /* sampler offset +4*sampler, interleave when committing state */
46 uint32_t config0;
47 uint32_t config1;
48 uint32_t config_lod;
49 uint32_t config_3d;
50 uint32_t baselod;
51 unsigned min_lod, max_lod, max_lod_min;
52 };
53
54 static inline struct etna_sampler_state *
etna_sampler_state(struct pipe_sampler_state * samp)55 etna_sampler_state(struct pipe_sampler_state *samp)
56 {
57 return (struct etna_sampler_state *)samp;
58 }
59
60 struct etna_sampler_view {
61 struct pipe_sampler_view base;
62
63 /* sampler offset +4*sampler, interleave when committing state */
64 uint32_t config0;
65 uint32_t config0_mask;
66 uint32_t config1;
67 uint32_t config_3d;
68 uint32_t size;
69 uint32_t log_size;
70 uint32_t astc0;
71 uint32_t linear_stride; /* only LOD0 */
72 struct etna_reloc lod_addr[VIVS_TE_SAMPLER_LOD_ADDR__LEN];
73 unsigned min_lod, max_lod; /* 5.5 fixp */
74
75 struct etna_sampler_ts ts;
76 };
77
78 static inline struct etna_sampler_view *
etna_sampler_view(struct pipe_sampler_view * view)79 etna_sampler_view(struct pipe_sampler_view *view)
80 {
81 return (struct etna_sampler_view *)view;
82 }
83
84 static void *
etna_create_sampler_state_state(struct pipe_context * pipe,const struct pipe_sampler_state * ss)85 etna_create_sampler_state_state(struct pipe_context *pipe,
86 const struct pipe_sampler_state *ss)
87 {
88 struct etna_sampler_state *cs = CALLOC_STRUCT(etna_sampler_state);
89 struct etna_context *ctx = etna_context(pipe);
90 const bool ansio = ss->max_anisotropy > 1;
91 const bool mipmap = ss->min_mip_filter != PIPE_TEX_MIPFILTER_NONE;
92
93 if (!cs)
94 return NULL;
95
96 cs->base = *ss;
97
98 cs->config0 =
99 VIVS_TE_SAMPLER_CONFIG0_UWRAP(translate_texture_wrapmode(ss->wrap_s)) |
100 VIVS_TE_SAMPLER_CONFIG0_VWRAP(translate_texture_wrapmode(ss->wrap_t)) |
101 VIVS_TE_SAMPLER_CONFIG0_MIN(translate_texture_filter(ss->min_img_filter)) |
102 VIVS_TE_SAMPLER_CONFIG0_MIP(translate_texture_mipfilter(ss->min_mip_filter)) |
103 VIVS_TE_SAMPLER_CONFIG0_MAG(translate_texture_filter(ss->mag_img_filter)) |
104 VIVS_TE_SAMPLER_CONFIG0_ANISOTROPY(COND(ansio, etna_log2_fixp55(ss->max_anisotropy)));
105
106 /* ROUND_UV improves precision - but not compatible with NEAREST filter */
107 if (ss->min_img_filter != PIPE_TEX_FILTER_NEAREST &&
108 ss->mag_img_filter != PIPE_TEX_FILTER_NEAREST) {
109 cs->config0 |= VIVS_TE_SAMPLER_CONFIG0_ROUND_UV;
110 }
111
112 cs->config1 =
113 COND(ss->seamless_cube_map, VIVS_TE_SAMPLER_CONFIG1_SEAMLESS_CUBE_MAP);
114
115 cs->config_lod =
116 COND(ss->lod_bias != 0.0 && mipmap, VIVS_TE_SAMPLER_LOD_CONFIG_BIAS_ENABLE) |
117 VIVS_TE_SAMPLER_LOD_CONFIG_BIAS(etna_float_to_fixp55(ss->lod_bias));
118
119 cs->config_3d =
120 VIVS_TE_SAMPLER_3D_CONFIG_WRAP(translate_texture_wrapmode(ss->wrap_r));
121
122 if (mipmap) {
123 cs->min_lod = etna_float_to_fixp55(ss->min_lod);
124 cs->max_lod = etna_float_to_fixp55(ss->max_lod);
125 } else {
126 /* when not mipmapping, we need to set max/min lod so that always
127 * lowest LOD is selected */
128 cs->min_lod = cs->max_lod = etna_float_to_fixp55(0.0f);
129 }
130
131 /* if max_lod is 0, MIN filter will never be used (GC3000)
132 * when min filter is different from mag filter, we need HW to compute LOD
133 * the workaround is to set max_lod to at least 1
134 */
135 cs->max_lod_min = (ss->min_img_filter != ss->mag_img_filter) ? 1 : 0;
136
137 cs->baselod =
138 COND(ss->compare_mode, VIVS_NTE_SAMPLER_BASELOD_COMPARE_ENABLE) |
139 VIVS_NTE_SAMPLER_BASELOD_COMPARE_FUNC(translate_texture_compare(ss->compare_func));
140
141 /* force nearest filting for nir_lower_sample_tex_compare(..) */
142 if ((ctx->screen->info->halti < 2) && ss->compare_mode) {
143 cs->config0 &= ~VIVS_TE_SAMPLER_CONFIG0_MIN__MASK;
144 cs->config0 &= ~VIVS_TE_SAMPLER_CONFIG0_MAG__MASK;
145
146 cs->config0 |=
147 VIVS_TE_SAMPLER_CONFIG0_MIN(TEXTURE_FILTER_NEAREST) |
148 VIVS_TE_SAMPLER_CONFIG0_MAG(TEXTURE_FILTER_NEAREST);
149 }
150
151 return cs;
152 }
153
154 static void
etna_delete_sampler_state_state(struct pipe_context * pctx,void * ss)155 etna_delete_sampler_state_state(struct pipe_context *pctx, void *ss)
156 {
157 FREE(ss);
158 }
159
160 static struct pipe_sampler_view *
etna_create_sampler_view_state(struct pipe_context * pctx,struct pipe_resource * prsc,const struct pipe_sampler_view * so)161 etna_create_sampler_view_state(struct pipe_context *pctx, struct pipe_resource *prsc,
162 const struct pipe_sampler_view *so)
163 {
164 struct etna_sampler_view *sv = CALLOC_STRUCT(etna_sampler_view);
165 struct etna_context *ctx = etna_context(pctx);
166 struct etna_screen *screen = ctx->screen;
167 const uint32_t format = translate_texture_format(so->format);
168 const bool ext = !!(format & EXT_FORMAT);
169 const bool astc = !!(format & ASTC_FORMAT);
170 const bool srgb = util_format_is_srgb(so->format);
171 const uint32_t swiz = get_texture_swiz(so->format, so->swizzle_r,
172 so->swizzle_g, so->swizzle_b,
173 so->swizzle_a);
174
175 if (!sv)
176 return NULL;
177
178 struct etna_resource *res = etna_texture_handle_incompatible(pctx, prsc);
179 if (!res) {
180 free(sv);
181 return NULL;
182 }
183
184 sv->base = *so;
185 pipe_reference_init(&sv->base.reference, 1);
186 sv->base.texture = NULL;
187 pipe_resource_reference(&sv->base.texture, prsc);
188 sv->base.context = pctx;
189
190 /* merged with sampler state */
191 sv->config0 =
192 VIVS_TE_SAMPLER_CONFIG0_TYPE(translate_texture_target(sv->base.target)) |
193 COND(!ext && !astc, VIVS_TE_SAMPLER_CONFIG0_FORMAT(format));
194 sv->config0_mask = 0xffffffff;
195
196 uint32_t base_height = res->base.height0;
197 uint32_t base_depth = res->base.depth0;
198 bool is_array = false;
199
200 switch (sv->base.target) {
201 case PIPE_TEXTURE_1D:
202 /* use 2D texture with T wrap to repeat for 1D texture
203 * TODO: check if old HW supports 1D texture
204 */
205 sv->config0_mask = ~VIVS_TE_SAMPLER_CONFIG0_VWRAP__MASK;
206 sv->config0 &= ~VIVS_TE_SAMPLER_CONFIG0_TYPE__MASK;
207 sv->config0 |=
208 VIVS_TE_SAMPLER_CONFIG0_TYPE(TEXTURE_TYPE_2D) |
209 VIVS_TE_SAMPLER_CONFIG0_VWRAP(TEXTURE_WRAPMODE_REPEAT);
210 break;
211 case PIPE_TEXTURE_1D_ARRAY:
212 is_array = true;
213 base_height = res->base.array_size;
214 break;
215 case PIPE_TEXTURE_2D_ARRAY:
216 is_array = true;
217 base_depth = res->base.array_size;
218 break;
219 default:
220 break;
221 }
222
223 if (res->layout == ETNA_LAYOUT_LINEAR && !util_format_is_compressed(so->format)) {
224 sv->config0 |= VIVS_TE_SAMPLER_CONFIG0_ADDRESSING_MODE(TEXTURE_ADDRESSING_MODE_LINEAR);
225
226 assert(res->base.last_level == 0);
227 sv->linear_stride = res->levels[0].stride;
228 } else {
229 sv->config0 |= VIVS_TE_SAMPLER_CONFIG0_ADDRESSING_MODE(TEXTURE_ADDRESSING_MODE_TILED);
230 sv->linear_stride = 0;
231 }
232
233 sv->config1 |= COND(ext, VIVS_TE_SAMPLER_CONFIG1_FORMAT_EXT(format)) |
234 COND(astc, VIVS_TE_SAMPLER_CONFIG1_FORMAT_EXT(TEXTURE_FORMAT_EXT_ASTC)) |
235 COND(is_array, VIVS_TE_SAMPLER_CONFIG1_TEXTURE_ARRAY) |
236 VIVS_TE_SAMPLER_CONFIG1_HALIGN(res->halign) | swiz;
237 sv->astc0 = COND(astc, VIVS_NTE_SAMPLER_ASTC0_ASTC_FORMAT(format)) |
238 COND(astc && srgb, VIVS_NTE_SAMPLER_ASTC0_ASTC_SRGB) |
239 VIVS_NTE_SAMPLER_ASTC0_UNK8(0xc) |
240 VIVS_NTE_SAMPLER_ASTC0_UNK16(0xc) |
241 VIVS_NTE_SAMPLER_ASTC0_UNK24(0xc);
242 sv->size = VIVS_TE_SAMPLER_SIZE_WIDTH(res->base.width0) |
243 VIVS_TE_SAMPLER_SIZE_HEIGHT(base_height);
244 sv->log_size =
245 VIVS_TE_SAMPLER_LOG_SIZE_WIDTH(etna_log2_fixp55(res->base.width0)) |
246 VIVS_TE_SAMPLER_LOG_SIZE_HEIGHT(etna_log2_fixp55(base_height)) |
247 COND(util_format_is_srgb(so->format) && !astc, VIVS_TE_SAMPLER_LOG_SIZE_SRGB) |
248 COND(astc, VIVS_TE_SAMPLER_LOG_SIZE_ASTC);
249 sv->config_3d =
250 VIVS_TE_SAMPLER_3D_CONFIG_DEPTH(base_depth) |
251 VIVS_TE_SAMPLER_3D_CONFIG_LOG_DEPTH(etna_log2_fixp55(base_depth));
252
253 /* Set up levels-of-detail */
254 for (int lod = 0; lod <= res->base.last_level; ++lod) {
255 sv->lod_addr[lod].bo = res->bo;
256 sv->lod_addr[lod].offset = res->levels[lod].offset;
257 sv->lod_addr[lod].flags = ETNA_RELOC_READ;
258 }
259 sv->min_lod = sv->base.u.tex.first_level << 5;
260 sv->max_lod = MIN2(sv->base.u.tex.last_level, res->base.last_level) << 5;
261
262 /* Workaround for npot textures -- it appears that only CLAMP_TO_EDGE is
263 * supported when the appropriate capability is not set. */
264 if (!etna_core_has_feature(screen->info, ETNA_FEATURE_NON_POWER_OF_TWO) &&
265 (!util_is_power_of_two_or_zero(res->base.width0) ||
266 !util_is_power_of_two_or_zero(res->base.height0))) {
267 sv->config0_mask = ~(VIVS_TE_SAMPLER_CONFIG0_UWRAP__MASK |
268 VIVS_TE_SAMPLER_CONFIG0_VWRAP__MASK);
269 sv->config0 |=
270 VIVS_TE_SAMPLER_CONFIG0_UWRAP(TEXTURE_WRAPMODE_CLAMP_TO_EDGE) |
271 VIVS_TE_SAMPLER_CONFIG0_VWRAP(TEXTURE_WRAPMODE_CLAMP_TO_EDGE);
272 }
273
274 return &sv->base;
275 }
276
277 static void
etna_sampler_view_state_destroy(struct pipe_context * pctx,struct pipe_sampler_view * view)278 etna_sampler_view_state_destroy(struct pipe_context *pctx,
279 struct pipe_sampler_view *view)
280 {
281 pipe_resource_reference(&view->texture, NULL);
282 FREE(view);
283 }
284
285 #define EMIT_STATE(state_name, src_value) \
286 etna_coalsence_emit(stream, &coalesce, VIVS_##state_name, src_value)
287
288 #define EMIT_STATE_FIXP(state_name, src_value) \
289 etna_coalsence_emit_fixp(stream, &coalesce, VIVS_##state_name, src_value)
290
291 #define EMIT_STATE_RELOC(state_name, src_value) \
292 etna_coalsence_emit_reloc(stream, &coalesce, VIVS_##state_name, src_value)
293
294 static void
etna_emit_ts_state(struct etna_context * ctx)295 etna_emit_ts_state(struct etna_context *ctx)
296 {
297 struct etna_cmd_stream *stream = ctx->stream;
298 uint32_t active_samplers = active_samplers_bits(ctx);
299 uint32_t dirty = ctx->dirty;
300 struct etna_coalesce coalesce;
301
302 etna_coalesce_start(stream, &coalesce);
303
304 if (unlikely(dirty & ETNA_DIRTY_SAMPLER_VIEWS)) {
305 for (int x = 0; x < VIVS_TS_SAMPLER__LEN; ++x) {
306 if ((1 << x) & active_samplers) {
307 struct etna_sampler_view *sv = etna_sampler_view(ctx->sampler_view[x]);
308 /*01720*/ EMIT_STATE(TS_SAMPLER_CONFIG(x), sv->ts.TS_SAMPLER_CONFIG);
309 }
310 }
311 for (int x = 0; x < VIVS_TS_SAMPLER__LEN; ++x) {
312 if ((1 << x) & active_samplers) {
313 struct etna_sampler_view *sv = etna_sampler_view(ctx->sampler_view[x]);
314 /*01740*/ EMIT_STATE_RELOC(TS_SAMPLER_STATUS_BASE(x), &sv->ts.TS_SAMPLER_STATUS_BASE);
315 }
316 }
317 for (int x = 0; x < VIVS_TS_SAMPLER__LEN; ++x) {
318 if ((1 << x) & active_samplers) {
319 struct etna_sampler_view *sv = etna_sampler_view(ctx->sampler_view[x]);
320 /*01760*/ EMIT_STATE(TS_SAMPLER_CLEAR_VALUE(x), sv->ts.TS_SAMPLER_CLEAR_VALUE);
321 }
322 }
323 for (int x = 0; x < VIVS_TS_SAMPLER__LEN; ++x) {
324 if ((1 << x) & active_samplers) {
325 struct etna_sampler_view *sv = etna_sampler_view(ctx->sampler_view[x]);
326 /*01780*/ EMIT_STATE(TS_SAMPLER_CLEAR_VALUE2(x), sv->ts.TS_SAMPLER_CLEAR_VALUE2);
327 }
328 }
329 }
330
331 etna_coalesce_end(stream, &coalesce);
332 }
333
334 static void
etna_emit_new_texture_state(struct etna_context * ctx)335 etna_emit_new_texture_state(struct etna_context *ctx)
336 {
337 struct etna_cmd_stream *stream = ctx->stream;
338 struct etna_screen *screen = ctx->screen;
339 uint32_t active_samplers = active_samplers_bits(ctx);
340 uint32_t dirty = ctx->dirty;
341 struct etna_coalesce coalesce;
342
343 etna_emit_ts_state(ctx);
344
345 etna_coalesce_start(stream, &coalesce);
346
347 if (unlikely(dirty & (ETNA_DIRTY_SAMPLER_VIEWS | ETNA_DIRTY_SAMPLERS))) {
348 for (int x = 0; x < VIVS_NTE_SAMPLER__LEN; ++x) {
349 if ((1 << x) & (active_samplers | ctx->prev_active_samplers)) {
350 uint32_t val = 0; /* 0 == sampler inactive */
351
352 /* set active samplers to their configuration value (determined by
353 * both the sampler state and sampler view) */
354 if ((1 << x) & active_samplers) {
355 struct etna_sampler_state *ss = etna_sampler_state(ctx->sampler[x]);
356 struct etna_sampler_view *sv = etna_sampler_view(ctx->sampler_view[x]);
357
358 val = (ss->config0 & sv->config0_mask) | sv->config0;
359 }
360
361 /*10000*/ EMIT_STATE(NTE_SAMPLER_CONFIG0(x), val);
362 }
363 }
364 }
365 if (unlikely(dirty & (ETNA_DIRTY_SAMPLER_VIEWS))) {
366 struct etna_sampler_view *sv;
367
368 for (int x = 0; x < VIVS_NTE_SAMPLER__LEN; ++x) {
369 if ((1 << x) & active_samplers) {
370 sv = etna_sampler_view(ctx->sampler_view[x]);
371 /*10080*/ EMIT_STATE(NTE_SAMPLER_SIZE(x), sv->size);
372 }
373 }
374 }
375 if (unlikely(dirty & (ETNA_DIRTY_SAMPLER_VIEWS | ETNA_DIRTY_SAMPLERS))) {
376 struct etna_sampler_state *ss;
377 struct etna_sampler_view *sv;
378
379 for (int x = 0; x < VIVS_NTE_SAMPLER__LEN; ++x) {
380 if ((1 << x) & active_samplers) {
381 ss = etna_sampler_state(ctx->sampler[x]);
382 sv = etna_sampler_view(ctx->sampler_view[x]);
383 uint32_t log_size = sv->log_size;
384
385 if (texture_use_int_filter(&sv->base, &ss->base, false))
386 log_size |= VIVS_TE_SAMPLER_LOG_SIZE_INT_FILTER;
387
388 /*10100*/ EMIT_STATE(NTE_SAMPLER_LOG_SIZE(x), log_size);
389 }
390 }
391 for (int x = 0; x < VIVS_NTE_SAMPLER__LEN; ++x) {
392 if ((1 << x) & active_samplers) {
393 ss = etna_sampler_state(ctx->sampler[x]);
394 sv = etna_sampler_view(ctx->sampler_view[x]);
395
396 unsigned max_lod = MAX2(MIN2(ss->max_lod + sv->min_lod, sv->max_lod), ss->max_lod_min);
397 unsigned min_lod = MIN2(MAX2(ss->min_lod + sv->min_lod, sv->min_lod), max_lod);
398
399 /* min and max lod is determined both by the sampler and the view */
400 /*10180*/ EMIT_STATE(NTE_SAMPLER_LOD_CONFIG(x),
401 ss->config_lod |
402 VIVS_TE_SAMPLER_LOD_CONFIG_MAX(max_lod) |
403 VIVS_TE_SAMPLER_LOD_CONFIG_MIN(min_lod));
404 }
405 }
406 }
407 if (unlikely(dirty & (ETNA_DIRTY_SAMPLER_VIEWS))) {
408 /* only LOD0 is valid for this register */
409 for (int x = 0; x < VIVS_NTE_SAMPLER__LEN; ++x) {
410 if ((1 << x) & active_samplers) {
411 struct etna_sampler_view *sv = etna_sampler_view(ctx->sampler_view[x]);
412 /*10280*/ EMIT_STATE(NTE_SAMPLER_LINEAR_STRIDE(0, x), sv->linear_stride);
413 }
414 }
415 }
416 if (unlikely(dirty & (ETNA_DIRTY_SAMPLER_VIEWS | ETNA_DIRTY_SAMPLERS))) {
417 struct etna_sampler_state *ss;
418 struct etna_sampler_view *sv;
419
420 for (int x = 0; x < VIVS_NTE_SAMPLER__LEN; ++x) {
421 if ((1 << x) & active_samplers) {
422 ss = etna_sampler_state(ctx->sampler[x]);
423 sv = etna_sampler_view(ctx->sampler_view[x]);
424
425 /*10300*/ EMIT_STATE(NTE_SAMPLER_3D_CONFIG(x), ss->config_3d |
426 sv->config_3d);
427 }
428 }
429 for (int x = 0; x < VIVS_NTE_SAMPLER__LEN; ++x) {
430 if ((1 << x) & active_samplers) {
431 ss = etna_sampler_state(ctx->sampler[x]);
432 sv = etna_sampler_view(ctx->sampler_view[x]);
433
434 /*10380*/ EMIT_STATE(NTE_SAMPLER_CONFIG1(x), ss->config1 |
435 sv->config1 |
436 COND(sv->ts.enable, VIVS_TE_SAMPLER_CONFIG1_USE_TS));
437 }
438 }
439 }
440 if (unlikely(screen->specs.tex_astc && (dirty & (ETNA_DIRTY_SAMPLER_VIEWS)))) {
441 for (int x = 0; x < VIVS_NTE_SAMPLER__LEN; ++x) {
442 if ((1 << x) & active_samplers) {
443 struct etna_sampler_view *sv = etna_sampler_view(ctx->sampler_view[x]);
444 /*10500*/ EMIT_STATE(NTE_SAMPLER_ASTC0(x), sv->astc0);
445 }
446 }
447 }
448 if (unlikely(dirty & (ETNA_DIRTY_SAMPLERS))) {
449 for (int x = 0; x < VIVS_NTE_SAMPLER__LEN; ++x) {
450 if ((1 << x) & active_samplers) {
451 struct etna_sampler_state *ss = etna_sampler_state(ctx->sampler[x]);
452 /*10700*/ EMIT_STATE(NTE_SAMPLER_BASELOD(x), ss->baselod);
453 }
454 }
455 }
456
457 if (unlikely(dirty & (ETNA_DIRTY_SAMPLER_VIEWS))) {
458 for (int x = 0; x < VIVS_NTE_SAMPLER__LEN; ++x) {
459 if ((1 << x) & active_samplers) {
460 for (int y = 0; y < VIVS_NTE_SAMPLER_ADDR_LOD__LEN; ++y) {
461 struct etna_sampler_view *sv = etna_sampler_view(ctx->sampler_view[x]);
462 /*10800*/ EMIT_STATE_RELOC(NTE_SAMPLER_ADDR_LOD(x, y), &sv->lod_addr[y]);
463 }
464 }
465 }
466 }
467
468 etna_coalesce_end(stream, &coalesce);
469
470 ctx->prev_active_samplers = active_samplers;
471 }
472
473 /* Emit plain (non-descriptor) texture state */
474 static void
etna_emit_texture_state(struct etna_context * ctx)475 etna_emit_texture_state(struct etna_context *ctx)
476 {
477 struct etna_cmd_stream *stream = ctx->stream;
478 struct etna_screen *screen = ctx->screen;
479 uint32_t active_samplers = active_samplers_bits(ctx);
480 uint32_t dirty = ctx->dirty;
481 struct etna_coalesce coalesce;
482
483 etna_emit_ts_state(ctx);
484
485 etna_coalesce_start(stream, &coalesce);
486
487 if (unlikely(dirty & (ETNA_DIRTY_SAMPLER_VIEWS | ETNA_DIRTY_SAMPLERS))) {
488 for (int x = 0; x < VIVS_TE_SAMPLER__LEN; ++x) {
489 if ((1 << x) & (active_samplers | ctx->prev_active_samplers)) {
490 uint32_t val = 0; /* 0 == sampler inactive */
491
492 /* set active samplers to their configuration value (determined by
493 * both the sampler state and sampler view) */
494 if ((1 << x) & active_samplers) {
495 struct etna_sampler_state *ss = etna_sampler_state(ctx->sampler[x]);
496 struct etna_sampler_view *sv = etna_sampler_view(ctx->sampler_view[x]);
497
498 val = (ss->config0 & sv->config0_mask) | sv->config0;
499 }
500
501 /*02000*/ EMIT_STATE(TE_SAMPLER_CONFIG0(x), val);
502 }
503 }
504 }
505 if (unlikely(dirty & (ETNA_DIRTY_SAMPLER_VIEWS))) {
506 struct etna_sampler_view *sv;
507
508 for (int x = 0; x < VIVS_TE_SAMPLER__LEN; ++x) {
509 if ((1 << x) & active_samplers) {
510 sv = etna_sampler_view(ctx->sampler_view[x]);
511 /*02040*/ EMIT_STATE(TE_SAMPLER_SIZE(x), sv->size);
512 }
513 }
514 }
515 if (unlikely(dirty & (ETNA_DIRTY_SAMPLER_VIEWS | ETNA_DIRTY_SAMPLERS))) {
516 struct etna_sampler_state *ss;
517 struct etna_sampler_view *sv;
518
519 for (int x = 0; x < VIVS_TE_SAMPLER__LEN; ++x) {
520 if ((1 << x) & active_samplers) {
521 ss = etna_sampler_state(ctx->sampler[x]);
522 sv = etna_sampler_view(ctx->sampler_view[x]);
523 uint32_t log_size = sv->log_size;
524
525 if (texture_use_int_filter(&sv->base, &ss->base, false))
526 log_size |= VIVS_TE_SAMPLER_LOG_SIZE_INT_FILTER;
527
528 /*02080*/ EMIT_STATE(TE_SAMPLER_LOG_SIZE(x), log_size);
529 }
530 }
531 for (int x = 0; x < VIVS_TE_SAMPLER__LEN; ++x) {
532 if ((1 << x) & active_samplers) {
533 ss = etna_sampler_state(ctx->sampler[x]);
534 sv = etna_sampler_view(ctx->sampler_view[x]);
535
536 unsigned max_lod = MAX2(MIN2(ss->max_lod + sv->min_lod, sv->max_lod), ss->max_lod_min);
537 unsigned min_lod = MIN2(MAX2(ss->min_lod + sv->min_lod, sv->min_lod), max_lod);
538
539 /* min and max lod is determined both by the sampler and the view */
540 /*020C0*/ EMIT_STATE(TE_SAMPLER_LOD_CONFIG(x),
541 ss->config_lod |
542 VIVS_TE_SAMPLER_LOD_CONFIG_MAX(max_lod) |
543 VIVS_TE_SAMPLER_LOD_CONFIG_MIN(min_lod));
544 }
545 }
546 for (int x = 0; x < VIVS_TE_SAMPLER__LEN; ++x) {
547 if ((1 << x) & active_samplers) {
548 ss = etna_sampler_state(ctx->sampler[x]);
549 sv = etna_sampler_view(ctx->sampler_view[x]);
550
551 /*02180*/ EMIT_STATE(TE_SAMPLER_3D_CONFIG(x), ss->config_3d |
552 sv->config_3d);
553 }
554 }
555 for (int x = 0; x < VIVS_TE_SAMPLER__LEN; ++x) {
556 if ((1 << x) & active_samplers) {
557 ss = etna_sampler_state(ctx->sampler[x]);
558 sv = etna_sampler_view(ctx->sampler_view[x]);
559
560 /*021C0*/ EMIT_STATE(TE_SAMPLER_CONFIG1(x), ss->config1 |
561 sv->config1 |
562 COND(sv->ts.enable, VIVS_TE_SAMPLER_CONFIG1_USE_TS));
563 }
564 }
565 }
566 if (unlikely(dirty & (ETNA_DIRTY_SAMPLER_VIEWS))) {
567 for (int y = 0; y < VIVS_TE_SAMPLER_LOD_ADDR__LEN; ++y) {
568 for (int x = 0; x < VIVS_TE_SAMPLER__LEN; ++x) {
569 if ((1 << x) & active_samplers) {
570 struct etna_sampler_view *sv = etna_sampler_view(ctx->sampler_view[x]);
571 /*02400*/ EMIT_STATE_RELOC(TE_SAMPLER_LOD_ADDR(x, y), &sv->lod_addr[y]);
572 }
573 }
574 }
575 }
576 if (unlikely(dirty & (ETNA_DIRTY_SAMPLER_VIEWS))) {
577 /* only LOD0 is valid for this register */
578 for (int x = 0; x < VIVS_TE_SAMPLER__LEN; ++x) {
579 if ((1 << x) & active_samplers) {
580 struct etna_sampler_view *sv = etna_sampler_view(ctx->sampler_view[x]);
581 /*02C00*/ EMIT_STATE(TE_SAMPLER_LINEAR_STRIDE(0, x), sv->linear_stride);
582 }
583 }
584 }
585 if (unlikely(screen->specs.tex_astc && (dirty & (ETNA_DIRTY_SAMPLER_VIEWS)))) {
586 for (int x = 0; x < VIVS_TE_SAMPLER__LEN; ++x) {
587 if ((1 << x) & active_samplers) {
588 struct etna_sampler_view *sv = etna_sampler_view(ctx->sampler_view[x]);
589 /*10500*/ EMIT_STATE(NTE_SAMPLER_ASTC0(x), sv->astc0);
590 }
591 }
592 }
593
594 etna_coalesce_end(stream, &coalesce);
595
596 ctx->prev_active_samplers = active_samplers;
597 }
598
599 #undef EMIT_STATE
600 #undef EMIT_STATE_FIXP
601 #undef EMIT_STATE_RELOC
602
603 static struct etna_sampler_ts*
etna_ts_for_sampler_view_state(struct pipe_sampler_view * pview)604 etna_ts_for_sampler_view_state(struct pipe_sampler_view *pview)
605 {
606 struct etna_sampler_view *sv = etna_sampler_view(pview);
607 return &sv->ts;
608 }
609
610 void
etna_texture_state_init(struct pipe_context * pctx)611 etna_texture_state_init(struct pipe_context *pctx)
612 {
613 struct etna_context *ctx = etna_context(pctx);
614 DBG("etnaviv: Using state-based texturing");
615 ctx->base.create_sampler_state = etna_create_sampler_state_state;
616 ctx->base.delete_sampler_state = etna_delete_sampler_state_state;
617 ctx->base.create_sampler_view = etna_create_sampler_view_state;
618 ctx->base.sampler_view_destroy = etna_sampler_view_state_destroy;
619 ctx->ts_for_sampler_view = etna_ts_for_sampler_view_state;
620
621 STATIC_ASSERT(VIVS_TE_SAMPLER_LOD_ADDR__LEN == VIVS_NTE_SAMPLER_ADDR_LOD__LEN);
622
623 if (ctx->screen->info->halti >= 1)
624 ctx->emit_texture_state = etna_emit_new_texture_state;
625 else
626 ctx->emit_texture_state = etna_emit_texture_state;
627 }
628