1 /*
2 * Copyright (c) 2012-2015 Etnaviv Project
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sub license,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the
12 * next paragraph) shall be included in all copies or substantial portions
13 * of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Wladimir J. van der Laan <[email protected]>
25 * Christian Gmeiner <[email protected]>
26 */
27
28 #include "etnaviv_screen.h"
29
30 #include "hw/common.xml.h"
31
32 #include "etnaviv_compiler.h"
33 #include "etnaviv_context.h"
34 #include "etnaviv_debug.h"
35 #include "etnaviv_fence.h"
36 #include "etnaviv_format.h"
37 #include "etnaviv_query.h"
38 #include "etnaviv_resource.h"
39 #include "etnaviv_translate.h"
40
41 #include "util/hash_table.h"
42 #include "util/os_time.h"
43 #include "util/u_math.h"
44 #include "util/u_memory.h"
45 #include "util/u_screen.h"
46 #include "util/u_string.h"
47
48 #include "frontend/drm_driver.h"
49
50 #include "drm-uapi/drm_fourcc.h"
51
52 #define ETNA_DRM_VERSION_FENCE_FD ETNA_DRM_VERSION(1, 1)
53 #define ETNA_DRM_VERSION_PERFMON ETNA_DRM_VERSION(1, 2)
54
55 static const struct debug_named_value etna_debug_options[] = {
56 {"dbg_msgs", ETNA_DBG_MSGS, "Print debug messages"},
57 {"drm_msgs", ETNA_DRM_MSGS, "Print drm messages"},
58 {"frame_msgs", ETNA_DBG_FRAME_MSGS, "Print frame messages"},
59 {"resource_msgs", ETNA_DBG_RESOURCE_MSGS, "Print resource messages"},
60 {"compiler_msgs", ETNA_DBG_COMPILER_MSGS, "Print compiler messages"},
61 {"linker_msgs", ETNA_DBG_LINKER_MSGS, "Print linker messages"},
62 {"ml_msgs", ETNA_DBG_ML_MSGS, "Print ML messages"},
63 {"dump_shaders", ETNA_DBG_DUMP_SHADERS, "Dump shaders"},
64 {"no_ts", ETNA_DBG_NO_TS, "Disable TS"},
65 {"no_autodisable", ETNA_DBG_NO_AUTODISABLE, "Disable autodisable"},
66 {"no_supertile", ETNA_DBG_NO_SUPERTILE, "Disable supertiles"},
67 {"no_early_z", ETNA_DBG_NO_EARLY_Z, "Disable early z"},
68 {"cflush_all", ETNA_DBG_CFLUSH_ALL, "Flush every cache before state update"},
69 {"flush_all", ETNA_DBG_FLUSH_ALL, "Flush after every rendered primitive"},
70 {"zero", ETNA_DBG_ZERO, "Zero all resources after allocation"},
71 {"draw_stall", ETNA_DBG_DRAW_STALL, "Stall FE/PE after each rendered primitive"},
72 {"shaderdb", ETNA_DBG_SHADERDB, "Enable shaderdb output"},
73 {"no_singlebuffer",ETNA_DBG_NO_SINGLEBUF, "Disable single buffer feature"},
74 {"deqp", ETNA_DBG_DEQP, "Hacks to run dEQP GLES3 tests"}, /* needs MESA_GLES_VERSION_OVERRIDE=3.0 */
75 {"nocache", ETNA_DBG_NOCACHE, "Disable shader cache"},
76 {"linear_pe", ETNA_DBG_LINEAR_PE, "Enable linear PE"},
77 {"no_msaa", ETNA_DBG_NO_MSAA, "Disable MSAA support"},
78 {"shared_ts", ETNA_DBG_SHARED_TS, "Enable TS sharing"},
79 {"perf", ETNA_DBG_PERF, "Enable performance warnings"},
80 {"npu_parallel", ETNA_DBG_NPU_PARALLEL, "Enable parallelism inside NPU batches (unsafe)"},
81 {"npu_no_batching",ETNA_DBG_NPU_NO_BATCHING, "Disable batching NPU jobs"},
82 DEBUG_NAMED_VALUE_END
83 };
84
85 DEBUG_GET_ONCE_FLAGS_OPTION(etna_mesa_debug, "ETNA_MESA_DEBUG", etna_debug_options, 0)
86 int etna_mesa_debug = 0;
87
88 static void
etna_screen_destroy(struct pipe_screen * pscreen)89 etna_screen_destroy(struct pipe_screen *pscreen)
90 {
91 struct etna_screen *screen = etna_screen(pscreen);
92
93 if (screen->dummy_desc_reloc.bo)
94 etna_bo_del(screen->dummy_desc_reloc.bo);
95
96 if (screen->dummy_rt_reloc.bo)
97 etna_bo_del(screen->dummy_rt_reloc.bo);
98
99 if (screen->perfmon)
100 etna_perfmon_del(screen->perfmon);
101
102 util_dynarray_fini(&screen->supported_pm_queries);
103
104 etna_shader_screen_fini(pscreen);
105
106 if (screen->pipe_nn)
107 etna_pipe_del(screen->pipe_nn);
108
109 if (screen->pipe)
110 etna_pipe_del(screen->pipe);
111
112 if (screen->npu && screen->npu != screen->gpu)
113 etna_gpu_del(screen->npu);
114
115 if (screen->gpu)
116 etna_gpu_del(screen->gpu);
117
118 if (screen->ro)
119 screen->ro->destroy(screen->ro);
120
121 if (screen->dev)
122 etna_device_del(screen->dev);
123
124 FREE(screen);
125 }
126
127 static const char *
etna_screen_get_name(struct pipe_screen * pscreen)128 etna_screen_get_name(struct pipe_screen *pscreen)
129 {
130 struct etna_screen *priv = etna_screen(pscreen);
131 static char buffer[128];
132
133 snprintf(buffer, sizeof(buffer), "Vivante GC%x rev %04x", priv->info->model,
134 priv->info->revision);
135
136 return buffer;
137 }
138
139 static const char *
etna_screen_get_vendor(struct pipe_screen * pscreen)140 etna_screen_get_vendor(struct pipe_screen *pscreen)
141 {
142 return "Mesa";
143 }
144
145 static const char *
etna_screen_get_device_vendor(struct pipe_screen * pscreen)146 etna_screen_get_device_vendor(struct pipe_screen *pscreen)
147 {
148 return "Vivante";
149 }
150
151 static int
etna_screen_get_param(struct pipe_screen * pscreen,enum pipe_cap param)152 etna_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
153 {
154 struct etna_screen *screen = etna_screen(pscreen);
155
156 switch (param) {
157 /* Supported features (boolean caps). */
158 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
159 case PIPE_CAP_FS_COORD_ORIGIN_UPPER_LEFT:
160 case PIPE_CAP_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
161 case PIPE_CAP_FRAGMENT_SHADER_TEXTURE_LOD:
162 case PIPE_CAP_FRAGMENT_SHADER_DERIVATIVES:
163 case PIPE_CAP_TEXTURE_BARRIER:
164 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
165 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
166 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
167 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
168 case PIPE_CAP_TGSI_TEXCOORD:
169 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
170 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
171 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
172 case PIPE_CAP_STRING_MARKER:
173 case PIPE_CAP_FRONTEND_NOOP:
174 return 1;
175 case PIPE_CAP_NATIVE_FENCE_FD:
176 return screen->drm_version >= ETNA_DRM_VERSION_FENCE_FD;
177 case PIPE_CAP_FS_POSITION_IS_SYSVAL:
178 case PIPE_CAP_FS_FACE_IS_INTEGER_SYSVAL: /* note: not integer */
179 return 1;
180 case PIPE_CAP_FS_POINT_IS_SYSVAL:
181 return 0;
182
183 /* Memory */
184 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
185 return 256;
186 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
187 return 4096;
188
189 case PIPE_CAP_NPOT_TEXTURES:
190 return true; /* VIV_FEATURE(priv->dev, chipMinorFeatures1,
191 NON_POWER_OF_TWO); */
192
193 case PIPE_CAP_ANISOTROPIC_FILTER:
194 case PIPE_CAP_TEXTURE_SWIZZLE:
195 case PIPE_CAP_PRIMITIVE_RESTART:
196 case PIPE_CAP_PRIMITIVE_RESTART_FIXED_INDEX:
197 return VIV_FEATURE(screen, ETNA_FEATURE_HALTI0);
198
199 case PIPE_CAP_ALPHA_TEST:
200 return !VIV_FEATURE(screen, ETNA_FEATURE_PE_NO_ALPHA_TEST);
201
202 /* Unsupported features. */
203 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
204 case PIPE_CAP_TEXRECT:
205 return 0;
206
207 /* Stream output. */
208 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
209 return DBG_ENABLED(ETNA_DBG_DEQP) ? 4 : 0;
210 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
211 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
212 return 0;
213
214 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
215 return 128;
216 case PIPE_CAP_MAX_VERTEX_ELEMENT_SRC_OFFSET:
217 return 255;
218 case PIPE_CAP_MAX_VERTEX_BUFFERS:
219 return screen->info->gpu.stream_count;
220 case PIPE_CAP_VS_INSTANCEID:
221 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
222 return VIV_FEATURE(screen, ETNA_FEATURE_HALTI2);
223
224
225 /* Texturing. */
226 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
227 return VIV_FEATURE(screen, ETNA_FEATURE_HALF_FLOAT);
228 case PIPE_CAP_TEXTURE_SHADOW_MAP:
229 return 1;
230 case PIPE_CAP_MAX_TEXTURE_2D_SIZE:
231 return screen->specs.max_texture_size;
232 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS: /* TODO: verify */
233 return screen->info->halti >= 0 ? screen->specs.max_texture_size : 0;
234 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
235 if (screen->info->halti < 0)
236 return 0;
237 FALLTHROUGH;
238 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
239 {
240 int log2_max_tex_size = util_last_bit(screen->specs.max_texture_size);
241 assert(log2_max_tex_size > 0);
242 return log2_max_tex_size;
243 }
244
245 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
246 case PIPE_CAP_MIN_TEXEL_OFFSET:
247 return -8;
248 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
249 case PIPE_CAP_MAX_TEXEL_OFFSET:
250 return 7;
251 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
252 return screen->specs.seamless_cube_map;
253
254 /* Queries. */
255 case PIPE_CAP_OCCLUSION_QUERY:
256 case PIPE_CAP_CONDITIONAL_RENDER:
257 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
258 return VIV_FEATURE(screen, ETNA_FEATURE_HALTI0);
259
260 /* Preferences */
261 case PIPE_CAP_TEXTURE_TRANSFER_MODES:
262 return 0;
263 case PIPE_CAP_MAX_TEXTURE_UPLOAD_MEMORY_BUDGET: {
264 /* etnaviv is being run on systems as small as 256MB total RAM so
265 * we need to provide a sane value for such a device. Limit the
266 * memory budget to min(~3% of pyhiscal memory, 64MB).
267 *
268 * a simple divison by 32 provides the numbers we want.
269 * 256MB / 32 = 8MB
270 * 2048MB / 32 = 64MB
271 */
272 uint64_t system_memory;
273
274 if (!os_get_total_physical_memory(&system_memory))
275 system_memory = (uint64_t)4096 << 20;
276
277 return MIN2(system_memory / 32, 64 * 1024 * 1024);
278 }
279
280 case PIPE_CAP_MAX_VARYINGS:
281 return screen->specs.max_varyings;
282
283 case PIPE_CAP_SUPPORTED_PRIM_MODES:
284 case PIPE_CAP_SUPPORTED_PRIM_MODES_WITH_RESTART: {
285 /* Generate the bitmask of supported draw primitives. */
286 uint32_t modes = 1 << MESA_PRIM_POINTS |
287 1 << MESA_PRIM_LINES |
288 1 << MESA_PRIM_LINE_STRIP |
289 1 << MESA_PRIM_TRIANGLES |
290 1 << MESA_PRIM_TRIANGLE_FAN;
291
292 /* TODO: The bug relates only to indexed draws, but here we signal
293 * that there is no support for triangle strips at all. This should
294 * be refined.
295 */
296 if (VIV_FEATURE(screen, ETNA_FEATURE_BUG_FIXES8))
297 modes |= 1 << MESA_PRIM_TRIANGLE_STRIP;
298
299 if (VIV_FEATURE(screen, ETNA_FEATURE_LINE_LOOP))
300 modes |= 1 << MESA_PRIM_LINE_LOOP;
301
302 return modes;
303 }
304
305 case PIPE_CAP_PCI_GROUP:
306 case PIPE_CAP_PCI_BUS:
307 case PIPE_CAP_PCI_DEVICE:
308 case PIPE_CAP_PCI_FUNCTION:
309 return 0;
310 case PIPE_CAP_ACCELERATED:
311 return 1;
312 case PIPE_CAP_VIDEO_MEMORY:
313 return 0;
314 case PIPE_CAP_UMA:
315 return 1;
316 case PIPE_CAP_GRAPHICS:
317 return !VIV_FEATURE(screen, ETNA_FEATURE_COMPUTE_ONLY);
318 default:
319 return u_pipe_screen_get_param_defaults(pscreen, param);
320 }
321 }
322
323 static float
etna_screen_get_paramf(struct pipe_screen * pscreen,enum pipe_capf param)324 etna_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
325 {
326 struct etna_screen *screen = etna_screen(pscreen);
327
328 switch (param) {
329 case PIPE_CAPF_MIN_LINE_WIDTH:
330 case PIPE_CAPF_MIN_LINE_WIDTH_AA:
331 case PIPE_CAPF_MIN_POINT_SIZE:
332 case PIPE_CAPF_MIN_POINT_SIZE_AA:
333 return 1;
334 case PIPE_CAPF_POINT_SIZE_GRANULARITY:
335 case PIPE_CAPF_LINE_WIDTH_GRANULARITY:
336 return 0.1;
337 case PIPE_CAPF_MAX_LINE_WIDTH:
338 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
339 case PIPE_CAPF_MAX_POINT_SIZE:
340 case PIPE_CAPF_MAX_POINT_SIZE_AA:
341 return 8192.0f;
342 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
343 return 16.0f;
344 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
345 return util_last_bit(screen->specs.max_texture_size);
346 case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
347 case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
348 case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
349 return 0.0f;
350 }
351
352 debug_printf("unknown paramf %d", param);
353 return 0;
354 }
355
356 static int
etna_screen_get_shader_param(struct pipe_screen * pscreen,enum pipe_shader_type shader,enum pipe_shader_cap param)357 etna_screen_get_shader_param(struct pipe_screen *pscreen,
358 enum pipe_shader_type shader,
359 enum pipe_shader_cap param)
360 {
361 struct etna_screen *screen = etna_screen(pscreen);
362 bool ubo_enable = screen->info->halti >= 2;
363
364 if (DBG_ENABLED(ETNA_DBG_DEQP))
365 ubo_enable = true;
366
367 switch (shader) {
368 case PIPE_SHADER_FRAGMENT:
369 case PIPE_SHADER_VERTEX:
370 break;
371 case PIPE_SHADER_COMPUTE:
372 case PIPE_SHADER_GEOMETRY:
373 case PIPE_SHADER_TESS_CTRL:
374 case PIPE_SHADER_TESS_EVAL:
375 return 0;
376 default:
377 DBG("unknown shader type %d", shader);
378 return 0;
379 }
380
381 switch (param) {
382 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
383 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
384 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
385 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
386 return ETNA_MAX_TOKENS;
387 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
388 return ETNA_MAX_DEPTH; /* XXX */
389 case PIPE_SHADER_CAP_MAX_INPUTS:
390 /* Maximum number of inputs for the vertex shader is the number
391 * of vertex elements - each element defines one vertex shader
392 * input register. For the fragment shader, this is the number
393 * of varyings. */
394 return shader == PIPE_SHADER_FRAGMENT ? screen->specs.max_varyings
395 : screen->specs.vertex_max_elements;
396 case PIPE_SHADER_CAP_MAX_OUTPUTS:
397 return screen->specs.max_vs_outputs;
398 case PIPE_SHADER_CAP_MAX_TEMPS:
399 return 64; /* Max native temporaries. */
400 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
401 return ubo_enable ? ETNA_MAX_CONST_BUF : 1;
402 case PIPE_SHADER_CAP_CONT_SUPPORTED:
403 return 1;
404 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
405 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
406 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
407 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
408 return 1;
409 case PIPE_SHADER_CAP_SUBROUTINES:
410 return 0;
411 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
412 return VIV_FEATURE(screen, ETNA_FEATURE_HAS_SQRT_TRIG);
413 case PIPE_SHADER_CAP_INT64_ATOMICS:
414 case PIPE_SHADER_CAP_FP16:
415 case PIPE_SHADER_CAP_FP16_DERIVATIVES:
416 case PIPE_SHADER_CAP_FP16_CONST_BUFFERS:
417 case PIPE_SHADER_CAP_INT16:
418 case PIPE_SHADER_CAP_GLSL_16BIT_CONSTS:
419 return 0;
420 case PIPE_SHADER_CAP_INTEGERS:
421 return screen->info->halti >= 2;
422 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
423 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
424 return shader == PIPE_SHADER_FRAGMENT
425 ? screen->specs.fragment_sampler_count
426 : screen->specs.vertex_sampler_count;
427 case PIPE_SHADER_CAP_MAX_CONST_BUFFER0_SIZE:
428 if (ubo_enable)
429 return 16384; /* 16384 so state tracker enables UBOs */
430 return shader == PIPE_SHADER_FRAGMENT
431 ? screen->specs.max_ps_uniforms * sizeof(float[4])
432 : screen->specs.max_vs_uniforms * sizeof(float[4]);
433 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
434 return false;
435 case PIPE_SHADER_CAP_SUPPORTED_IRS:
436 return (1 << PIPE_SHADER_IR_TGSI) |
437 (1 << PIPE_SHADER_IR_NIR);
438 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
439 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
440 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
441 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
442 return 0;
443 }
444
445 debug_printf("unknown shader param %d", param);
446 return 0;
447 }
448
449 static bool
gpu_supports_texture_target(struct etna_screen * screen,enum pipe_texture_target target)450 gpu_supports_texture_target(struct etna_screen *screen,
451 enum pipe_texture_target target)
452 {
453 if (target == PIPE_TEXTURE_CUBE_ARRAY)
454 return false;
455
456 /* pre-halti has no array/3D */
457 if (screen->info->halti < 0 &&
458 (target == PIPE_TEXTURE_1D_ARRAY ||
459 target == PIPE_TEXTURE_2D_ARRAY ||
460 target == PIPE_TEXTURE_3D))
461 return false;
462
463 return true;
464 }
465
466 static bool
gpu_supports_texture_format(struct etna_screen * screen,uint32_t fmt,enum pipe_format format)467 gpu_supports_texture_format(struct etna_screen *screen, uint32_t fmt,
468 enum pipe_format format)
469 {
470 bool supported = true;
471
472 /* Requires split sampler support, which the driver doesn't support, yet. */
473 if (!util_format_is_compressed(format) &&
474 util_format_get_blocksizebits(format) > 32)
475 return false;
476
477 if (fmt == TEXTURE_FORMAT_ETC1)
478 supported = VIV_FEATURE(screen, ETNA_FEATURE_ETC1_TEXTURE_COMPRESSION);
479
480 if (fmt >= TEXTURE_FORMAT_DXT1 && fmt <= TEXTURE_FORMAT_DXT4_DXT5)
481 supported = VIV_FEATURE(screen, ETNA_FEATURE_DXT_TEXTURE_COMPRESSION);
482
483 if (util_format_is_srgb(format))
484 supported = VIV_FEATURE(screen, ETNA_FEATURE_HALTI0);
485
486 if (fmt & EXT_FORMAT)
487 supported = VIV_FEATURE(screen, ETNA_FEATURE_HALTI0);
488
489 if (fmt & ASTC_FORMAT) {
490 supported = screen->specs.tex_astc;
491 }
492
493 if (util_format_is_snorm(format))
494 supported = VIV_FEATURE(screen, ETNA_FEATURE_HALTI1);
495
496 if (format != PIPE_FORMAT_S8_UINT_Z24_UNORM &&
497 (util_format_is_pure_integer(format) || util_format_is_float(format)))
498 supported = VIV_FEATURE(screen, ETNA_FEATURE_HALTI2);
499
500
501 if (!supported)
502 return false;
503
504 if (texture_format_needs_swiz(format))
505 return VIV_FEATURE(screen, ETNA_FEATURE_HALTI0);
506
507 return true;
508 }
509
510 static bool
gpu_supports_render_format(struct etna_screen * screen,enum pipe_format format,unsigned sample_count)511 gpu_supports_render_format(struct etna_screen *screen, enum pipe_format format,
512 unsigned sample_count)
513 {
514 const uint32_t fmt = translate_pe_format(format);
515
516 if (fmt == ETNA_NO_MATCH)
517 return false;
518
519 /* Requires split target support, which the driver doesn't support, yet. */
520 if (util_format_get_blocksizebits(format) > 32)
521 return false;
522
523 if (sample_count > 1) {
524 /* Explicitly disabled. */
525 if (DBG_ENABLED(ETNA_DBG_NO_MSAA))
526 return false;
527
528 /* The hardware supports it. */
529 if (!VIV_FEATURE(screen, ETNA_FEATURE_MSAA))
530 return false;
531
532 /* Number of samples must be allowed. */
533 if (!translate_samples_to_xyscale(sample_count, NULL, NULL))
534 return false;
535
536 /* On SMALL_MSAA hardware 2x MSAA does not work. */
537 if (sample_count == 2 && VIV_FEATURE(screen, ETNA_FEATURE_SMALL_MSAA))
538 return false;
539
540 /* BLT/RS supports the format. */
541 if (screen->specs.use_blt) {
542 if (translate_blt_format(format) == ETNA_NO_MATCH)
543 return false;
544 } else {
545 if (translate_rs_format(format) == ETNA_NO_MATCH)
546 return false;
547 }
548 }
549
550 if (format == PIPE_FORMAT_R8_UNORM)
551 return VIV_FEATURE(screen, ETNA_FEATURE_HALTI5);
552
553 /* figure out 8bpp RS clear to enable these formats */
554 if (format == PIPE_FORMAT_R8_SINT || format == PIPE_FORMAT_R8_UINT)
555 return VIV_FEATURE(screen, ETNA_FEATURE_HALTI5);
556
557 if (util_format_is_srgb(format))
558 return VIV_FEATURE(screen, ETNA_FEATURE_HALTI3);
559
560 if (util_format_is_pure_integer(format) || util_format_is_float(format))
561 return VIV_FEATURE(screen, ETNA_FEATURE_HALTI2);
562
563 if (format == PIPE_FORMAT_R8G8_UNORM)
564 return VIV_FEATURE(screen, ETNA_FEATURE_HALTI2);
565
566 /* any other extended format is HALTI0 (only R10G10B10A2?) */
567 if (fmt >= PE_FORMAT_R16F)
568 return VIV_FEATURE(screen, ETNA_FEATURE_HALTI0);
569
570 return true;
571 }
572
573 static bool
gpu_supports_vertex_format(struct etna_screen * screen,enum pipe_format format)574 gpu_supports_vertex_format(struct etna_screen *screen, enum pipe_format format)
575 {
576 if (translate_vertex_format_type(format) == ETNA_NO_MATCH)
577 return false;
578
579 if (util_format_is_pure_integer(format))
580 return VIV_FEATURE(screen, ETNA_FEATURE_HALTI2);
581
582 return true;
583 }
584
585 static bool
etna_screen_is_format_supported(struct pipe_screen * pscreen,enum pipe_format format,enum pipe_texture_target target,unsigned sample_count,unsigned storage_sample_count,unsigned usage)586 etna_screen_is_format_supported(struct pipe_screen *pscreen,
587 enum pipe_format format,
588 enum pipe_texture_target target,
589 unsigned sample_count,
590 unsigned storage_sample_count,
591 unsigned usage)
592 {
593 struct etna_screen *screen = etna_screen(pscreen);
594 unsigned allowed = 0;
595
596 if (!gpu_supports_texture_target(screen, target))
597 return false;
598
599 if (MAX2(1, sample_count) != MAX2(1, storage_sample_count))
600 return false;
601
602 if (usage & PIPE_BIND_RENDER_TARGET) {
603 if (gpu_supports_render_format(screen, format, sample_count))
604 allowed |= PIPE_BIND_RENDER_TARGET;
605 }
606
607 if (usage & PIPE_BIND_DEPTH_STENCIL) {
608 if (translate_depth_format(format) != ETNA_NO_MATCH)
609 allowed |= PIPE_BIND_DEPTH_STENCIL;
610 }
611
612 if (usage & PIPE_BIND_SAMPLER_VIEW) {
613 uint32_t fmt = translate_texture_format(format);
614
615 if (!gpu_supports_texture_format(screen, fmt, format))
616 fmt = ETNA_NO_MATCH;
617
618 if (sample_count < 2 && fmt != ETNA_NO_MATCH)
619 allowed |= PIPE_BIND_SAMPLER_VIEW;
620 }
621
622 if (usage & PIPE_BIND_VERTEX_BUFFER) {
623 if (gpu_supports_vertex_format(screen, format))
624 allowed |= PIPE_BIND_VERTEX_BUFFER;
625 }
626
627 if (usage & PIPE_BIND_INDEX_BUFFER) {
628 /* must be supported index format */
629 if (format == PIPE_FORMAT_R8_UINT || format == PIPE_FORMAT_R16_UINT ||
630 (format == PIPE_FORMAT_R32_UINT &&
631 VIV_FEATURE(screen, ETNA_FEATURE_32_BIT_INDICES))) {
632 allowed |= PIPE_BIND_INDEX_BUFFER;
633 }
634 }
635
636 /* Always allowed */
637 allowed |=
638 usage & (PIPE_BIND_DISPLAY_TARGET | PIPE_BIND_SCANOUT | PIPE_BIND_SHARED);
639
640 if (usage != allowed) {
641 DBG("not supported: format=%s, target=%d, sample_count=%d, "
642 "usage=%x, allowed=%x",
643 util_format_name(format), target, sample_count, usage, allowed);
644 }
645
646 return usage == allowed;
647 }
648
649 const uint64_t supported_modifiers[] = {
650 DRM_FORMAT_MOD_LINEAR,
651 DRM_FORMAT_MOD_VIVANTE_TILED,
652 DRM_FORMAT_MOD_VIVANTE_SUPER_TILED,
653 DRM_FORMAT_MOD_VIVANTE_SPLIT_TILED,
654 DRM_FORMAT_MOD_VIVANTE_SPLIT_SUPER_TILED,
655 };
656
etna_get_num_modifiers(struct etna_screen * screen)657 static int etna_get_num_modifiers(struct etna_screen *screen)
658 {
659 int num = ARRAY_SIZE(supported_modifiers);
660
661 /* don't advertise split tiled formats on single pipe/buffer GPUs */
662 if (screen->specs.pixel_pipes == 1 || screen->specs.single_buffer)
663 num = 3;
664
665 return num;
666 }
667
668 static void
etna_screen_query_dmabuf_modifiers(struct pipe_screen * pscreen,enum pipe_format format,int max,uint64_t * modifiers,unsigned int * external_only,int * count)669 etna_screen_query_dmabuf_modifiers(struct pipe_screen *pscreen,
670 enum pipe_format format, int max,
671 uint64_t *modifiers,
672 unsigned int *external_only, int *count)
673 {
674 struct etna_screen *screen = etna_screen(pscreen);
675 int num_base_mods = etna_get_num_modifiers(screen);
676 int mods_multiplier = 1;
677 int i, j;
678
679 if (DBG_ENABLED(ETNA_DBG_SHARED_TS) &&
680 VIV_FEATURE(screen, ETNA_FEATURE_FAST_CLEAR)) {
681 /* If TS is supported expose the TS modifiers. GPUs with feature
682 * CACHE128B256BPERLINE have both 128B and 256B color tile TS modes,
683 * older cores support exactly one TS layout.
684 */
685 if (VIV_FEATURE(screen, ETNA_FEATURE_CACHE128B256BPERLINE))
686 if (screen->specs.v4_compression &&
687 translate_ts_format(format) != ETNA_NO_MATCH)
688 mods_multiplier += 4;
689 else
690 mods_multiplier += 2;
691 else
692 mods_multiplier += 1;
693 }
694
695 if (max > num_base_mods * mods_multiplier)
696 max = num_base_mods * mods_multiplier;
697
698 if (!max) {
699 modifiers = NULL;
700 max = num_base_mods * mods_multiplier;
701 }
702
703 for (i = 0, *count = 0; *count < max && i < num_base_mods; i++) {
704 for (j = 0; *count < max && j < mods_multiplier; j++, (*count)++) {
705 uint64_t ts_mod;
706
707 if (j == 0) {
708 ts_mod = 0;
709 } else if (VIV_FEATURE(screen, ETNA_FEATURE_CACHE128B256BPERLINE)) {
710 switch (j) {
711 case 1:
712 ts_mod = VIVANTE_MOD_TS_128_4;
713 break;
714 case 2:
715 ts_mod = VIVANTE_MOD_TS_256_4;
716 break;
717 case 3:
718 ts_mod = VIVANTE_MOD_TS_128_4 | VIVANTE_MOD_COMP_DEC400;
719 break;
720 case 4:
721 ts_mod = VIVANTE_MOD_TS_256_4 | VIVANTE_MOD_COMP_DEC400;
722 }
723 } else {
724 if (screen->specs.bits_per_tile == 2)
725 ts_mod = VIVANTE_MOD_TS_64_2;
726 else
727 ts_mod = VIVANTE_MOD_TS_64_4;
728 }
729
730 if (modifiers)
731 modifiers[*count] = supported_modifiers[i] | ts_mod;
732 if (external_only)
733 external_only[*count] = util_format_is_yuv(format) ? 1 : 0;
734 }
735 }
736 }
737
738 static bool
etna_screen_is_dmabuf_modifier_supported(struct pipe_screen * pscreen,uint64_t modifier,enum pipe_format format,bool * external_only)739 etna_screen_is_dmabuf_modifier_supported(struct pipe_screen *pscreen,
740 uint64_t modifier,
741 enum pipe_format format,
742 bool *external_only)
743 {
744 struct etna_screen *screen = etna_screen(pscreen);
745 int num_base_mods = etna_get_num_modifiers(screen);
746 uint64_t base_mod = modifier & ~VIVANTE_MOD_EXT_MASK;
747 uint64_t ts_mod = modifier & VIVANTE_MOD_TS_MASK;
748 int i;
749
750 for (i = 0; i < num_base_mods; i++) {
751 if (base_mod != supported_modifiers[i])
752 continue;
753
754 if ((modifier & VIVANTE_MOD_COMP_DEC400) &&
755 (!screen->specs.v4_compression || translate_ts_format(format) == ETNA_NO_MATCH))
756 return false;
757
758 if (ts_mod) {
759 if (!VIV_FEATURE(screen, ETNA_FEATURE_FAST_CLEAR))
760 return false;
761
762 if (VIV_FEATURE(screen, ETNA_FEATURE_CACHE128B256BPERLINE)) {
763 if (ts_mod != VIVANTE_MOD_TS_128_4 &&
764 ts_mod != VIVANTE_MOD_TS_256_4)
765 return false;
766 } else {
767 if ((screen->specs.bits_per_tile == 2 &&
768 ts_mod != VIVANTE_MOD_TS_64_2) ||
769 (screen->specs.bits_per_tile == 4 &&
770 ts_mod != VIVANTE_MOD_TS_64_4))
771 return false;
772 }
773 }
774
775 if (external_only)
776 *external_only = util_format_is_yuv(format) ? 1 : 0;
777
778 return true;
779 }
780
781 return false;
782 }
783
784 static unsigned int
etna_screen_get_dmabuf_modifier_planes(struct pipe_screen * pscreen,uint64_t modifier,enum pipe_format format)785 etna_screen_get_dmabuf_modifier_planes(struct pipe_screen *pscreen,
786 uint64_t modifier,
787 enum pipe_format format)
788 {
789 unsigned planes = util_format_get_num_planes(format);
790
791 if (modifier & VIVANTE_MOD_TS_MASK)
792 return planes * 2;
793
794 return planes;
795 }
796
797 static void
etna_determine_uniform_limits(struct etna_screen * screen)798 etna_determine_uniform_limits(struct etna_screen *screen)
799 {
800 /* values for the non unified case are taken from
801 * gcmCONFIGUREUNIFORMS in the Vivante kernel driver file
802 * drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_base.h.
803 */
804 if (screen->info->model == chipModel_GC2000 &&
805 (screen->info->revision == 0x5118 || screen->info->revision == 0x5140)) {
806 screen->specs.max_vs_uniforms = 256;
807 screen->specs.max_ps_uniforms = 64;
808 } else if (screen->info->gpu.num_constants == 320) {
809 screen->specs.max_vs_uniforms = 256;
810 screen->specs.max_ps_uniforms = 64;
811 } else if (screen->info->gpu.num_constants > 256 &&
812 screen->info->model == chipModel_GC1000) {
813 /* All GC1000 series chips can only support 64 uniforms for ps on non-unified const mode. */
814 screen->specs.max_vs_uniforms = 256;
815 screen->specs.max_ps_uniforms = 64;
816 } else if (screen->info->gpu.num_constants > 256) {
817 screen->specs.max_vs_uniforms = 256;
818 screen->specs.max_ps_uniforms = 256;
819 } else if (screen->info->gpu.num_constants == 256) {
820 screen->specs.max_vs_uniforms = 256;
821 screen->specs.max_ps_uniforms = 256;
822 } else {
823 screen->specs.max_vs_uniforms = 168;
824 screen->specs.max_ps_uniforms = 64;
825 }
826 }
827
828 static void
etna_determine_sampler_limits(struct etna_screen * screen)829 etna_determine_sampler_limits(struct etna_screen *screen)
830 {
831 /* vertex and fragment samplers live in one address space */
832 if (screen->info->halti >= 1) {
833 screen->specs.vertex_sampler_offset = 16;
834 screen->specs.fragment_sampler_count = 16;
835 screen->specs.vertex_sampler_count = 16;
836 } else {
837 screen->specs.vertex_sampler_offset = 8;
838 screen->specs.fragment_sampler_count = 8;
839 screen->specs.vertex_sampler_count = 4;
840 }
841
842 if (screen->info->model == 0x400)
843 screen->specs.vertex_sampler_count = 0;
844 }
845
846 static void
etna_get_specs(struct etna_screen * screen)847 etna_get_specs(struct etna_screen *screen)
848 {
849 const struct etna_core_info *info = screen->info;
850 uint32_t instruction_count = 0;
851
852 /* Copy all relevant limits from etna_core_info. */
853 if (info->type == ETNA_CORE_GPU) {
854 instruction_count = info->gpu.max_instructions;
855 screen->specs.pixel_pipes = info->gpu.pixel_pipes;
856
857 if (screen->npu)
858 info = etna_gpu_get_core_info(screen->npu);
859 }
860
861 if (info->type == ETNA_CORE_NPU) {
862 if (etna_core_has_feature(info, ETNA_FEATURE_NN_XYDP0))
863 screen->specs.nn_core_version = 8;
864 else if (etna_core_has_feature(info, ETNA_FEATURE_VIP_V7))
865 screen->specs.nn_core_version = 7;
866 else
867 screen->specs.nn_core_version = 6;
868 }
869
870 screen->info->halti = info->halti;
871 if (screen->info->halti >= 0)
872 DBG("etnaviv: GPU arch: HALTI%d", screen->info->halti);
873 else
874 DBG("etnaviv: GPU arch: pre-HALTI");
875
876 screen->specs.can_supertile =
877 VIV_FEATURE(screen, ETNA_FEATURE_SUPER_TILED);
878 screen->specs.bits_per_tile =
879 !VIV_FEATURE(screen, ETNA_FEATURE_2BITPERTILE) ||
880 VIV_FEATURE(screen, ETNA_FEATURE_CACHE128B256BPERLINE) ? 4 : 2;
881
882 screen->specs.ts_clear_value =
883 VIV_FEATURE(screen, ETNA_FEATURE_DEC400) ? 0xffffffff :
884 screen->specs.bits_per_tile == 4 ? 0x11111111 : 0x55555555;
885
886 screen->specs.vs_need_z_div =
887 screen->info->model < 0x1000 && screen->info->model != 0x880;
888 screen->specs.has_shader_range_registers =
889 screen->info->model >= 0x1000 || screen->info->model == 0x880;
890 screen->specs.has_new_transcendentals =
891 VIV_FEATURE(screen, ETNA_FEATURE_HAS_FAST_TRANSCENDENTALS);
892 screen->specs.has_no_oneconst_limit =
893 VIV_FEATURE(screen, ETNA_FEATURE_SH_NO_ONECONST_LIMIT);
894 screen->specs.v4_compression =
895 VIV_FEATURE(screen, ETNA_FEATURE_V4_COMPRESSION);
896 screen->specs.seamless_cube_map =
897 (screen->info->model != 0x880) && /* Seamless cubemap is broken on GC880? */
898 VIV_FEATURE(screen, ETNA_FEATURE_SEAMLESS_CUBE_MAP);
899
900 if (screen->info->halti >= 5) {
901 /* GC7000 - this core must load shaders from memory. */
902 screen->specs.vs_offset = 0;
903 screen->specs.ps_offset = 0;
904 screen->specs.max_instructions = 0; /* Do not program shaders manually */
905 screen->specs.has_icache = true;
906 } else if (VIV_FEATURE(screen, ETNA_FEATURE_INSTRUCTION_CACHE)) {
907 /* GC3000 - this core is capable of loading shaders from
908 * memory. It can also run shaders from registers, as a fallback, but
909 * "max_instructions" does not have the correct value. It has place for
910 * 2*256 instructions just like GC2000, but the offsets are slightly
911 * different.
912 */
913 screen->specs.vs_offset = 0xC000;
914 /* State 08000-0C000 mirrors 0C000-0E000, and the Vivante driver uses
915 * this mirror for writing PS instructions, probably safest to do the
916 * same.
917 */
918 screen->specs.ps_offset = 0x8000 + 0x1000;
919 screen->specs.max_instructions = 256; /* maximum number instructions for non-icache use */
920 screen->specs.has_icache = true;
921 } else {
922 if (instruction_count > 256) { /* unified instruction memory? */
923 screen->specs.vs_offset = 0xC000;
924 screen->specs.ps_offset = 0xD000; /* like vivante driver */
925 screen->specs.max_instructions = 256;
926 } else {
927 screen->specs.vs_offset = 0x4000;
928 screen->specs.ps_offset = 0x6000;
929 screen->specs.max_instructions = instruction_count;
930 }
931 screen->specs.has_icache = false;
932 }
933
934 if (VIV_FEATURE(screen, ETNA_FEATURE_HALTI0)) {
935 screen->specs.vertex_max_elements = 16;
936 } else {
937 /* Etna_viv documentation seems confused over the correct value
938 * here so choose the lower to be safe: HALTI0 says 16 i.s.o.
939 * 10, but VERTEX_ELEMENT_CONFIG register says 16 i.s.o. 12. */
940 screen->specs.vertex_max_elements = 10;
941 }
942
943 etna_determine_uniform_limits(screen);
944 etna_determine_sampler_limits(screen);
945
946 if (screen->info->halti >= 5) {
947 screen->specs.has_unified_uniforms = true;
948 screen->specs.vs_uniforms_offset = VIVS_SH_HALTI5_UNIFORMS_MIRROR(0);
949 screen->specs.ps_uniforms_offset = VIVS_SH_HALTI5_UNIFORMS(screen->specs.max_vs_uniforms*4);
950 } else if (screen->info->halti >= 1) {
951 /* unified uniform memory on GC3000 - HALTI1 feature bit is just a guess
952 */
953 screen->specs.has_unified_uniforms = true;
954 screen->specs.vs_uniforms_offset = VIVS_SH_UNIFORMS(0);
955 /* hardcode PS uniforms to start after end of VS uniforms -
956 * for more flexibility this offset could be variable based on the
957 * shader.
958 */
959 screen->specs.ps_uniforms_offset = VIVS_SH_UNIFORMS(screen->specs.max_vs_uniforms*4);
960 } else {
961 screen->specs.has_unified_uniforms = false;
962 screen->specs.vs_uniforms_offset = VIVS_VS_UNIFORMS(0);
963 screen->specs.ps_uniforms_offset = VIVS_PS_UNIFORMS(0);
964 }
965
966 screen->specs.max_vs_outputs = screen->info->halti >= 5 ? 32 : 16;
967
968 screen->specs.max_varyings = MIN3(ETNA_NUM_VARYINGS,
969 info->gpu.max_varyings,
970 /* one output slot used for position */
971 screen->specs.max_vs_outputs - 1);
972
973 screen->specs.max_texture_size =
974 VIV_FEATURE(screen, ETNA_FEATURE_TEXTURE_8K) ? 8192 : 2048;
975 screen->specs.max_rendertarget_size =
976 VIV_FEATURE(screen, ETNA_FEATURE_RENDERTARGET_8K) ? 8192 : 2048;
977
978 screen->specs.single_buffer = VIV_FEATURE(screen, ETNA_FEATURE_SINGLE_BUFFER);
979 if (screen->specs.single_buffer)
980 DBG("etnaviv: Single buffer mode enabled with %d pixel pipes", screen->specs.pixel_pipes);
981
982 screen->specs.tex_astc = VIV_FEATURE(screen, ETNA_FEATURE_TEXTURE_ASTC) &&
983 !VIV_FEATURE(screen, ETNA_FEATURE_NO_ASTC);
984
985 screen->specs.use_blt = VIV_FEATURE(screen, ETNA_FEATURE_BLT_ENGINE);
986
987 /* Only allow fast clear with MC2.0 or MMUv2, as the TS unit bypasses the
988 * memory offset for the MMUv1 linear window on MC1.0 and we have no way to
989 * fixup the address.
990 */
991 if (!VIV_FEATURE(screen, ETNA_FEATURE_MC20) &&
992 !VIV_FEATURE(screen, ETNA_FEATURE_MMU_VERSION))
993 etna_core_disable_feature(screen->info, ETNA_FEATURE_FAST_CLEAR);
994 }
995
996 struct etna_bo *
etna_screen_bo_from_handle(struct pipe_screen * pscreen,struct winsys_handle * whandle)997 etna_screen_bo_from_handle(struct pipe_screen *pscreen,
998 struct winsys_handle *whandle)
999 {
1000 struct etna_screen *screen = etna_screen(pscreen);
1001 struct etna_bo *bo;
1002
1003 if (whandle->type == WINSYS_HANDLE_TYPE_SHARED) {
1004 bo = etna_bo_from_name(screen->dev, whandle->handle);
1005 } else if (whandle->type == WINSYS_HANDLE_TYPE_FD) {
1006 bo = etna_bo_from_dmabuf(screen->dev, whandle->handle);
1007 } else {
1008 DBG("Attempt to import unsupported handle type %d", whandle->type);
1009 return NULL;
1010 }
1011
1012 if (!bo) {
1013 DBG("ref name 0x%08x failed", whandle->handle);
1014 return NULL;
1015 }
1016
1017 return bo;
1018 }
1019
1020 static const void *
etna_get_compiler_options(struct pipe_screen * pscreen,enum pipe_shader_ir ir,enum pipe_shader_type shader)1021 etna_get_compiler_options(struct pipe_screen *pscreen,
1022 enum pipe_shader_ir ir, enum pipe_shader_type shader)
1023 {
1024 return etna_compiler_get_options(etna_screen(pscreen)->compiler);
1025 }
1026
1027 static struct disk_cache *
etna_get_disk_shader_cache(struct pipe_screen * pscreen)1028 etna_get_disk_shader_cache(struct pipe_screen *pscreen)
1029 {
1030 struct etna_screen *screen = etna_screen(pscreen);
1031 struct etna_compiler *compiler = screen->compiler;
1032
1033 return compiler->disk_cache;
1034 }
1035
1036 static int
etna_screen_get_fd(struct pipe_screen * pscreen)1037 etna_screen_get_fd(struct pipe_screen *pscreen)
1038 {
1039 struct etna_screen *screen = etna_screen(pscreen);
1040 return etna_device_fd(screen->dev);
1041 }
1042
1043 struct pipe_screen *
etna_screen_create(struct etna_device * dev,struct etna_gpu * gpu,struct etna_gpu * npu,struct renderonly * ro)1044 etna_screen_create(struct etna_device *dev, struct etna_gpu *gpu,
1045 struct etna_gpu *npu, struct renderonly *ro)
1046 {
1047 struct etna_screen *screen = CALLOC_STRUCT(etna_screen);
1048 struct pipe_screen *pscreen;
1049
1050 if (!screen)
1051 return NULL;
1052
1053 if (!gpu)
1054 gpu = npu;
1055
1056 pscreen = &screen->base;
1057 screen->dev = dev;
1058 screen->gpu = gpu;
1059 screen->npu = npu;
1060 screen->ro = ro;
1061 screen->info = etna_gpu_get_core_info(gpu);
1062
1063 screen->drm_version = etnaviv_device_version(screen->dev);
1064 etna_mesa_debug = debug_get_option_etna_mesa_debug();
1065
1066 /* Disable autodisable for correct rendering with TS */
1067 etna_mesa_debug |= ETNA_DBG_NO_AUTODISABLE;
1068
1069 screen->pipe = etna_pipe_new(gpu, ETNA_PIPE_3D);
1070 if (!screen->pipe) {
1071 DBG("could not create 3d pipe");
1072 goto fail;
1073 }
1074
1075 if (gpu != npu) {
1076 screen->pipe_nn = etna_pipe_new(npu, ETNA_PIPE_3D);
1077 if (!screen->pipe_nn) {
1078 DBG("could not create nn pipe");
1079 goto fail;
1080 }
1081 }
1082
1083 /* apply debug options that disable individual features */
1084 if (DBG_ENABLED(ETNA_DBG_NO_EARLY_Z))
1085 etna_core_disable_feature(screen->info, ETNA_FEATURE_NO_EARLY_Z);
1086 if (DBG_ENABLED(ETNA_DBG_NO_TS))
1087 etna_core_disable_feature(screen->info, ETNA_FEATURE_FAST_CLEAR);
1088 if (DBG_ENABLED(ETNA_DBG_NO_AUTODISABLE))
1089 etna_core_disable_feature(screen->info, ETNA_FEATURE_AUTO_DISABLE);
1090 if (DBG_ENABLED(ETNA_DBG_NO_SUPERTILE))
1091 etna_core_disable_feature(screen->info, ETNA_FEATURE_SUPER_TILED);
1092 if (DBG_ENABLED(ETNA_DBG_NO_SINGLEBUF))
1093 etna_core_disable_feature(screen->info, ETNA_FEATURE_SINGLE_BUFFER);
1094 if (!DBG_ENABLED(ETNA_DBG_LINEAR_PE))
1095 etna_core_disable_feature(screen->info, ETNA_FEATURE_LINEAR_PE);
1096
1097 etna_get_specs(screen);
1098
1099 if (screen->info->halti >= 5 && !etnaviv_device_softpin_capable(dev)) {
1100 DBG("halti5 requires softpin");
1101 goto fail;
1102 }
1103
1104 pscreen->destroy = etna_screen_destroy;
1105 pscreen->get_screen_fd = etna_screen_get_fd;
1106 pscreen->get_param = etna_screen_get_param;
1107 pscreen->get_paramf = etna_screen_get_paramf;
1108 pscreen->get_shader_param = etna_screen_get_shader_param;
1109 pscreen->get_compiler_options = etna_get_compiler_options;
1110 pscreen->get_disk_shader_cache = etna_get_disk_shader_cache;
1111
1112 pscreen->get_name = etna_screen_get_name;
1113 pscreen->get_vendor = etna_screen_get_vendor;
1114 pscreen->get_device_vendor = etna_screen_get_device_vendor;
1115
1116 pscreen->context_create = etna_context_create;
1117 pscreen->is_format_supported = etna_screen_is_format_supported;
1118 pscreen->query_dmabuf_modifiers = etna_screen_query_dmabuf_modifiers;
1119 pscreen->is_dmabuf_modifier_supported = etna_screen_is_dmabuf_modifier_supported;
1120 pscreen->get_dmabuf_modifier_planes = etna_screen_get_dmabuf_modifier_planes;
1121
1122 if (!etna_shader_screen_init(pscreen))
1123 goto fail;
1124
1125 etna_fence_screen_init(pscreen);
1126 etna_query_screen_init(pscreen);
1127 etna_resource_screen_init(pscreen);
1128
1129 util_dynarray_init(&screen->supported_pm_queries, NULL);
1130 slab_create_parent(&screen->transfer_pool, sizeof(struct etna_transfer), 16);
1131
1132 if (screen->drm_version >= ETNA_DRM_VERSION_PERFMON)
1133 etna_pm_query_setup(screen);
1134
1135
1136 /* create dummy RT buffer, used when rendering with no color buffer */
1137 screen->dummy_rt_reloc.bo = etna_bo_new(screen->dev, 64 * 64 * 4,
1138 DRM_ETNA_GEM_CACHE_WC);
1139 if (!screen->dummy_rt_reloc.bo)
1140 goto fail;
1141
1142 screen->dummy_rt_reloc.offset = 0;
1143 screen->dummy_rt_reloc.flags = ETNA_RELOC_READ | ETNA_RELOC_WRITE;
1144
1145 if (screen->info->halti >= 5) {
1146 void *buf;
1147
1148 /* create an empty dummy texture descriptor */
1149 screen->dummy_desc_reloc.bo = etna_bo_new(screen->dev, 0x100,
1150 DRM_ETNA_GEM_CACHE_WC);
1151 if (!screen->dummy_desc_reloc.bo)
1152 goto fail;
1153
1154 buf = etna_bo_map(screen->dummy_desc_reloc.bo);
1155 etna_bo_cpu_prep(screen->dummy_desc_reloc.bo, DRM_ETNA_PREP_WRITE);
1156 memset(buf, 0, 0x100);
1157 etna_bo_cpu_fini(screen->dummy_desc_reloc.bo);
1158 screen->dummy_desc_reloc.offset = 0;
1159 screen->dummy_desc_reloc.flags = ETNA_RELOC_READ;
1160 }
1161
1162 return pscreen;
1163
1164 fail:
1165 etna_screen_destroy(pscreen);
1166 return NULL;
1167 }
1168