1 /*
2 * Copyright (c) 2017 Etnaviv Project
3 * Copyright (C) 2017 Zodiac Inflight Innovations
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sub license,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the
13 * next paragraph) shall be included in all copies or substantial portions
14 * of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 *
24 * Authors:
25 * Wladimir J. van der Laan <[email protected]>
26 */
27 #include "etnaviv_blt.h"
28
29 #include "etnaviv_emit.h"
30 #include "etnaviv_clear_blit.h"
31 #include "etnaviv_context.h"
32 #include "etnaviv_emit.h"
33 #include "etnaviv_format.h"
34 #include "etnaviv_resource.h"
35 #include "etnaviv_surface.h"
36 #include "etnaviv_translate.h"
37
38 #include "util/u_math.h"
39 #include "pipe/p_defines.h"
40 #include "pipe/p_state.h"
41 #include "util/u_blitter.h"
42 #include "util/u_inlines.h"
43 #include "util/u_memory.h"
44 #include "util/u_surface.h"
45
46 #include "hw/common_3d.xml.h"
47 #include "hw/state_blt.xml.h"
48 #include "hw/common.xml.h"
49
50 #include <assert.h>
51
52 static uint32_t
etna_compatible_blt_format(enum pipe_format fmt)53 etna_compatible_blt_format(enum pipe_format fmt)
54 {
55 /* YUYV and UYVY are blocksize 4, but 2 bytes per pixel */
56 if (fmt == PIPE_FORMAT_YUYV || fmt == PIPE_FORMAT_UYVY)
57 return BLT_FORMAT_R8G8;
58
59 switch (util_format_get_blocksize(fmt)) {
60 case 1: return BLT_FORMAT_R8;
61 case 2: return BLT_FORMAT_R8G8;
62 case 4: return BLT_FORMAT_A8R8G8B8;
63 case 8: return BLT_FORMAT_A16R16G16B16;
64 default: return ETNA_NO_MATCH;
65 }
66 }
67
68 static inline uint32_t
blt_compute_stride_bits(const struct blt_imginfo * img)69 blt_compute_stride_bits(const struct blt_imginfo *img)
70 {
71 return VIVS_BLT_DEST_STRIDE_TILING(img->tiling == ETNA_LAYOUT_LINEAR ? 0 : 3) | /* 1/3? */
72 VIVS_BLT_DEST_STRIDE_FORMAT(img->format) |
73 VIVS_BLT_DEST_STRIDE_STRIDE(img->stride) |
74 COND(img->downsample_x, VIVS_BLT_SRC_STRIDE_DOWNSAMPLE_X) |
75 COND(img->downsample_y, VIVS_BLT_SRC_STRIDE_DOWNSAMPLE_Y);
76 }
77
78 static inline uint32_t
blt_compute_img_config_bits(const struct blt_imginfo * img,bool for_dest)79 blt_compute_img_config_bits(const struct blt_imginfo *img, bool for_dest)
80 {
81 uint32_t tiling_bits = 0;
82 if (img->tiling == ETNA_LAYOUT_SUPER_TILED) {
83 tiling_bits |= for_dest ? BLT_IMAGE_CONFIG_TO_SUPER_TILED : BLT_IMAGE_CONFIG_FROM_SUPER_TILED;
84 }
85
86 return BLT_IMAGE_CONFIG_TS_MODE(img->ts_mode) |
87 COND(img->use_ts, BLT_IMAGE_CONFIG_TS) |
88 COND(img->use_ts && img->ts_compress_fmt >= 0, BLT_IMAGE_CONFIG_COMPRESSION) |
89 BLT_IMAGE_CONFIG_COMPRESSION_FORMAT(img->ts_compress_fmt) |
90 COND(for_dest, BLT_IMAGE_CONFIG_UNK22) |
91 BLT_IMAGE_CONFIG_SWIZ_R(0) | /* not used? */
92 BLT_IMAGE_CONFIG_SWIZ_G(1) |
93 BLT_IMAGE_CONFIG_SWIZ_B(2) |
94 BLT_IMAGE_CONFIG_SWIZ_A(3) |
95 tiling_bits;
96 }
97
98 static inline uint32_t
blt_compute_swizzle_bits(const struct blt_imginfo * img,bool for_dest)99 blt_compute_swizzle_bits(const struct blt_imginfo *img, bool for_dest)
100 {
101 uint32_t swiz = VIVS_BLT_SWIZZLE_SRC_R(img->swizzle[0]) |
102 VIVS_BLT_SWIZZLE_SRC_G(img->swizzle[1]) |
103 VIVS_BLT_SWIZZLE_SRC_B(img->swizzle[2]) |
104 VIVS_BLT_SWIZZLE_SRC_A(img->swizzle[3]);
105 return for_dest ? (swiz << 12) : swiz;
106 }
107
108 /* Clear (part of) an image */
109 static void
emit_blt_clearimage(struct etna_cmd_stream * stream,const struct blt_clear_op * op)110 emit_blt_clearimage(struct etna_cmd_stream *stream, const struct blt_clear_op *op)
111 {
112 etna_cmd_stream_reserve(stream, 64*2); /* Make sure BLT op doesn't get broken up */
113
114 etna_set_state(stream, VIVS_BLT_ENABLE, 0x00000001);
115 assert(op->dest.bpp);
116 etna_set_state(stream, VIVS_BLT_CONFIG, VIVS_BLT_CONFIG_CLEAR_BPP(op->dest.bpp-1));
117 /* NB: blob sets format to 1 in dest/src config for clear, and the swizzle to RRRR.
118 * does this matter? It seems to just be ignored. But if we run into issues with BLT
119 * behaving stragely, it's something to look at.
120 */
121 etna_set_state(stream, VIVS_BLT_DEST_STRIDE, blt_compute_stride_bits(&op->dest));
122 etna_set_state(stream, VIVS_BLT_DEST_CONFIG, blt_compute_img_config_bits(&op->dest, true));
123 etna_set_state_reloc(stream, VIVS_BLT_DEST_ADDR, &op->dest.addr);
124 etna_set_state(stream, VIVS_BLT_SRC_STRIDE, blt_compute_stride_bits(&op->dest));
125 etna_set_state(stream, VIVS_BLT_SRC_CONFIG, blt_compute_img_config_bits(&op->dest, false));
126 etna_set_state_reloc(stream, VIVS_BLT_SRC_ADDR, &op->dest.addr);
127 etna_set_state(stream, VIVS_BLT_DEST_POS, VIVS_BLT_DEST_POS_X(op->rect_x) | VIVS_BLT_DEST_POS_Y(op->rect_y));
128 etna_set_state(stream, VIVS_BLT_IMAGE_SIZE, VIVS_BLT_IMAGE_SIZE_WIDTH(op->rect_w) | VIVS_BLT_IMAGE_SIZE_HEIGHT(op->rect_h));
129 etna_set_state(stream, VIVS_BLT_CLEAR_COLOR0, op->clear_value[0]);
130 etna_set_state(stream, VIVS_BLT_CLEAR_COLOR1, op->clear_value[1]);
131 etna_set_state(stream, VIVS_BLT_CLEAR_BITS0, op->clear_bits[0]);
132 etna_set_state(stream, VIVS_BLT_CLEAR_BITS1, op->clear_bits[1]);
133 if (op->dest.use_ts) {
134 etna_set_state_reloc(stream, VIVS_BLT_DEST_TS, &op->dest.ts_addr);
135 etna_set_state_reloc(stream, VIVS_BLT_SRC_TS, &op->dest.ts_addr);
136 etna_set_state(stream, VIVS_BLT_DEST_TS_CLEAR_VALUE0, op->dest.ts_clear_value[0]);
137 etna_set_state(stream, VIVS_BLT_DEST_TS_CLEAR_VALUE1, op->dest.ts_clear_value[1]);
138 etna_set_state(stream, VIVS_BLT_SRC_TS_CLEAR_VALUE0, op->dest.ts_clear_value[0]);
139 etna_set_state(stream, VIVS_BLT_SRC_TS_CLEAR_VALUE1, op->dest.ts_clear_value[1]);
140 }
141 etna_set_state(stream, VIVS_BLT_SET_COMMAND, 0x00000003);
142 etna_set_state(stream, VIVS_BLT_COMMAND, VIVS_BLT_COMMAND_COMMAND_CLEAR_IMAGE);
143 etna_set_state(stream, VIVS_BLT_SET_COMMAND, 0x00000003);
144 etna_set_state(stream, VIVS_BLT_ENABLE, 0x00000000);
145 }
146
147 /* Copy (a subset of) an image to another image. */
148 static void
emit_blt_copyimage(struct etna_cmd_stream * stream,const struct blt_imgcopy_op * op)149 emit_blt_copyimage(struct etna_cmd_stream *stream, const struct blt_imgcopy_op *op)
150 {
151 etna_cmd_stream_reserve(stream, 64*2); /* Never allow BLT sequences to be broken up */
152
153 etna_set_state(stream, VIVS_BLT_ENABLE, 0x00000001);
154 etna_set_state(stream, VIVS_BLT_CONFIG,
155 VIVS_BLT_CONFIG_SRC_ENDIAN(op->src.endian_mode) |
156 VIVS_BLT_CONFIG_DEST_ENDIAN(op->dest.endian_mode));
157 etna_set_state(stream, VIVS_BLT_SRC_STRIDE, blt_compute_stride_bits(&op->src));
158 etna_set_state(stream, VIVS_BLT_SRC_CONFIG, blt_compute_img_config_bits(&op->src, false));
159 etna_set_state(stream, VIVS_BLT_SWIZZLE,
160 blt_compute_swizzle_bits(&op->src, false) |
161 blt_compute_swizzle_bits(&op->dest, true));
162 etna_set_state(stream, VIVS_BLT_UNK140A0, 0x00040004);
163 etna_set_state(stream, VIVS_BLT_UNK1409C, 0x00400040);
164 if (op->src.use_ts) {
165 etna_set_state_reloc(stream, VIVS_BLT_SRC_TS, &op->src.ts_addr);
166 etna_set_state(stream, VIVS_BLT_SRC_TS_CLEAR_VALUE0, op->src.ts_clear_value[0]);
167 etna_set_state(stream, VIVS_BLT_SRC_TS_CLEAR_VALUE1, op->src.ts_clear_value[1]);
168 }
169 etna_set_state_reloc(stream, VIVS_BLT_SRC_ADDR, &op->src.addr);
170 etna_set_state(stream, VIVS_BLT_DEST_STRIDE, blt_compute_stride_bits(&op->dest));
171 etna_set_state(stream, VIVS_BLT_DEST_CONFIG,
172 blt_compute_img_config_bits(&op->dest, true) |
173 COND(op->flip_y, BLT_IMAGE_CONFIG_FLIP_Y));
174 assert(!op->dest.use_ts); /* Dest TS path doesn't work for copies? */
175 if (op->dest.use_ts) {
176 etna_set_state_reloc(stream, VIVS_BLT_DEST_TS, &op->dest.ts_addr);
177 etna_set_state(stream, VIVS_BLT_DEST_TS_CLEAR_VALUE0, op->dest.ts_clear_value[0]);
178 etna_set_state(stream, VIVS_BLT_DEST_TS_CLEAR_VALUE1, op->dest.ts_clear_value[1]);
179 }
180 etna_set_state_reloc(stream, VIVS_BLT_DEST_ADDR, &op->dest.addr);
181 etna_set_state(stream, VIVS_BLT_SRC_POS, VIVS_BLT_DEST_POS_X(op->src_x) | VIVS_BLT_DEST_POS_Y(op->src_y));
182 etna_set_state(stream, VIVS_BLT_DEST_POS, VIVS_BLT_DEST_POS_X(op->dest_x) | VIVS_BLT_DEST_POS_Y(op->dest_y));
183 etna_set_state(stream, VIVS_BLT_IMAGE_SIZE, VIVS_BLT_IMAGE_SIZE_WIDTH(op->rect_w) | VIVS_BLT_IMAGE_SIZE_HEIGHT(op->rect_h));
184 etna_set_state(stream, VIVS_BLT_UNK14058, 0xffffffff);
185 etna_set_state(stream, VIVS_BLT_UNK1405C, 0xffffffff);
186 etna_set_state(stream, VIVS_BLT_SET_COMMAND, 0x00000003);
187 etna_set_state(stream, VIVS_BLT_COMMAND, VIVS_BLT_COMMAND_COMMAND_COPY_IMAGE);
188 etna_set_state(stream, VIVS_BLT_SET_COMMAND, 0x00000003);
189 etna_set_state(stream, VIVS_BLT_ENABLE, 0x00000000);
190 }
191
192 /* Emit in-place resolve using BLT. */
193 static void
emit_blt_inplace(struct etna_cmd_stream * stream,const struct blt_inplace_op * op)194 emit_blt_inplace(struct etna_cmd_stream *stream, const struct blt_inplace_op *op)
195 {
196 assert(op->bpp > 0 && util_is_power_of_two_nonzero(op->bpp));
197 etna_cmd_stream_reserve(stream, 64*2); /* Never allow BLT sequences to be broken up */
198 etna_set_state(stream, VIVS_BLT_ENABLE, 0x00000001);
199 etna_set_state(stream, VIVS_BLT_CONFIG,
200 VIVS_BLT_CONFIG_INPLACE_TS_MODE(op->ts_mode) |
201 VIVS_BLT_CONFIG_INPLACE_BOTH |
202 (util_logbase2(op->bpp) << VIVS_BLT_CONFIG_INPLACE_BPP__SHIFT));
203 etna_set_state(stream, VIVS_BLT_DEST_TS_CLEAR_VALUE0, op->ts_clear_value[0]);
204 etna_set_state(stream, VIVS_BLT_DEST_TS_CLEAR_VALUE1, op->ts_clear_value[1]);
205 etna_set_state_reloc(stream, VIVS_BLT_DEST_ADDR, &op->addr);
206 etna_set_state_reloc(stream, VIVS_BLT_DEST_TS, &op->ts_addr);
207 etna_set_state(stream, 0x14068, op->num_tiles);
208 etna_set_state(stream, VIVS_BLT_SET_COMMAND, 0x00000003);
209 etna_set_state(stream, VIVS_BLT_COMMAND, 0x00000004);
210 etna_set_state(stream, VIVS_BLT_SET_COMMAND, 0x00000003);
211 etna_set_state(stream, VIVS_BLT_ENABLE, 0x00000000);
212 }
213
214 static void
etna_blit_clear_color_blt(struct pipe_context * pctx,struct pipe_surface * dst,const union pipe_color_union * color)215 etna_blit_clear_color_blt(struct pipe_context *pctx, struct pipe_surface *dst,
216 const union pipe_color_union *color)
217 {
218 struct etna_context *ctx = etna_context(pctx);
219 struct etna_surface *surf = etna_surface(dst);
220 uint64_t new_clear_value = etna_clear_blit_pack_rgba(surf->base.format, color);
221 int msaa_xscale = 1, msaa_yscale = 1;
222
223 translate_samples_to_xyscale(surf->base.texture->nr_samples,
224 &msaa_xscale, &msaa_yscale);
225
226 struct etna_resource *res = etna_resource(surf->base.texture);
227 struct blt_clear_op clr = {};
228 clr.dest.addr.bo = res->bo;
229 clr.dest.addr.offset = surf->offset;
230 clr.dest.addr.flags = ETNA_RELOC_WRITE;
231 clr.dest.bpp = util_format_get_blocksize(surf->base.format);
232 clr.dest.stride = surf->level->stride;
233 clr.dest.tiling = res->layout;
234
235 if (surf->level->ts_size) {
236 clr.dest.use_ts = 1;
237 clr.dest.ts_addr.bo = res->ts_bo;
238 clr.dest.ts_addr.offset = surf->ts_offset;
239 clr.dest.ts_addr.flags = ETNA_RELOC_WRITE;
240 clr.dest.ts_clear_value[0] = new_clear_value;
241 clr.dest.ts_clear_value[1] = new_clear_value >> 32;
242 clr.dest.ts_mode = surf->level->ts_mode;
243 clr.dest.ts_compress_fmt = surf->level->ts_compress_fmt;
244 }
245
246 clr.clear_value[0] = new_clear_value;
247 clr.clear_value[1] = new_clear_value >> 32;
248 clr.clear_bits[0] = 0xffffffff; /* TODO: Might want to clear only specific channels? */
249 clr.clear_bits[1] = 0xffffffff;
250 clr.rect_x = 0; /* What about scissors? */
251 clr.rect_y = 0;
252 clr.rect_w = surf->level->width * msaa_xscale;
253 clr.rect_h = surf->level->height * msaa_yscale;
254
255 emit_blt_clearimage(ctx->stream, &clr);
256
257 /* This made the TS valid */
258 if (surf->level->ts_size) {
259 ctx->framebuffer.TS_COLOR_CLEAR_VALUE = new_clear_value;
260 ctx->framebuffer.TS_COLOR_CLEAR_VALUE_EXT = new_clear_value >> 32;
261
262 /* update clear color in SW meta area of the buffer if TS is exported */
263 if (unlikely(new_clear_value != surf->level->clear_value &&
264 etna_resource_ext_ts(etna_resource(dst->texture))))
265 surf->level->ts_meta->v0.clear_value = new_clear_value;
266
267 etna_resource_level_ts_mark_valid(surf->level);
268 ctx->dirty |= ETNA_DIRTY_TS | ETNA_DIRTY_DERIVE_TS;
269 }
270
271 surf->level->clear_value = new_clear_value;
272 resource_written(ctx, surf->base.texture);
273 etna_resource_level_mark_changed(surf->level);
274 }
275
276 static void
etna_blit_clear_zs_blt(struct pipe_context * pctx,struct pipe_surface * dst,unsigned buffers,double depth,unsigned stencil)277 etna_blit_clear_zs_blt(struct pipe_context *pctx, struct pipe_surface *dst,
278 unsigned buffers, double depth, unsigned stencil)
279 {
280 struct etna_context *ctx = etna_context(pctx);
281 struct etna_surface *surf = etna_surface(dst);
282 uint32_t new_clear_value = translate_clear_depth_stencil(surf->base.format, depth, stencil);
283 uint32_t new_clear_bits = 0, clear_bits_depth, clear_bits_stencil;
284 int msaa_xscale = 1, msaa_yscale = 1;
285
286 translate_samples_to_xyscale(surf->base.texture->nr_samples,
287 &msaa_xscale, &msaa_yscale);
288
289 /* Get the channels to clear */
290 switch (surf->base.format) {
291 case PIPE_FORMAT_Z16_UNORM:
292 case PIPE_FORMAT_X8Z24_UNORM:
293 clear_bits_depth = 0xffffffff;
294 clear_bits_stencil = 0x00000000;
295 break;
296 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
297 clear_bits_depth = 0xffffff00;
298 clear_bits_stencil = 0x000000ff;
299 break;
300 default:
301 clear_bits_depth = clear_bits_stencil = 0xffffffff;
302 break;
303 }
304
305 if (buffers & PIPE_CLEAR_DEPTH)
306 new_clear_bits |= clear_bits_depth;
307 if (buffers & PIPE_CLEAR_STENCIL)
308 new_clear_bits |= clear_bits_stencil;
309
310 /* if all bits are cleared, update TS clear value */
311 if (new_clear_bits == 0xffffffff)
312 surf->level->clear_value = new_clear_value;
313
314 /* TODO unduplicate this */
315 struct etna_resource *res = etna_resource(surf->base.texture);
316 struct blt_clear_op clr = {};
317 clr.dest.addr.bo = res->bo;
318 clr.dest.addr.offset = surf->offset;
319 clr.dest.addr.flags = ETNA_RELOC_WRITE;
320 clr.dest.bpp = util_format_get_blocksize(surf->base.format);
321 clr.dest.stride = surf->level->stride;
322 clr.dest.tiling = res->layout;
323
324 if (surf->level->ts_size) {
325 clr.dest.use_ts = 1;
326 clr.dest.ts_addr.bo = res->ts_bo;
327 clr.dest.ts_addr.offset = surf->ts_offset;
328 clr.dest.ts_addr.flags = ETNA_RELOC_WRITE;
329 clr.dest.ts_clear_value[0] = surf->level->clear_value;
330 clr.dest.ts_clear_value[1] = surf->level->clear_value;
331 clr.dest.ts_mode = surf->level->ts_mode;
332 clr.dest.ts_compress_fmt = surf->level->ts_compress_fmt;
333 }
334
335 clr.clear_value[0] = new_clear_value;
336 clr.clear_value[1] = new_clear_value;
337 clr.clear_bits[0] = new_clear_bits;
338 clr.clear_bits[1] = new_clear_bits;
339 clr.rect_x = 0; /* What about scissors? */
340 clr.rect_y = 0;
341 clr.rect_w = surf->level->width * msaa_xscale;
342 clr.rect_h = surf->level->height * msaa_yscale;
343
344 emit_blt_clearimage(ctx->stream, &clr);
345
346 /* This made the TS valid */
347 if (surf->level->ts_size) {
348 ctx->framebuffer.TS_DEPTH_CLEAR_VALUE = surf->level->clear_value;
349 etna_resource_level_ts_mark_valid(surf->level);
350 ctx->dirty |= ETNA_DIRTY_TS | ETNA_DIRTY_DERIVE_TS;
351 }
352
353 resource_written(ctx, surf->base.texture);
354 etna_resource_level_mark_changed(surf->level);
355 }
356
357 static void
etna_clear_blt(struct pipe_context * pctx,unsigned buffers,const struct pipe_scissor_state * scissor_state,const union pipe_color_union * color,double depth,unsigned stencil)358 etna_clear_blt(struct pipe_context *pctx, unsigned buffers, const struct pipe_scissor_state *scissor_state,
359 const union pipe_color_union *color, double depth, unsigned stencil)
360 {
361 struct etna_context *ctx = etna_context(pctx);
362
363 if (!etna_render_condition_check(pctx))
364 return;
365
366 etna_set_state(ctx->stream, VIVS_GL_FLUSH_CACHE, 0x00000c23);
367 etna_set_state(ctx->stream, VIVS_TS_FLUSH_CACHE, VIVS_TS_FLUSH_CACHE_FLUSH);
368
369 if (buffers & PIPE_CLEAR_COLOR) {
370 for (int idx = 0; idx < ctx->framebuffer_s.nr_cbufs; ++idx) {
371 struct etna_surface *surf = etna_surface(ctx->framebuffer_s.cbufs[idx]);
372
373 etna_blit_clear_color_blt(pctx, ctx->framebuffer_s.cbufs[idx],
374 &color[idx]);
375
376 if (!etna_resource(surf->prsc)->explicit_flush)
377 etna_context_add_flush_resource(ctx, surf->prsc);
378 }
379 }
380
381 if ((buffers & PIPE_CLEAR_DEPTHSTENCIL) && ctx->framebuffer_s.zsbuf != NULL)
382 etna_blit_clear_zs_blt(pctx, ctx->framebuffer_s.zsbuf, buffers, depth, stencil);
383
384 etna_stall(ctx->stream, SYNC_RECIPIENT_RA, SYNC_RECIPIENT_BLT);
385
386 if ((buffers & PIPE_CLEAR_COLOR) && (buffers & PIPE_CLEAR_DEPTH))
387 etna_set_state(ctx->stream, VIVS_GL_FLUSH_CACHE, 0x00000c23);
388 else
389 etna_set_state(ctx->stream, VIVS_GL_FLUSH_CACHE, 0x00000002);
390 }
391
392 static bool
etna_try_blt_blit(struct pipe_context * pctx,const struct pipe_blit_info * blit_info)393 etna_try_blt_blit(struct pipe_context *pctx,
394 const struct pipe_blit_info *blit_info)
395 {
396 struct etna_context *ctx = etna_context(pctx);
397 struct etna_resource *src = etna_resource(blit_info->src.resource);
398 struct etna_resource *dst = etna_resource(blit_info->dst.resource);
399 int src_xscale, src_yscale, dst_xscale, dst_yscale;
400 bool downsample_x = false, downsample_y = false;
401
402 /* Ensure that the level is valid */
403 assert(blit_info->src.level <= src->base.last_level);
404 assert(blit_info->dst.level <= dst->base.last_level);
405
406 if (!translate_samples_to_xyscale(src->base.nr_samples, &src_xscale, &src_yscale))
407 return false;
408 if (!translate_samples_to_xyscale(dst->base.nr_samples, &dst_xscale, &dst_yscale))
409 return false;
410
411 /* BLT does not support upscaling */
412 if ((src_xscale < dst_xscale) || (src_yscale < dst_yscale))
413 return false;
414
415 if (src_xscale > dst_xscale)
416 downsample_x = true;
417 if (src_yscale > dst_yscale)
418 downsample_y = true;
419
420 /* The width/height are in pixels; they do not change as a result of
421 * multi-sampling. So, when blitting from a 4x multisampled surface
422 * to a non-multisampled surface, the width and height will be
423 * identical. As we do not support scaling, reject different sizes.
424 * TODO: could handle 2x downsample here with emit_blt_genmipmaps */
425 if (blit_info->dst.box.width != blit_info->src.box.width ||
426 blit_info->dst.box.height != abs(blit_info->src.box.height)) { /* allow y flip for glTexImage2D */
427 DBG("scaling requested: source %dx%d destination %dx%d",
428 blit_info->src.box.width, blit_info->src.box.height,
429 blit_info->dst.box.width, blit_info->dst.box.height);
430 return false;
431 }
432
433 /* No masks - not sure if BLT can copy individual channels */
434 unsigned mask = util_format_get_mask(blit_info->dst.format);
435 if ((blit_info->mask & mask) != mask) {
436 DBG("sub-mask requested: 0x%02x vs format mask 0x%02x", blit_info->mask, mask);
437 return false;
438 }
439
440 /* Only support same format (used tiling/detiling) blits for now.
441 * TODO: figure out which different-format blits are possible and test them
442 * - need to use correct swizzle
443 * - set sRGB bits correctly
444 * - avoid trying to convert between float/int formats?
445 */
446 if (blit_info->src.format != blit_info->dst.format)
447 return false;
448
449 /* try to find a exact format match first */
450 uint32_t format = translate_blt_format(blit_info->dst.format);
451 /* When not resolving MSAA, but only doing a layout conversion, we can get
452 * away with a fallback format of matching size.
453 */
454 if (format == ETNA_NO_MATCH && !downsample_x && !downsample_y)
455 format = etna_compatible_blt_format(blit_info->dst.format);
456 if (format == ETNA_NO_MATCH)
457 return false;
458
459 if (blit_info->scissor_enable ||
460 blit_info->dst.box.depth != blit_info->src.box.depth ||
461 blit_info->dst.box.depth != 1) {
462 return false;
463 }
464
465 struct etna_resource_level *src_lev = &src->levels[blit_info->src.level];
466 struct etna_resource_level *dst_lev = &dst->levels[blit_info->dst.level];
467
468 /* if we asked for in-place resolve, return immediately if ts isn't valid
469 * do this check separately because it applies when compression is used, but
470 * we can't use inplace resolve path with compression
471 */
472 if (src == dst) {
473 assert(!memcmp(&blit_info->src, &blit_info->dst, sizeof(blit_info->src)));
474 if (!etna_resource_level_ts_valid(src_lev)) /* No TS, no worries */
475 return true;
476 }
477
478 /* Flush destination, as the blit will invalidate any pending TS changes. */
479 if (dst != src && etna_resource_level_needs_flush(dst_lev))
480 etna_copy_resource(pctx, &dst->base, &dst->base,
481 blit_info->dst.level, blit_info->dst.level);
482
483 /* Kick off BLT here */
484 if (src == dst && src_lev->ts_compress_fmt < 0) {
485 /* Resolve-in-place */
486 struct blt_inplace_op op = {};
487 size_t tile_size = etna_screen_get_tile_size(ctx->screen, src_lev->ts_mode,
488 src->base.nr_samples > 1);
489
490 op.addr.bo = src->bo;
491 op.addr.offset = src_lev->offset + blit_info->src.box.z * src_lev->layer_stride;
492 op.addr.flags = ETNA_RELOC_READ | ETNA_RELOC_WRITE;
493 op.ts_addr.bo = src->ts_bo;
494 op.ts_addr.offset = src_lev->ts_offset + blit_info->src.box.z * src_lev->ts_layer_stride;
495 op.ts_addr.flags = ETNA_RELOC_READ;
496 op.ts_clear_value[0] = src_lev->clear_value;
497 op.ts_clear_value[1] = src_lev->clear_value >> 32;
498 op.ts_mode = src_lev->ts_mode;
499 op.num_tiles = DIV_ROUND_UP(src_lev->size, tile_size);
500 op.bpp = util_format_get_blocksize(src->base.format);
501
502 etna_set_state(ctx->stream, VIVS_GL_FLUSH_CACHE, 0x00000c23);
503 etna_set_state(ctx->stream, VIVS_TS_FLUSH_CACHE, 0x00000001);
504 emit_blt_inplace(ctx->stream, &op);
505 } else {
506 /* Copy op */
507 struct blt_imgcopy_op op = {};
508
509 op.src.addr.bo = src->bo;
510 op.src.addr.offset = src_lev->offset + blit_info->src.box.z * src_lev->layer_stride;
511 op.src.addr.flags = ETNA_RELOC_READ;
512 op.src.format = format;
513 op.src.stride = src_lev->stride;
514 op.src.tiling = src->layout;
515 op.src.downsample_x = downsample_x;
516 op.src.downsample_y = downsample_y;
517 for (unsigned x=0; x<4; ++x)
518 op.src.swizzle[x] = x;
519
520 if (etna_resource_level_ts_valid(src_lev)) {
521 op.src.use_ts = 1;
522 op.src.ts_addr.bo = src->ts_bo;
523 op.src.ts_addr.offset = src_lev->ts_offset + blit_info->src.box.z * src_lev->ts_layer_stride;
524 op.src.ts_addr.flags = ETNA_RELOC_READ;
525 op.src.ts_clear_value[0] = src_lev->clear_value;
526 op.src.ts_clear_value[1] = src_lev->clear_value >> 32;
527 op.src.ts_mode = src_lev->ts_mode;
528 op.src.ts_compress_fmt = src_lev->ts_compress_fmt;
529 }
530
531 op.dest.addr.bo = dst->bo;
532 op.dest.addr.offset = dst_lev->offset + blit_info->dst.box.z * dst_lev->layer_stride;
533 op.dest.addr.flags = ETNA_RELOC_WRITE;
534 op.dest.format = format;
535 op.dest.stride = dst_lev->stride;
536 op.dest.tiling = dst->layout;
537 for (unsigned x=0; x<4; ++x)
538 op.dest.swizzle[x] = x;
539
540 op.dest_x = blit_info->dst.box.x;
541 op.dest_y = blit_info->dst.box.y;
542 op.src_x = blit_info->src.box.x;
543 op.src_y = blit_info->src.box.y;
544 op.rect_w = blit_info->dst.box.width;
545 op.rect_h = blit_info->dst.box.height;
546
547 assert(op.dest_x < dst_lev->padded_width);
548 assert(op.dest_y < dst_lev->padded_height);
549 assert((op.dest_x + op.rect_w) <= dst_lev->padded_width);
550 assert((op.dest_y + op.rect_h) <= dst_lev->padded_height);
551
552 if (blit_info->src.box.height < 0) { /* flipped? fix up base y */
553 op.flip_y = 1;
554 op.src_y += blit_info->src.box.height;
555 }
556
557 op.src_x *= src_xscale;
558 op.src_y *= src_yscale;
559 op.rect_w *= src_xscale;
560 op.rect_h *= src_yscale;
561
562 assert(op.src_x < src_lev->padded_width);
563 assert(op.src_y < src_lev->padded_height);
564 assert((op.src_x + op.rect_w) <= src_lev->padded_width);
565 assert((op.src_y + op.rect_h) <= src_lev->padded_height);
566
567 etna_set_state(ctx->stream, VIVS_GL_FLUSH_CACHE, 0x00000c23);
568 etna_set_state(ctx->stream, VIVS_TS_FLUSH_CACHE, 0x00000001);
569 emit_blt_copyimage(ctx->stream, &op);
570 }
571
572 /* Make FE wait for BLT, in case we want to do something with the image next.
573 * This probably shouldn't be here, and depend on what is done with the resource.
574 */
575 etna_stall(ctx->stream, SYNC_RECIPIENT_FE, SYNC_RECIPIENT_BLT);
576 etna_set_state(ctx->stream, VIVS_GL_FLUSH_CACHE, 0x00000c23);
577
578 resource_read(ctx, &src->base);
579 resource_written(ctx, &dst->base);
580
581 etna_resource_level_mark_changed(dst_lev);
582
583 /* We don't need to mark the TS as invalid if this was just a flush without
584 * compression, as in that case only clear tiles are filled and the tile
585 * status still matches the blit target buffer. For compressed formats the
586 * tiles are decompressed, so tile status doesn't match anymore.
587 */
588 if (src != dst || src_lev->ts_compress_fmt >= 0)
589 etna_resource_level_ts_mark_invalid(dst_lev);
590
591 return true;
592 }
593
594 void
etna_clear_blit_blt_init(struct pipe_context * pctx)595 etna_clear_blit_blt_init(struct pipe_context *pctx)
596 {
597 struct etna_context *ctx = etna_context(pctx);
598
599 DBG("etnaviv: Using BLT blit engine");
600 pctx->clear = etna_clear_blt;
601 ctx->blit = etna_try_blt_blit;
602 }
603