1 /* 2 * Copyright © 2024 Igalia S.L. 3 * SPDX-License-Identifier: MIT 4 */ 5 6 #include "util/u_math.h" 7 #include "adreno_common.xml.h" 8 #include "adreno_pm4.xml.h" 9 #include "a6xx.xml.h" 10 11 #include "freedreno_perfcntr.h" 12 13 #define REG6(_x) REG_A6XX_##_x 14 #define REG7(_x) REG_A7XX_##_x 15 16 #define FD7_COUNTER(_sel, _offset) COUNTER_BASE(_sel, _offset+0, _offset+1) 17 #define FD7_COUNTABLE(_sel) COUNTABLE_BASE(#_sel, A7XX_##_sel, UINT64, AVERAGE) 18 19 static const struct fd_perfcntr_counter cp_counters[] = { 20 FD7_COUNTER(REG6(CP_PERFCTR_CP_SEL(0)), REG7(RBBM_PERFCTR_CP(0))), 21 FD7_COUNTER(REG6(CP_PERFCTR_CP_SEL(1)), REG7(RBBM_PERFCTR_CP(1))), 22 FD7_COUNTER(REG6(CP_PERFCTR_CP_SEL(2)), REG7(RBBM_PERFCTR_CP(2))), 23 FD7_COUNTER(REG6(CP_PERFCTR_CP_SEL(3)), REG7(RBBM_PERFCTR_CP(3))), 24 FD7_COUNTER(REG6(CP_PERFCTR_CP_SEL(4)), REG7(RBBM_PERFCTR_CP(4))), 25 FD7_COUNTER(REG6(CP_PERFCTR_CP_SEL(5)), REG7(RBBM_PERFCTR_CP(5))), 26 FD7_COUNTER(REG6(CP_PERFCTR_CP_SEL(6)), REG7(RBBM_PERFCTR_CP(6))), 27 FD7_COUNTER(REG6(CP_PERFCTR_CP_SEL(7)), REG7(RBBM_PERFCTR_CP(7))), 28 FD7_COUNTER(REG6(CP_PERFCTR_CP_SEL(8)), REG7(RBBM_PERFCTR_CP(8))), 29 FD7_COUNTER(REG6(CP_PERFCTR_CP_SEL(9)), REG7(RBBM_PERFCTR_CP(9))), 30 FD7_COUNTER(REG6(CP_PERFCTR_CP_SEL(10)), REG7(RBBM_PERFCTR_CP(10))), 31 FD7_COUNTER(REG6(CP_PERFCTR_CP_SEL(11)), REG7(RBBM_PERFCTR_CP(11))), 32 FD7_COUNTER(REG6(CP_PERFCTR_CP_SEL(12)), REG7(RBBM_PERFCTR_CP(12))), 33 FD7_COUNTER(REG6(CP_PERFCTR_CP_SEL(13)), REG7(RBBM_PERFCTR_CP(13))), 34 }; 35 36 static const struct fd_perfcntr_countable cp_countables[] = { 37 FD7_COUNTABLE(PERF_CP_ALWAYS_COUNT), 38 FD7_COUNTABLE(PERF_CP_BUSY_GFX_CORE_IDLE), 39 FD7_COUNTABLE(PERF_CP_BUSY_CYCLES), 40 FD7_COUNTABLE(PERF_CP_NUM_PREEMPTIONS), 41 FD7_COUNTABLE(PERF_CP_PREEMPTION_REACTION_DELAY), 42 FD7_COUNTABLE(PERF_CP_PREEMPTION_SWITCH_OUT_TIME), 43 FD7_COUNTABLE(PERF_CP_PREEMPTION_SWITCH_IN_TIME), 44 FD7_COUNTABLE(PERF_CP_DEAD_DRAWS_IN_BIN_RENDER), 45 FD7_COUNTABLE(PERF_CP_PREDICATED_DRAWS_KILLED), 46 FD7_COUNTABLE(PERF_CP_MODE_SWITCH), 47 FD7_COUNTABLE(PERF_CP_ZPASS_DONE), 48 FD7_COUNTABLE(PERF_CP_CONTEXT_DONE), 49 FD7_COUNTABLE(PERF_CP_CACHE_FLUSH), 50 FD7_COUNTABLE(PERF_CP_LONG_PREEMPTIONS), 51 FD7_COUNTABLE(PERF_CP_SQE_I_CACHE_STARVE), 52 FD7_COUNTABLE(PERF_CP_SQE_IDLE), 53 FD7_COUNTABLE(PERF_CP_SQE_PM4_STARVE_RB_IB), 54 FD7_COUNTABLE(PERF_CP_SQE_PM4_STARVE_SDS), 55 FD7_COUNTABLE(PERF_CP_SQE_MRB_STARVE), 56 FD7_COUNTABLE(PERF_CP_SQE_RRB_STARVE), 57 FD7_COUNTABLE(PERF_CP_SQE_VSD_STARVE), 58 FD7_COUNTABLE(PERF_CP_VSD_DECODE_STARVE), 59 FD7_COUNTABLE(PERF_CP_SQE_PIPE_OUT_STALL), 60 FD7_COUNTABLE(PERF_CP_SQE_SYNC_STALL), 61 FD7_COUNTABLE(PERF_CP_SQE_PM4_WFI_STALL), 62 FD7_COUNTABLE(PERF_CP_SQE_SYS_WFI_STALL), 63 FD7_COUNTABLE(PERF_CP_SQE_T4_EXEC), 64 FD7_COUNTABLE(PERF_CP_SQE_LOAD_STATE_EXEC), 65 FD7_COUNTABLE(PERF_CP_SQE_SAVE_SDS_STATE), 66 FD7_COUNTABLE(PERF_CP_SQE_DRAW_EXEC), 67 FD7_COUNTABLE(PERF_CP_SQE_CTXT_REG_BUNCH_EXEC), 68 FD7_COUNTABLE(PERF_CP_SQE_EXEC_PROFILED), 69 FD7_COUNTABLE(PERF_CP_MEMORY_POOL_EMPTY), 70 FD7_COUNTABLE(PERF_CP_MEMORY_POOL_SYNC_STALL), 71 FD7_COUNTABLE(PERF_CP_MEMORY_POOL_ABOVE_THRESH), 72 FD7_COUNTABLE(PERF_CP_AHB_WR_STALL_PRE_DRAWS), 73 FD7_COUNTABLE(PERF_CP_AHB_STALL_SQE_GMU), 74 FD7_COUNTABLE(PERF_CP_AHB_STALL_SQE_WR_OTHER), 75 FD7_COUNTABLE(PERF_CP_AHB_STALL_SQE_RD_OTHER), 76 FD7_COUNTABLE(PERF_CP_CLUSTER0_EMPTY), 77 FD7_COUNTABLE(PERF_CP_CLUSTER1_EMPTY), 78 FD7_COUNTABLE(PERF_CP_CLUSTER2_EMPTY), 79 FD7_COUNTABLE(PERF_CP_CLUSTER3_EMPTY), 80 FD7_COUNTABLE(PERF_CP_CLUSTER4_EMPTY), 81 FD7_COUNTABLE(PERF_CP_CLUSTER5_EMPTY), 82 FD7_COUNTABLE(PERF_CP_PM4_DATA), 83 FD7_COUNTABLE(PERF_CP_PM4_HEADERS), 84 FD7_COUNTABLE(PERF_CP_VBIF_READ_BEATS), 85 FD7_COUNTABLE(PERF_CP_VBIF_WRITE_BEATS), 86 FD7_COUNTABLE(PERF_CP_SQE_INSTR_COUNTER), 87 FD7_COUNTABLE(PERF_CP_RESERVED_50), 88 FD7_COUNTABLE(PERF_CP_RESERVED_51), 89 FD7_COUNTABLE(PERF_CP_RESERVED_52), 90 FD7_COUNTABLE(PERF_CP_RESERVED_53), 91 FD7_COUNTABLE(PERF_CP_RESERVED_54), 92 FD7_COUNTABLE(PERF_CP_RESERVED_55), 93 FD7_COUNTABLE(PERF_CP_RESERVED_56), 94 FD7_COUNTABLE(PERF_CP_RESERVED_57), 95 FD7_COUNTABLE(PERF_CP_RESERVED_58), 96 FD7_COUNTABLE(PERF_CP_RESERVED_59), 97 FD7_COUNTABLE(PERF_CP_CLUSTER0_FULL), 98 FD7_COUNTABLE(PERF_CP_CLUSTER1_FULL), 99 FD7_COUNTABLE(PERF_CP_CLUSTER2_FULL), 100 FD7_COUNTABLE(PERF_CP_CLUSTER3_FULL), 101 FD7_COUNTABLE(PERF_CP_CLUSTER4_FULL), 102 FD7_COUNTABLE(PERF_CP_CLUSTER5_FULL), 103 FD7_COUNTABLE(PERF_CP_CLUSTER6_FULL), 104 FD7_COUNTABLE(PERF_CP_CLUSTER6_EMPTY), 105 FD7_COUNTABLE(PERF_CP_ICACHE_MISSES), 106 FD7_COUNTABLE(PERF_CP_ICACHE_HITS), 107 FD7_COUNTABLE(PERF_CP_ICACHE_STALL), 108 FD7_COUNTABLE(PERF_CP_DCACHE_MISSES), 109 FD7_COUNTABLE(PERF_CP_DCACHE_HITS), 110 FD7_COUNTABLE(PERF_CP_DCACHE_STALLS), 111 FD7_COUNTABLE(PERF_CP_AQE_SQE_STALL), 112 FD7_COUNTABLE(PERF_CP_SQE_AQE_STARVE), 113 FD7_COUNTABLE(PERF_CP_PREEMPT_LATENCY), 114 FD7_COUNTABLE(PERF_CP_SQE_MD8_STALL_CYCLES), 115 FD7_COUNTABLE(PERF_CP_SQE_MESH_EXEC_CYCLES), 116 FD7_COUNTABLE(PERF_CP_AQE_NUM_AS_CHUNKS), 117 FD7_COUNTABLE(PERF_CP_AQE_NUM_MS_CHUNKS), 118 }; 119 120 static const struct fd_perfcntr_counter rbbm_counters[] = { 121 FD7_COUNTER(REG6(RBBM_PERFCTR_RBBM_SEL(0)), REG7(RBBM_PERFCTR_RBBM(0))), 122 FD7_COUNTER(REG6(RBBM_PERFCTR_RBBM_SEL(1)), REG7(RBBM_PERFCTR_RBBM(1))), 123 FD7_COUNTER(REG6(RBBM_PERFCTR_RBBM_SEL(2)), REG7(RBBM_PERFCTR_RBBM(2))), 124 FD7_COUNTER(REG6(RBBM_PERFCTR_RBBM_SEL(3)), REG7(RBBM_PERFCTR_RBBM(3))), 125 }; 126 127 static const struct fd_perfcntr_countable rbbm_countables[] = { 128 FD7_COUNTABLE(PERF_RBBM_ALWAYS_COUNT), 129 FD7_COUNTABLE(PERF_RBBM_ALWAYS_ON), 130 FD7_COUNTABLE(PERF_RBBM_TSE_BUSY), 131 FD7_COUNTABLE(PERF_RBBM_RAS_BUSY), 132 FD7_COUNTABLE(PERF_RBBM_PC_DCALL_BUSY), 133 FD7_COUNTABLE(PERF_RBBM_PC_VSD_BUSY), 134 FD7_COUNTABLE(PERF_RBBM_STATUS_MASKED), 135 FD7_COUNTABLE(PERF_RBBM_COM_BUSY), 136 FD7_COUNTABLE(PERF_RBBM_DCOM_BUSY), 137 FD7_COUNTABLE(PERF_RBBM_VBIF_BUSY), 138 FD7_COUNTABLE(PERF_RBBM_VSC_BUSY), 139 FD7_COUNTABLE(PERF_RBBM_TESS_BUSY), 140 FD7_COUNTABLE(PERF_RBBM_UCHE_BUSY), 141 FD7_COUNTABLE(PERF_RBBM_HLSQ_BUSY), 142 }; 143 144 static const struct fd_perfcntr_counter pc_counters[] = { 145 FD7_COUNTER(REG7(PC_PERFCTR_PC_SEL(0)), REG7(RBBM_PERFCTR_PC(0))), 146 FD7_COUNTER(REG7(PC_PERFCTR_PC_SEL(1)), REG7(RBBM_PERFCTR_PC(1))), 147 FD7_COUNTER(REG7(PC_PERFCTR_PC_SEL(2)), REG7(RBBM_PERFCTR_PC(2))), 148 FD7_COUNTER(REG7(PC_PERFCTR_PC_SEL(3)), REG7(RBBM_PERFCTR_PC(3))), 149 FD7_COUNTER(REG7(PC_PERFCTR_PC_SEL(4)), REG7(RBBM_PERFCTR_PC(4))), 150 FD7_COUNTER(REG7(PC_PERFCTR_PC_SEL(5)), REG7(RBBM_PERFCTR_PC(5))), 151 FD7_COUNTER(REG7(PC_PERFCTR_PC_SEL(6)), REG7(RBBM_PERFCTR_PC(6))), 152 FD7_COUNTER(REG7(PC_PERFCTR_PC_SEL(7)), REG7(RBBM_PERFCTR_PC(7))), 153 }; 154 155 static const struct fd_perfcntr_countable pc_countables[] = { 156 FD7_COUNTABLE(PERF_PC_BUSY_CYCLES), 157 FD7_COUNTABLE(PERF_PC_WORKING_CYCLES), 158 FD7_COUNTABLE(PERF_PC_STALL_CYCLES_VFD), 159 FD7_COUNTABLE(PERF_PC_RESERVED), 160 FD7_COUNTABLE(PERF_PC_STALL_CYCLES_VPC), 161 FD7_COUNTABLE(PERF_PC_STALL_CYCLES_UCHE), 162 FD7_COUNTABLE(PERF_PC_STALL_CYCLES_TESS), 163 FD7_COUNTABLE(PERF_PC_STALL_CYCLES_VFD_ONLY), 164 FD7_COUNTABLE(PERF_PC_STALL_CYCLES_VPC_ONLY), 165 FD7_COUNTABLE(PERF_PC_PASS1_TF_STALL_CYCLES), 166 FD7_COUNTABLE(PERF_PC_STARVE_CYCLES_FOR_INDEX), 167 FD7_COUNTABLE(PERF_PC_STARVE_CYCLES_FOR_TESS_FACTOR), 168 FD7_COUNTABLE(PERF_PC_STARVE_CYCLES_FOR_VIZ_STREAM), 169 FD7_COUNTABLE(PERF_PC_STARVE_CYCLES_DI), 170 FD7_COUNTABLE(PERF_PC_VIS_STREAMS_LOADED), 171 FD7_COUNTABLE(PERF_PC_INSTANCES), 172 FD7_COUNTABLE(PERF_PC_VPC_PRIMITIVES), 173 FD7_COUNTABLE(PERF_PC_DEAD_PRIM), 174 FD7_COUNTABLE(PERF_PC_LIVE_PRIM), 175 FD7_COUNTABLE(PERF_PC_VERTEX_HITS), 176 FD7_COUNTABLE(PERF_PC_IA_VERTICES), 177 FD7_COUNTABLE(PERF_PC_IA_PRIMITIVES), 178 FD7_COUNTABLE(PERF_PC_RESERVED_22), 179 FD7_COUNTABLE(PERF_PC_HS_INVOCATIONS), 180 FD7_COUNTABLE(PERF_PC_DS_INVOCATIONS), 181 FD7_COUNTABLE(PERF_PC_VS_INVOCATIONS), 182 FD7_COUNTABLE(PERF_PC_GS_INVOCATIONS), 183 FD7_COUNTABLE(PERF_PC_DS_PRIMITIVES), 184 FD7_COUNTABLE(PERF_PC_3D_DRAWCALLS), 185 FD7_COUNTABLE(PERF_PC_2D_DRAWCALLS), 186 FD7_COUNTABLE(PERF_PC_NON_DRAWCALL_GLOBAL_EVENTS), 187 FD7_COUNTABLE(PERF_PC_TESS_BUSY_CYCLES), 188 FD7_COUNTABLE(PERF_PC_TESS_WORKING_CYCLES), 189 FD7_COUNTABLE(PERF_PC_TESS_STALL_CYCLES_PC), 190 FD7_COUNTABLE(PERF_PC_TESS_STARVE_CYCLES_PC), 191 FD7_COUNTABLE(PERF_PC_TESS_SINGLE_PRIM_CYCLES), 192 FD7_COUNTABLE(PERF_PC_TESS_PC_UV_TRANS), 193 FD7_COUNTABLE(PERF_PC_TESS_PC_UV_PATCHES), 194 FD7_COUNTABLE(PERF_PC_TESS_FACTOR_TRANS), 195 FD7_COUNTABLE(PERF_PC_TAG_CHECKED_VERTICES), 196 FD7_COUNTABLE(PERF_PC_MESH_VS_WAVES), 197 FD7_COUNTABLE(PERF_PC_MESH_DRAWS), 198 FD7_COUNTABLE(PERF_PC_MESH_DEAD_DRAWS), 199 FD7_COUNTABLE(PERF_PC_MESH_MVIS_EN_DRAWS), 200 FD7_COUNTABLE(PERF_PC_MESH_DEAD_PRIM), 201 FD7_COUNTABLE(PERF_PC_MESH_LIVE_PRIM), 202 FD7_COUNTABLE(PERF_PC_MESH_PA_EN_PRIM), 203 FD7_COUNTABLE(PERF_PC_STARVE_CYCLES_FOR_MVIS_STREAM), 204 FD7_COUNTABLE(PERF_PC_STARVE_CYCLES_PREDRAW), 205 FD7_COUNTABLE(PERF_PC_STALL_CYCLES_COMPUTE_GFX), 206 FD7_COUNTABLE(PERF_PC_STALL_CYCLES_GFX_COMPUTE), 207 FD7_COUNTABLE(PERF_PC_TESS_PC_MULTI_PATCH_TRANS), 208 }; 209 210 static const struct fd_perfcntr_counter vfd_counters[] = { 211 FD7_COUNTER(REG6(VFD_PERFCTR_VFD_SEL(0)), REG7(RBBM_PERFCTR_VFD(0))), 212 FD7_COUNTER(REG6(VFD_PERFCTR_VFD_SEL(1)), REG7(RBBM_PERFCTR_VFD(1))), 213 FD7_COUNTER(REG6(VFD_PERFCTR_VFD_SEL(2)), REG7(RBBM_PERFCTR_VFD(2))), 214 FD7_COUNTER(REG6(VFD_PERFCTR_VFD_SEL(3)), REG7(RBBM_PERFCTR_VFD(3))), 215 FD7_COUNTER(REG6(VFD_PERFCTR_VFD_SEL(4)), REG7(RBBM_PERFCTR_VFD(4))), 216 FD7_COUNTER(REG6(VFD_PERFCTR_VFD_SEL(5)), REG7(RBBM_PERFCTR_VFD(5))), 217 FD7_COUNTER(REG6(VFD_PERFCTR_VFD_SEL(6)), REG7(RBBM_PERFCTR_VFD(6))), 218 FD7_COUNTER(REG6(VFD_PERFCTR_VFD_SEL(7)), REG7(RBBM_PERFCTR_VFD(7))), 219 }; 220 221 static const struct fd_perfcntr_countable vfd_countables[] = { 222 FD7_COUNTABLE(PERF_VFD_BUSY_CYCLES), 223 FD7_COUNTABLE(PERF_VFD_STALL_CYCLES_UCHE), 224 FD7_COUNTABLE(PERF_VFD_STALL_CYCLES_VPC_ALLOC), 225 FD7_COUNTABLE(PERF_VFD_STALL_CYCLES_SP_INFO), 226 FD7_COUNTABLE(PERF_VFD_STALL_CYCLES_SP_ATTR), 227 FD7_COUNTABLE(PERF_VFD_STARVE_CYCLES_UCHE), 228 FD7_COUNTABLE(PERF_VFD_RBUFFER_FULL), 229 FD7_COUNTABLE(PERF_VFD_ATTR_INFO_FIFO_FULL), 230 FD7_COUNTABLE(PERF_VFD_DECODED_ATTRIBUTE_BYTES), 231 FD7_COUNTABLE(PERF_VFD_NUM_ATTRIBUTES), 232 FD7_COUNTABLE(PERF_VFD_UPPER_SHADER_FIBERS), 233 FD7_COUNTABLE(PERF_VFD_LOWER_SHADER_FIBERS), 234 FD7_COUNTABLE(PERF_VFD_MODE_0_FIBERS), 235 FD7_COUNTABLE(PERF_VFD_MODE_1_FIBERS), 236 FD7_COUNTABLE(PERF_VFD_MODE_2_FIBERS), 237 FD7_COUNTABLE(PERF_VFD_MODE_3_FIBERS), 238 FD7_COUNTABLE(PERF_VFD_MODE_4_FIBERS), 239 FD7_COUNTABLE(PERF_VFD_TOTAL_VERTICES), 240 FD7_COUNTABLE(PERF_VFDP_STALL_CYCLES_VFD), 241 FD7_COUNTABLE(PERF_VFDP_STALL_CYCLES_VFD_INDEX), 242 FD7_COUNTABLE(PERF_VFDP_STALL_CYCLES_VFD_PROG), 243 FD7_COUNTABLE(PERF_VFDP_STARVE_CYCLES_PC), 244 FD7_COUNTABLE(PERF_VFDP_VS_STAGE_WAVES), 245 FD7_COUNTABLE(PERF_VFD_STALL_CYCLES_PRG_END_FE), 246 FD7_COUNTABLE(PERF_VFD_STALL_CYCLES_CBSYNC), 247 }; 248 249 static const struct fd_perfcntr_counter hlsq_counters[] = { 250 FD7_COUNTER(REG7(SP_PERFCTR_HLSQ_SEL(0)), REG7(RBBM_PERFCTR_HLSQ(0))), 251 FD7_COUNTER(REG7(SP_PERFCTR_HLSQ_SEL(1)), REG7(RBBM_PERFCTR_HLSQ(1))), 252 FD7_COUNTER(REG7(SP_PERFCTR_HLSQ_SEL(2)), REG7(RBBM_PERFCTR_HLSQ(2))), 253 FD7_COUNTER(REG7(SP_PERFCTR_HLSQ_SEL(3)), REG7(RBBM_PERFCTR_HLSQ(3))), 254 FD7_COUNTER(REG7(SP_PERFCTR_HLSQ_SEL(4)), REG7(RBBM_PERFCTR_HLSQ(4))), 255 FD7_COUNTER(REG7(SP_PERFCTR_HLSQ_SEL(5)), REG7(RBBM_PERFCTR_HLSQ(5))), 256 }; 257 258 static const struct fd_perfcntr_countable hlsq_countables[] = { 259 FD7_COUNTABLE(PERF_HLSQ_BUSY_CYCLES), 260 FD7_COUNTABLE(PERF_HLSQ_STALL_CYCLES_UCHE), 261 FD7_COUNTABLE(PERF_HLSQ_STALL_CYCLES_SP_STATE), 262 FD7_COUNTABLE(PERF_HLSQ_STALL_CYCLES_SP_FS_STAGE), 263 FD7_COUNTABLE(PERF_HLSQ_UCHE_LATENCY_CYCLES), 264 FD7_COUNTABLE(PERF_HLSQ_UCHE_LATENCY_COUNT), 265 FD7_COUNTABLE(PERF_HLSQ_RESERVED_6), 266 FD7_COUNTABLE(PERF_HLSQ_RESERVED_7), 267 FD7_COUNTABLE(PERF_HLSQ_RESERVED_8), 268 FD7_COUNTABLE(PERF_HLSQ_RESERVED_9), 269 FD7_COUNTABLE(PERF_HLSQ_COMPUTE_DRAWCALLS), 270 FD7_COUNTABLE(PERF_HLSQ_FS_DATA_WAIT_PROGRAMMING), 271 FD7_COUNTABLE(PERF_HLSQ_DUAL_FS_PROG_ACTIVE), 272 FD7_COUNTABLE(PERF_HLSQ_DUAL_VS_PROG_ACTIVE), 273 FD7_COUNTABLE(PERF_HLSQ_FS_BATCH_COUNT_ZERO), 274 FD7_COUNTABLE(PERF_HLSQ_VS_BATCH_COUNT_ZERO), 275 FD7_COUNTABLE(PERF_HLSQ_WAVE_PENDING_NO_QUAD), 276 FD7_COUNTABLE(PERF_HLSQ_WAVE_PENDING_NO_PRIM_BASE), 277 FD7_COUNTABLE(PERF_HLSQ_STALL_CYCLES_VPC), 278 FD7_COUNTABLE(PERF_HLSQ_RESERVED_19), 279 FD7_COUNTABLE(PERF_HLSQ_DRAW_MODE_SWITCH_VSFS_SYNC), 280 FD7_COUNTABLE(PERF_HLSQ_VSBR_STALL_CYCLES), 281 FD7_COUNTABLE(PERF_HLSQ_FS_STALL_CYCLES), 282 FD7_COUNTABLE(PERF_HLSQ_LPAC_STALL_CYCLES), 283 FD7_COUNTABLE(PERF_HLSQ_BV_STALL_CYCLES), 284 FD7_COUNTABLE(PERF_HLSQ_VSBR_DEREF_CYCLES), 285 FD7_COUNTABLE(PERF_HLSQ_FS_DEREF_CYCLES), 286 FD7_COUNTABLE(PERF_HLSQ_LPAC_DEREF_CYCLES), 287 FD7_COUNTABLE(PERF_HLSQ_BV_DEREF_CYCLES), 288 FD7_COUNTABLE(PERF_HLSQ_VSBR_S2W_CYCLES), 289 FD7_COUNTABLE(PERF_HLSQ_FS_S2W_CYCLES), 290 FD7_COUNTABLE(PERF_HLSQ_LPAC_S2W_CYCLES), 291 FD7_COUNTABLE(PERF_HLSQ_BV_S2W_CYCLES), 292 FD7_COUNTABLE(PERF_HLSQ_VSBR_WAIT_FS_S2W), 293 FD7_COUNTABLE(PERF_HLSQ_FS_WAIT_VS_S2W), 294 FD7_COUNTABLE(PERF_HLSQ_LPAC_WAIT_VS_S2W), 295 FD7_COUNTABLE(PERF_HLSQ_BV_WAIT_FS_S2W), 296 FD7_COUNTABLE(PERF_HLSQ_VS_WAIT_CONST_RESOURCE), 297 FD7_COUNTABLE(PERF_HLSQ_FS_WAIT_SAME_VS_S2W), 298 FD7_COUNTABLE(PERF_HLSQ_FS_STARVING_SP), 299 FD7_COUNTABLE(PERF_HLSQ_VS_DATA_WAIT_PROGRAMMING), 300 FD7_COUNTABLE(PERF_HLSQ_BV_DATA_WAIT_PROGRAMMING), 301 FD7_COUNTABLE(PERF_HLSQ_STPROC_WAVE_CONTEXTS_VS), 302 FD7_COUNTABLE(PERF_HLSQ_STPROC_WAVE_CONTEXT_CYCLES_VS), 303 FD7_COUNTABLE(PERF_HLSQ_STPROC_WAVE_CONTEXTS_FS), 304 FD7_COUNTABLE(PERF_HLSQ_STPROC_WAVE_CONTEXT_CYCLES_FS), 305 FD7_COUNTABLE(PERF_HLSQ_STPROC_WAVE_CONTEXTS_BV), 306 FD7_COUNTABLE(PERF_HLSQ_STPROC_WAVE_CONTEXT_CYCLES_BV), 307 FD7_COUNTABLE(PERF_HLSQ_STPROC_WAVE_CONTEXTS_LPAC), 308 FD7_COUNTABLE(PERF_HLSQ_STPROC_WAVE_CONTEXT_CYCLES_LPAC), 309 FD7_COUNTABLE(PERF_HLSQ_SPTROC_STCHE_WARMUP_INC_VS), 310 FD7_COUNTABLE(PERF_HLSQ_SPTROC_STCHE_WARMUP_INC_FS), 311 FD7_COUNTABLE(PERF_HLSQ_SPTROC_STCHE_WARMUP_INC_BV), 312 FD7_COUNTABLE(PERF_HLSQ_SPTROC_STCHE_WARMUP_INC_LPAC), 313 FD7_COUNTABLE(PERF_HLSQ_SPTROC_STCHE_MISS_INC_VS), 314 FD7_COUNTABLE(PERF_HLSQ_SPTROC_STCHE_MISS_INC_FS), 315 FD7_COUNTABLE(PERF_HLSQ_SPTROC_STCHE_MISS_INC_BV), 316 FD7_COUNTABLE(PERF_HLSQ_SPTROC_STCHE_MISS_INC_LPAC), 317 }; 318 319 static const struct fd_perfcntr_counter vpc_counters[] = { 320 FD7_COUNTER(REG7(VPC_PERFCTR_VPC_SEL(0)), REG7(RBBM_PERFCTR_VPC(0))), 321 FD7_COUNTER(REG7(VPC_PERFCTR_VPC_SEL(1)), REG7(RBBM_PERFCTR_VPC(1))), 322 FD7_COUNTER(REG7(VPC_PERFCTR_VPC_SEL(2)), REG7(RBBM_PERFCTR_VPC(2))), 323 FD7_COUNTER(REG7(VPC_PERFCTR_VPC_SEL(3)), REG7(RBBM_PERFCTR_VPC(3))), 324 FD7_COUNTER(REG7(VPC_PERFCTR_VPC_SEL(4)), REG7(RBBM_PERFCTR_VPC(4))), 325 FD7_COUNTER(REG7(VPC_PERFCTR_VPC_SEL(5)), REG7(RBBM_PERFCTR_VPC(5))), 326 }; 327 328 static const struct fd_perfcntr_countable vpc_countables[] = { 329 FD7_COUNTABLE(PERF_VPC_BUSY_CYCLES), 330 FD7_COUNTABLE(PERF_VPC_WORKING_CYCLES), 331 FD7_COUNTABLE(PERF_VPC_STALL_CYCLES_UCHE), 332 FD7_COUNTABLE(PERF_VPC_STALL_CYCLES_VFD_WACK), 333 FD7_COUNTABLE(PERF_VPC_STALL_CYCLES_HLSQ_PRIM_ALLOC), 334 FD7_COUNTABLE(PERF_VPC_RESERVED_5), 335 FD7_COUNTABLE(PERF_VPC_STALL_CYCLES_SP_LM), 336 FD7_COUNTABLE(PERF_VPC_STARVE_CYCLES_SP), 337 FD7_COUNTABLE(PERF_VPC_STARVE_CYCLES_LRZ), 338 FD7_COUNTABLE(PERF_VPC_PC_PRIMITIVES), 339 FD7_COUNTABLE(PERF_VPC_SP_COMPONENTS), 340 FD7_COUNTABLE(PERF_VPC_STALL_CYCLES_VPCRAM_POS), 341 FD7_COUNTABLE(PERF_VPC_LRZ_ASSIGN_PRIMITIVES), 342 FD7_COUNTABLE(PERF_VPC_RB_VISIBLE_PRIMITIVES), 343 FD7_COUNTABLE(PERF_VPC_LM_TRANSACTION), 344 FD7_COUNTABLE(PERF_VPC_STREAMOUT_TRANSACTION), 345 FD7_COUNTABLE(PERF_VPC_VS_BUSY_CYCLES), 346 FD7_COUNTABLE(PERF_VPC_PS_BUSY_CYCLES), 347 FD7_COUNTABLE(PERF_VPC_VS_WORKING_CYCLES), 348 FD7_COUNTABLE(PERF_VPC_PS_WORKING_CYCLES), 349 FD7_COUNTABLE(PERF_VPC_STARVE_CYCLES_RB), 350 FD7_COUNTABLE(PERF_VPC_NUM_VPCRAM_READ_POS), 351 FD7_COUNTABLE(PERF_VPC_WIT_FULL_CYCLES), 352 FD7_COUNTABLE(PERF_VPC_VPCRAM_FULL_CYCLES), 353 FD7_COUNTABLE(PERF_VPC_LM_FULL_WAIT_FOR_INTP_END), 354 FD7_COUNTABLE(PERF_VPC_NUM_VPCRAM_WRITE), 355 FD7_COUNTABLE(PERF_VPC_NUM_VPCRAM_READ_SO), 356 FD7_COUNTABLE(PERF_VPC_NUM_ATTR_REQ_LM), 357 FD7_COUNTABLE(PERF_VPC_STALL_CYCLE_TSE), 358 FD7_COUNTABLE(PERF_VPC_TSE_PRIMITIVES), 359 FD7_COUNTABLE(PERF_VPC_GS_PRIMITIVES), 360 FD7_COUNTABLE(PERF_VPC_TSE_TRANSACTIONS), 361 FD7_COUNTABLE(PERF_VPC_STALL_CYCLES_CCU), 362 FD7_COUNTABLE(PERF_VPC_NUM_WM_HIT), 363 FD7_COUNTABLE(PERF_VPC_STALL_DQ_WACK), 364 FD7_COUNTABLE(PERF_VPC_STALL_CYCLES_CCHE), 365 FD7_COUNTABLE(PERF_VPC_STARVE_CYCLES_CCHE), 366 FD7_COUNTABLE(PERF_VPC_NUM_PA_REQ), 367 FD7_COUNTABLE(PERF_VPC_NUM_LM_REQ_HIT), 368 FD7_COUNTABLE(PERF_VPC_CCHE_REQBUF_FULL), 369 FD7_COUNTABLE(PERF_VPC_STALL_CYCLES_LM_ACK), 370 FD7_COUNTABLE(PERF_VPC_STALL_CYCLES_PRG_END_FE), 371 FD7_COUNTABLE(PERF_VPC_STALL_CYCLES_PRG_END_PCVS), 372 FD7_COUNTABLE(PERF_VPC_STALL_CYCLES_PRG_END_VPCPS), 373 }; 374 375 static const struct fd_perfcntr_counter tse_counters[] = { 376 FD7_COUNTER(REG6(GRAS_PERFCTR_TSE_SEL(0)), REG7(RBBM_PERFCTR_TSE(0))), 377 FD7_COUNTER(REG6(GRAS_PERFCTR_TSE_SEL(1)), REG7(RBBM_PERFCTR_TSE(1))), 378 FD7_COUNTER(REG6(GRAS_PERFCTR_TSE_SEL(2)), REG7(RBBM_PERFCTR_TSE(2))), 379 FD7_COUNTER(REG6(GRAS_PERFCTR_TSE_SEL(3)), REG7(RBBM_PERFCTR_TSE(3))), 380 }; 381 382 static const struct fd_perfcntr_countable tse_countables[] = { 383 FD7_COUNTABLE(PERF_TSE_BUSY_CYCLES), 384 FD7_COUNTABLE(PERF_TSE_CLIPPING_CYCLES), 385 FD7_COUNTABLE(PERF_TSE_STALL_CYCLES_RAS), 386 FD7_COUNTABLE(PERF_TSE_STALL_CYCLES_LRZ_BARYPLANE), 387 FD7_COUNTABLE(PERF_TSE_STALL_CYCLES_LRZ_ZPLANE), 388 FD7_COUNTABLE(PERF_TSE_STARVE_CYCLES_PC), 389 FD7_COUNTABLE(PERF_TSE_INPUT_PRIM), 390 FD7_COUNTABLE(PERF_TSE_INPUT_NULL_PRIM), 391 FD7_COUNTABLE(PERF_TSE_TRIVAL_REJ_PRIM), 392 FD7_COUNTABLE(PERF_TSE_CLIPPED_PRIM), 393 FD7_COUNTABLE(PERF_TSE_ZERO_AREA_PRIM), 394 FD7_COUNTABLE(PERF_TSE_FACENESS_CULLED_PRIM), 395 FD7_COUNTABLE(PERF_TSE_ZERO_PIXEL_PRIM), 396 FD7_COUNTABLE(PERF_TSE_OUTPUT_NULL_PRIM), 397 FD7_COUNTABLE(PERF_TSE_OUTPUT_VISIBLE_PRIM), 398 FD7_COUNTABLE(PERF_TSE_CINVOCATION), 399 FD7_COUNTABLE(PERF_TSE_CPRIMITIVES), 400 FD7_COUNTABLE(PERF_TSE_2D_INPUT_PRIM), 401 FD7_COUNTABLE(PERF_TSE_2D_ALIVE_CYCLES), 402 FD7_COUNTABLE(PERF_TSE_CLIP_PLANES), 403 }; 404 405 static const struct fd_perfcntr_counter ras_counters[] = { 406 FD7_COUNTER(REG6(GRAS_PERFCTR_RAS_SEL(0)), REG7(RBBM_PERFCTR_RAS(0))), 407 FD7_COUNTER(REG6(GRAS_PERFCTR_RAS_SEL(1)), REG7(RBBM_PERFCTR_RAS(1))), 408 FD7_COUNTER(REG6(GRAS_PERFCTR_RAS_SEL(2)), REG7(RBBM_PERFCTR_RAS(2))), 409 FD7_COUNTER(REG6(GRAS_PERFCTR_RAS_SEL(3)), REG7(RBBM_PERFCTR_RAS(3))), 410 }; 411 412 static const struct fd_perfcntr_countable ras_countables[] = { 413 FD7_COUNTABLE(PERF_RAS_BUSY_CYCLES), 414 FD7_COUNTABLE(PERF_RAS_SUPERTILE_ACTIVE_CYCLES), 415 FD7_COUNTABLE(PERF_RAS_STALL_CYCLES_LRZ), 416 FD7_COUNTABLE(PERF_RAS_STARVE_CYCLES_TSE), 417 FD7_COUNTABLE(PERF_RAS_SUPER_TILES), 418 FD7_COUNTABLE(PERF_RAS_8X4_TILES), 419 FD7_COUNTABLE(PERF_RAS_MASKGEN_ACTIVE), 420 FD7_COUNTABLE(PERF_RAS_FULLY_COVERED_SUPER_TILES), 421 FD7_COUNTABLE(PERF_RAS_FULLY_COVERED_8X4_TILES), 422 FD7_COUNTABLE(PERF_RAS_PRIM_KILLED_INVISILBE), 423 FD7_COUNTABLE(PERF_RAS_SUPERTILE_GEN_ACTIVE_CYCLES), 424 FD7_COUNTABLE(PERF_RAS_LRZ_INTF_WORKING_CYCLES), 425 FD7_COUNTABLE(PERF_RAS_BLOCKS), 426 FD7_COUNTABLE(PERF_RAS_SAMPLE_MASK_GEN_LANE_0_WORKING_CC_l2), 427 FD7_COUNTABLE(PERF_RAS_SAMPLE_MASK_GEN_LANE_1_WORKING_CC_l2), 428 FD7_COUNTABLE(PERF_RAS_SAMPLE_MASK_GEN_LANE_2_WORKING_CC_l2), 429 FD7_COUNTABLE(PERF_RAS_SAMPLE_MASK_GEN_LANE_3_WORKING_CC_l2), 430 FD7_COUNTABLE(PERF_RAS_SAMPLE_MASK_GEN_LANE_4_WORKING_CC_l2), 431 FD7_COUNTABLE(PERF_RAS_SAMPLE_MASK_GEN_LANE_5_WORKING_CC_l2), 432 FD7_COUNTABLE(PERF_RAS_SAMPLE_MASK_GEN_LANE_6_WORKING_CC_l2), 433 FD7_COUNTABLE(PERF_RAS_SAMPLE_MASK_GEN_LANE_7_WORKING_CC_l2), 434 FD7_COUNTABLE(PERF_RAS_SAMPLE_MASK_GEN_LANE_8_WORKING_CC_l2), 435 FD7_COUNTABLE(PERF_RAS_SAMPLE_MASK_GEN_LANE_9_WORKING_CC_l2), 436 FD7_COUNTABLE(PERF_RAS_SAMPLE_MASK_GEN_LANE_10_WORKING_CC_l2), 437 FD7_COUNTABLE(PERF_RAS_SAMPLE_MASK_GEN_LANE_11_WORKING_CC_l2), 438 FD7_COUNTABLE(PERF_RAS_SAMPLE_MASK_GEN_LANE_12_WORKING_CC_l2), 439 FD7_COUNTABLE(PERF_RAS_SAMPLE_MASK_GEN_LANE_13_WORKING_CC_l2), 440 FD7_COUNTABLE(PERF_RAS_SAMPLE_MASK_GEN_LANE_14_WORKING_CC_l2), 441 FD7_COUNTABLE(PERF_RAS_SAMPLE_MASK_GEN_LANE_15_WORKING_CC_l2), 442 FD7_COUNTABLE(PERF_RAS_FALSE_PARTIAL_STILE), 443 }; 444 445 static const struct fd_perfcntr_counter uche_counters[] = { 446 FD7_COUNTER(REG6(UCHE_PERFCTR_UCHE_SEL(0)), REG7(RBBM_PERFCTR_UCHE(0))), 447 FD7_COUNTER(REG6(UCHE_PERFCTR_UCHE_SEL(1)), REG7(RBBM_PERFCTR_UCHE(1))), 448 FD7_COUNTER(REG6(UCHE_PERFCTR_UCHE_SEL(2)), REG7(RBBM_PERFCTR_UCHE(2))), 449 FD7_COUNTER(REG6(UCHE_PERFCTR_UCHE_SEL(3)), REG7(RBBM_PERFCTR_UCHE(3))), 450 FD7_COUNTER(REG6(UCHE_PERFCTR_UCHE_SEL(4)), REG7(RBBM_PERFCTR_UCHE(4))), 451 FD7_COUNTER(REG6(UCHE_PERFCTR_UCHE_SEL(5)), REG7(RBBM_PERFCTR_UCHE(5))), 452 FD7_COUNTER(REG6(UCHE_PERFCTR_UCHE_SEL(6)), REG7(RBBM_PERFCTR_UCHE(6))), 453 FD7_COUNTER(REG6(UCHE_PERFCTR_UCHE_SEL(7)), REG7(RBBM_PERFCTR_UCHE(7))), 454 FD7_COUNTER(REG6(UCHE_PERFCTR_UCHE_SEL(8)), REG7(RBBM_PERFCTR_UCHE(8))), 455 FD7_COUNTER(REG6(UCHE_PERFCTR_UCHE_SEL(9)), REG7(RBBM_PERFCTR_UCHE(9))), 456 FD7_COUNTER(REG6(UCHE_PERFCTR_UCHE_SEL(10)), REG7(RBBM_PERFCTR_UCHE(10))), 457 FD7_COUNTER(REG6(UCHE_PERFCTR_UCHE_SEL(11)), REG7(RBBM_PERFCTR_UCHE(11))), 458 }; 459 460 static const struct fd_perfcntr_countable uche_countables[] = { 461 FD7_COUNTABLE(PERF_UCHE_BUSY_CYCLES), 462 FD7_COUNTABLE(PERF_UCHE_STALL_CYCLES_ARBITER), 463 FD7_COUNTABLE(PERF_UCHE_VBIF_LATENCY_CYCLES), 464 FD7_COUNTABLE(PERF_UCHE_VBIF_LATENCY_SAMPLES), 465 FD7_COUNTABLE(PERF_UCHE_VBIF_READ_BEATS_TP), 466 FD7_COUNTABLE(PERF_UCHE_VBIF_READ_BEATS_VFD), 467 FD7_COUNTABLE(PERF_UCHE_VBIF_READ_BEATS_HLSQ), 468 FD7_COUNTABLE(PERF_UCHE_VBIF_READ_BEATS_LRZ), 469 FD7_COUNTABLE(PERF_UCHE_VBIF_READ_BEATS_SP), 470 FD7_COUNTABLE(PERF_UCHE_READ_REQUESTS_TP), 471 FD7_COUNTABLE(PERF_UCHE_READ_REQUESTS_VFD), 472 FD7_COUNTABLE(PERF_UCHE_READ_REQUESTS_HLSQ), 473 FD7_COUNTABLE(PERF_UCHE_READ_REQUESTS_LRZ), 474 FD7_COUNTABLE(PERF_UCHE_READ_REQUESTS_SP), 475 FD7_COUNTABLE(PERF_UCHE_WRITE_REQUESTS_LRZ), 476 FD7_COUNTABLE(PERF_UCHE_WRITE_REQUESTS_SP), 477 FD7_COUNTABLE(PERF_UCHE_WRITE_REQUESTS_VPC), 478 FD7_COUNTABLE(PERF_UCHE_WRITE_REQUESTS_VSC), 479 FD7_COUNTABLE(PERF_UCHE_EVICTS), 480 FD7_COUNTABLE(PERF_UCHE_BANK_REQ0), 481 FD7_COUNTABLE(PERF_UCHE_BANK_REQ1), 482 FD7_COUNTABLE(PERF_UCHE_BANK_REQ2), 483 FD7_COUNTABLE(PERF_UCHE_BANK_REQ3), 484 FD7_COUNTABLE(PERF_UCHE_BANK_REQ4), 485 FD7_COUNTABLE(PERF_UCHE_BANK_REQ5), 486 FD7_COUNTABLE(PERF_UCHE_BANK_REQ6), 487 FD7_COUNTABLE(PERF_UCHE_BANK_REQ7), 488 FD7_COUNTABLE(PERF_UCHE_VBIF_READ_BEATS_CH0), 489 FD7_COUNTABLE(PERF_UCHE_VBIF_READ_BEATS_CH1), 490 FD7_COUNTABLE(PERF_UCHE_GMEM_READ_BEATS), 491 FD7_COUNTABLE(PERF_UCHE_TPH_REF_FULL), 492 FD7_COUNTABLE(PERF_UCHE_TPH_VICTIM_FULL), 493 FD7_COUNTABLE(PERF_UCHE_TPH_EXT_FULL), 494 FD7_COUNTABLE(PERF_UCHE_VBIF_STALL_WRITE_DATA), 495 FD7_COUNTABLE(PERF_UCHE_DCMP_LATENCY_SAMPLES), 496 FD7_COUNTABLE(PERF_UCHE_DCMP_LATENCY_CYCLES), 497 FD7_COUNTABLE(PERF_UCHE_VBIF_READ_BEATS_PC), 498 FD7_COUNTABLE(PERF_UCHE_READ_REQUESTS_PC), 499 FD7_COUNTABLE(PERF_UCHE_RAM_READ_REQ), 500 FD7_COUNTABLE(PERF_UCHE_RAM_WRITE_REQ), 501 FD7_COUNTABLE(PERF_UCHE_STARVED_CYCLES_VBIF_DECMP), 502 FD7_COUNTABLE(PERF_UCHE_STALL_CYCLES_DECMP), 503 FD7_COUNTABLE(PERF_UCHE_ARBITER_STALL_CYCLES_VBIF), 504 FD7_COUNTABLE(PERF_UCHE_READ_REQUESTS_TP_UBWC), 505 FD7_COUNTABLE(PERF_UCHE_READ_REQUESTS_TP_NONUBWC), 506 FD7_COUNTABLE(PERF_UCHE_READ_REQUESTS_TP_GMEM), 507 FD7_COUNTABLE(PERF_UCHE_LONG_LINE_ALL_EVICTS_KAILUA), 508 FD7_COUNTABLE(PERF_UCHE_LONG_LINE_PARTIAL_EVICTS_KAILUA), 509 FD7_COUNTABLE(PERF_UCHE_TPH_CONFLICT_CL_CCHE), 510 FD7_COUNTABLE(PERF_UCHE_TPH_CONFLICT_CL_OTHER_KAILUA), 511 FD7_COUNTABLE(PERF_UCHE_DBANK_CONFLICT_CL_CCHE), 512 FD7_COUNTABLE(PERF_UCHE_DBANK_CONFLICT_CL_OTHER_CLIENTS), 513 FD7_COUNTABLE(PERF_UCHE_VBIF_WRITE_BEATS_CH0), 514 FD7_COUNTABLE(PERF_UCHE_VBIF_WRITE_BEATS_CH1), 515 FD7_COUNTABLE(PERF_UCHE_CCHE_TPH_QUEUE_FULL), 516 FD7_COUNTABLE(PERF_UCHE_CCHE_DPH_QUEUE_FULL), 517 FD7_COUNTABLE(PERF_UCHE_GMEM_WRITE_BEATS), 518 FD7_COUNTABLE(PERF_UCHE_UBWC_READ_BEATS), 519 FD7_COUNTABLE(PERF_UCHE_UBWC_WRITE_BEATS), 520 }; 521 522 static const struct fd_perfcntr_counter tp_counters[] = { 523 FD7_COUNTER(REG7(TPL1_PERFCTR_TP_SEL(0)), REG7(RBBM_PERFCTR_TP(0))), 524 FD7_COUNTER(REG7(TPL1_PERFCTR_TP_SEL(1)), REG7(RBBM_PERFCTR_TP(1))), 525 FD7_COUNTER(REG7(TPL1_PERFCTR_TP_SEL(2)), REG7(RBBM_PERFCTR_TP(2))), 526 FD7_COUNTER(REG7(TPL1_PERFCTR_TP_SEL(3)), REG7(RBBM_PERFCTR_TP(3))), 527 FD7_COUNTER(REG7(TPL1_PERFCTR_TP_SEL(4)), REG7(RBBM_PERFCTR_TP(4))), 528 FD7_COUNTER(REG7(TPL1_PERFCTR_TP_SEL(5)), REG7(RBBM_PERFCTR_TP(5))), 529 FD7_COUNTER(REG7(TPL1_PERFCTR_TP_SEL(6)), REG7(RBBM_PERFCTR_TP(6))), 530 FD7_COUNTER(REG7(TPL1_PERFCTR_TP_SEL(7)), REG7(RBBM_PERFCTR_TP(7))), 531 FD7_COUNTER(REG7(TPL1_PERFCTR_TP_SEL(8)), REG7(RBBM_PERFCTR_TP(8))), 532 FD7_COUNTER(REG7(TPL1_PERFCTR_TP_SEL(9)), REG7(RBBM_PERFCTR_TP(9))), 533 FD7_COUNTER(REG7(TPL1_PERFCTR_TP_SEL(10)), REG7(RBBM_PERFCTR_TP(10))), 534 FD7_COUNTER(REG7(TPL1_PERFCTR_TP_SEL(11)), REG7(RBBM_PERFCTR_TP(11))), 535 }; 536 537 static const struct fd_perfcntr_countable tp_countables[] = { 538 FD7_COUNTABLE(PERF_TP_BUSY_CYCLES), 539 FD7_COUNTABLE(PERF_TP_STALL_CYCLES_UCHE), 540 FD7_COUNTABLE(PERF_TP_LATENCY_CYCLES), 541 FD7_COUNTABLE(PERF_TP_LATENCY_TRANS), 542 FD7_COUNTABLE(PERF_TP_FLAG_FIFO_DELAY_SAMPLES), 543 FD7_COUNTABLE(PERF_TP_FLAG_FIFO_DELAY_CYCLES), 544 FD7_COUNTABLE(PERF_TP_L1_CACHELINE_REQUESTS), 545 FD7_COUNTABLE(PERF_TP_L1_CACHELINE_MISSES), 546 FD7_COUNTABLE(PERF_TP_SP_TP_TRANS), 547 FD7_COUNTABLE(PERF_TP_TP_SP_TRANS), 548 FD7_COUNTABLE(PERF_TP_OUTPUT_PIXELS), 549 FD7_COUNTABLE(PERF_TP_FILTER_WORKLOAD_16BIT), 550 FD7_COUNTABLE(PERF_TP_FILTER_WORKLOAD_32BIT), 551 FD7_COUNTABLE(PERF_TP_QUADS_RECEIVED), 552 FD7_COUNTABLE(PERF_TP_QUADS_OFFSET), 553 FD7_COUNTABLE(PERF_TP_QUADS_SHADOW), 554 FD7_COUNTABLE(PERF_TP_QUADS_ARRAY), 555 FD7_COUNTABLE(PERF_TP_QUADS_GRADIENT), 556 FD7_COUNTABLE(PERF_TP_QUADS_1D), 557 FD7_COUNTABLE(PERF_TP_QUADS_2D), 558 FD7_COUNTABLE(PERF_TP_QUADS_BUFFER), 559 FD7_COUNTABLE(PERF_TP_QUADS_3D), 560 FD7_COUNTABLE(PERF_TP_QUADS_CUBE), 561 FD7_COUNTABLE(PERF_TP_DIVERGENT_QUADS_RECEIVED), 562 FD7_COUNTABLE(PERF_TP_PRT_NON_RESIDENT_EVENTS), 563 FD7_COUNTABLE(PERF_TP_OUTPUT_PIXELS_POINT), 564 FD7_COUNTABLE(PERF_TP_OUTPUT_PIXELS_BILINEAR), 565 FD7_COUNTABLE(PERF_TP_OUTPUT_PIXELS_MIP), 566 FD7_COUNTABLE(PERF_TP_OUTPUT_PIXELS_ANISO), 567 FD7_COUNTABLE(PERF_TP_OUTPUT_PIXELS_ZERO_LOD), 568 FD7_COUNTABLE(PERF_TP_FLAG_CACHE_REQUESTS), 569 FD7_COUNTABLE(PERF_TP_FLAG_CACHE_MISSES), 570 FD7_COUNTABLE(PERF_TP_L1_5_L2_REQUESTS), 571 FD7_COUNTABLE(PERF_TP_2D_OUTPUT_PIXELS), 572 FD7_COUNTABLE(PERF_TP_2D_OUTPUT_PIXELS_POINT), 573 FD7_COUNTABLE(PERF_TP_2D_OUTPUT_PIXELS_BILINEAR), 574 FD7_COUNTABLE(PERF_TP_2D_FILTER_WORKLOAD_16BIT), 575 FD7_COUNTABLE(PERF_TP_2D_FILTER_WORKLOAD_32BIT), 576 FD7_COUNTABLE(PERF_TP_TPA2TPC_TRANS), 577 FD7_COUNTABLE(PERF_TP_L1_MISSES_ASTC_1TILE), 578 FD7_COUNTABLE(PERF_TP_L1_MISSES_ASTC_2TILE), 579 FD7_COUNTABLE(PERF_TP_L1_MISSES_ASTC_4TILE), 580 FD7_COUNTABLE(PERF_TP_L1_5_COMPRESS_REQS), 581 FD7_COUNTABLE(PERF_TP_L1_5_L2_COMPRESS_MISS), 582 FD7_COUNTABLE(PERF_TP_L1_BANK_CONFLICT), 583 FD7_COUNTABLE(PERF_TP_L1_5_MISS_LATENCY_CYCLES), 584 FD7_COUNTABLE(PERF_TP_L1_5_MISS_LATENCY_TRANS), 585 FD7_COUNTABLE(PERF_TP_QUADS_CONSTANT_MULTIPLIED), 586 FD7_COUNTABLE(PERF_TP_FRONTEND_WORKING_CYCLES), 587 FD7_COUNTABLE(PERF_TP_L1_TAG_WORKING_CYCLES), 588 FD7_COUNTABLE(PERF_TP_L1_DATA_WRITE_WORKING_CYCLES), 589 FD7_COUNTABLE(PERF_TP_PRE_L1_DECOM_WORKING_CYCLES), 590 FD7_COUNTABLE(PERF_TP_BACKEND_WORKING_CYCLES), 591 FD7_COUNTABLE(PERF_TP_L1_5_CACHE_WORKING_CYCLES), 592 FD7_COUNTABLE(PERF_TP_STARVE_CYCLES_SP), 593 FD7_COUNTABLE(PERF_TP_STARVE_CYCLES_UCHE), 594 FD7_COUNTABLE(PERF_TP_STALL_CYCLES_UFC), 595 FD7_COUNTABLE(PERF_TP_FORMAT_DECOMP), 596 FD7_COUNTABLE(PERF_TP_FILTER_POINT_FP16), 597 FD7_COUNTABLE(PERF_TP_FILTER_POINT_FP32), 598 FD7_COUNTABLE(PERF_TP_LATENCY_FIFO_FULL), 599 FD7_COUNTABLE(PERF_TP_RESERVED_61), 600 FD7_COUNTABLE(PERF_TP_RESERVED_62), 601 FD7_COUNTABLE(PERF_TP_RESERVED_63), 602 FD7_COUNTABLE(PERF_TP_RESERVED_64), 603 FD7_COUNTABLE(PERF_TP_RESERVED_65), 604 FD7_COUNTABLE(PERF_TP_RESERVED_66), 605 FD7_COUNTABLE(PERF_TP_RESERVED_67), 606 FD7_COUNTABLE(PERF_TP_RESERVED_68), 607 FD7_COUNTABLE(PERF_TP_RESERVED_69), 608 FD7_COUNTABLE(PERF_TP_RESERVED_70), 609 FD7_COUNTABLE(PERF_TP_RESERVED_71), 610 FD7_COUNTABLE(PERF_TP_RESERVED_72), 611 FD7_COUNTABLE(PERF_TP_RESERVED_73), 612 FD7_COUNTABLE(PERF_TP_RESERVED_74), 613 FD7_COUNTABLE(PERF_TP_RESERVED_75), 614 FD7_COUNTABLE(PERF_TP_RESERVED_76), 615 FD7_COUNTABLE(PERF_TP_RESERVED_77), 616 FD7_COUNTABLE(PERF_TP_RESERVED_78), 617 FD7_COUNTABLE(PERF_TP_RESERVED_79), 618 FD7_COUNTABLE(PERF_TP_RESERVED_80), 619 FD7_COUNTABLE(PERF_TP_RESERVED_81), 620 FD7_COUNTABLE(PERF_TP_RESERVED_82), 621 FD7_COUNTABLE(PERF_TP_RESERVED_83), 622 FD7_COUNTABLE(PERF_TP_RESERVED_84), 623 FD7_COUNTABLE(PERF_TP_RESERVED_85), 624 FD7_COUNTABLE(PERF_TP_RESERVED_86), 625 FD7_COUNTABLE(PERF_TP_RESERVED_87), 626 FD7_COUNTABLE(PERF_TP_RESERVED_88), 627 FD7_COUNTABLE(PERF_TP_RESERVED_89), 628 FD7_COUNTABLE(PERF_TP_RESERVED_90), 629 FD7_COUNTABLE(PERF_TP_RESERVED_91), 630 FD7_COUNTABLE(PERF_TP_RESERVED_92), 631 FD7_COUNTABLE(PERF_TP_RESERVED_93), 632 FD7_COUNTABLE(PERF_TP_RESERVED_94), 633 FD7_COUNTABLE(PERF_TP_RESERVED_95), 634 FD7_COUNTABLE(PERF_TP_RESERVED_96), 635 FD7_COUNTABLE(PERF_TP_RESERVED_97), 636 FD7_COUNTABLE(PERF_TP_RESERVED_98), 637 FD7_COUNTABLE(PERF_TP_RESERVED_99), 638 FD7_COUNTABLE(PERF_TP_RESERVED_100), 639 FD7_COUNTABLE(PERF_TP_RESERVED_101), 640 FD7_COUNTABLE(PERF_TP_RESERVED_102), 641 FD7_COUNTABLE(PERF_TP_RESERVED_103), 642 FD7_COUNTABLE(PERF_TP_RESERVED_104), 643 FD7_COUNTABLE(PERF_TP_RESERVED_105), 644 FD7_COUNTABLE(PERF_TP_RESERVED_106), 645 FD7_COUNTABLE(PERF_TP_RESERVED_107), 646 FD7_COUNTABLE(PERF_TP_RESERVED_108), 647 FD7_COUNTABLE(PERF_TP_RESERVED_109), 648 FD7_COUNTABLE(PERF_TP_RESERVED_110), 649 FD7_COUNTABLE(PERF_TP_RESERVED_111), 650 FD7_COUNTABLE(PERF_TP_RESERVED_112), 651 FD7_COUNTABLE(PERF_TP_RESERVED_113), 652 FD7_COUNTABLE(PERF_TP_RESERVED_114), 653 FD7_COUNTABLE(PERF_TP_RESERVED_115), 654 FD7_COUNTABLE(PERF_TP_RESERVED_116), 655 FD7_COUNTABLE(PERF_TP_RESERVED_117), 656 FD7_COUNTABLE(PERF_TP_RESERVED_118), 657 FD7_COUNTABLE(PERF_TP_RESERVED_119), 658 FD7_COUNTABLE(PERF_TP_RESERVED_120), 659 FD7_COUNTABLE(PERF_TP_RESERVED_121), 660 FD7_COUNTABLE(PERF_TP_RESERVED_122), 661 FD7_COUNTABLE(PERF_TP_RESERVED_123), 662 FD7_COUNTABLE(PERF_TP_RESERVED_124), 663 FD7_COUNTABLE(PERF_TP_RESERVED_125), 664 FD7_COUNTABLE(PERF_TP_RESERVED_126), 665 FD7_COUNTABLE(PERF_TP_RESERVED_127), 666 FD7_COUNTABLE(PERF_TP_FORMAT_DECOMP_BILINEAR), 667 FD7_COUNTABLE(PERF_TP_PACKED_POINT_BOTH_VALID_FP16), 668 FD7_COUNTABLE(PERF_TP_PACKED_POINT_SINGLE_VALID_FP16), 669 FD7_COUNTABLE(PERF_TP_PACKED_POINT_BOTH_VALID_FP32), 670 FD7_COUNTABLE(PERF_TP_PACKED_POINT_SINGLE_VALID_FP32), 671 }; 672 673 static const struct fd_perfcntr_counter sp_counters[] = { 674 FD7_COUNTER(REG7(SP_PERFCTR_SP_SEL(0)), REG7(RBBM_PERFCTR_SP(0))), 675 FD7_COUNTER(REG7(SP_PERFCTR_SP_SEL(1)), REG7(RBBM_PERFCTR_SP(1))), 676 FD7_COUNTER(REG7(SP_PERFCTR_SP_SEL(2)), REG7(RBBM_PERFCTR_SP(2))), 677 FD7_COUNTER(REG7(SP_PERFCTR_SP_SEL(3)), REG7(RBBM_PERFCTR_SP(3))), 678 FD7_COUNTER(REG7(SP_PERFCTR_SP_SEL(4)), REG7(RBBM_PERFCTR_SP(4))), 679 FD7_COUNTER(REG7(SP_PERFCTR_SP_SEL(5)), REG7(RBBM_PERFCTR_SP(5))), 680 FD7_COUNTER(REG7(SP_PERFCTR_SP_SEL(6)), REG7(RBBM_PERFCTR_SP(6))), 681 FD7_COUNTER(REG7(SP_PERFCTR_SP_SEL(7)), REG7(RBBM_PERFCTR_SP(7))), 682 FD7_COUNTER(REG7(SP_PERFCTR_SP_SEL(8)), REG7(RBBM_PERFCTR_SP(8))), 683 FD7_COUNTER(REG7(SP_PERFCTR_SP_SEL(9)), REG7(RBBM_PERFCTR_SP(9))), 684 FD7_COUNTER(REG7(SP_PERFCTR_SP_SEL(10)), REG7(RBBM_PERFCTR_SP(10))), 685 FD7_COUNTER(REG7(SP_PERFCTR_SP_SEL(11)), REG7(RBBM_PERFCTR_SP(11))), 686 FD7_COUNTER(REG7(SP_PERFCTR_SP_SEL(12)), REG7(RBBM_PERFCTR_SP(12))), 687 FD7_COUNTER(REG7(SP_PERFCTR_SP_SEL(13)), REG7(RBBM_PERFCTR_SP(13))), 688 FD7_COUNTER(REG7(SP_PERFCTR_SP_SEL(14)), REG7(RBBM_PERFCTR_SP(14))), 689 FD7_COUNTER(REG7(SP_PERFCTR_SP_SEL(15)), REG7(RBBM_PERFCTR_SP(15))), 690 FD7_COUNTER(REG7(SP_PERFCTR_SP_SEL(16)), REG7(RBBM_PERFCTR_SP(16))), 691 FD7_COUNTER(REG7(SP_PERFCTR_SP_SEL(17)), REG7(RBBM_PERFCTR_SP(17))), 692 FD7_COUNTER(REG7(SP_PERFCTR_SP_SEL(18)), REG7(RBBM_PERFCTR_SP(18))), 693 FD7_COUNTER(REG7(SP_PERFCTR_SP_SEL(19)), REG7(RBBM_PERFCTR_SP(19))), 694 FD7_COUNTER(REG7(SP_PERFCTR_SP_SEL(20)), REG7(RBBM_PERFCTR_SP(20))), 695 FD7_COUNTER(REG7(SP_PERFCTR_SP_SEL(21)), REG7(RBBM_PERFCTR_SP(21))), 696 FD7_COUNTER(REG7(SP_PERFCTR_SP_SEL(22)), REG7(RBBM_PERFCTR_SP(22))), 697 FD7_COUNTER(REG7(SP_PERFCTR_SP_SEL(23)), REG7(RBBM_PERFCTR_SP(23))), 698 }; 699 700 static const struct fd_perfcntr_countable sp_countables[] = { 701 FD7_COUNTABLE(PERF_SP_BUSY_CYCLES), 702 FD7_COUNTABLE(PERF_SP_ALU_WORKING_CYCLES), 703 FD7_COUNTABLE(PERF_SP_EFU_WORKING_CYCLES), 704 FD7_COUNTABLE(PERF_SP_STALL_CYCLES_VPC), 705 FD7_COUNTABLE(PERF_SP_STALL_CYCLES_TP), 706 FD7_COUNTABLE(PERF_SP_STALL_CYCLES_UCHE), 707 FD7_COUNTABLE(PERF_SP_STALL_CYCLES_RB), 708 FD7_COUNTABLE(PERF_SP_NON_EXECUTION_CYCLES), 709 FD7_COUNTABLE(PERF_SP_WAVE_CONTEXTS), 710 FD7_COUNTABLE(PERF_SP_WAVE_CONTEXT_CYCLES), 711 FD7_COUNTABLE(PERF_SP_STAGE_WAVE_CYCLES), 712 FD7_COUNTABLE(PERF_SP_STAGE_WAVE_SAMPLES), 713 FD7_COUNTABLE(PERF_SP_VS_STAGE_WAVE_CYCLES), 714 FD7_COUNTABLE(PERF_SP_VS_STAGE_WAVE_SAMPLES), 715 FD7_COUNTABLE(PERF_SP_FS_STAGE_DURATION_CYCLES), 716 FD7_COUNTABLE(PERF_SP_VS_STAGE_DURATION_CYCLES), 717 FD7_COUNTABLE(PERF_SP_WAVE_CTRL_CYCLES), 718 FD7_COUNTABLE(PERF_SP_WAVE_LOAD_CYCLES), 719 FD7_COUNTABLE(PERF_SP_WAVE_EMIT_CYCLES), 720 FD7_COUNTABLE(PERF_SP_WAVE_NOP_CYCLES), 721 FD7_COUNTABLE(PERF_SP_WAVE_WAIT_CYCLES), 722 FD7_COUNTABLE(PERF_SP_WAVE_FETCH_CYCLES), 723 FD7_COUNTABLE(PERF_SP_WAVE_IDLE_CYCLES), 724 FD7_COUNTABLE(PERF_SP_WAVE_END_CYCLES), 725 FD7_COUNTABLE(PERF_SP_WAVE_LONG_SYNC_CYCLES), 726 FD7_COUNTABLE(PERF_SP_WAVE_SHORT_SYNC_CYCLES), 727 FD7_COUNTABLE(PERF_SP_WAVE_JOIN_CYCLES), 728 FD7_COUNTABLE(PERF_SP_LM_LOAD_INSTRUCTIONS), 729 FD7_COUNTABLE(PERF_SP_LM_STORE_INSTRUCTIONS), 730 FD7_COUNTABLE(PERF_SP_LM_ATOMICS), 731 FD7_COUNTABLE(PERF_SP_GM_LOAD_INSTRUCTIONS), 732 FD7_COUNTABLE(PERF_SP_GM_STORE_INSTRUCTIONS), 733 FD7_COUNTABLE(PERF_SP_GM_ATOMICS), 734 FD7_COUNTABLE(PERF_SP_VS_STAGE_TEX_INSTRUCTIONS), 735 FD7_COUNTABLE(PERF_SP_VS_STAGE_EFU_INSTRUCTIONS), 736 FD7_COUNTABLE(PERF_SP_VS_STAGE_FULL_ALU_INSTRUCTIONS), 737 FD7_COUNTABLE(PERF_SP_VS_STAGE_HALF_ALU_INSTRUCTIONS), 738 FD7_COUNTABLE(PERF_SP_FS_STAGE_TEX_INSTRUCTIONS), 739 FD7_COUNTABLE(PERF_SP_FS_STAGE_CFLOW_INSTRUCTIONS), 740 FD7_COUNTABLE(PERF_SP_FS_STAGE_EFU_INSTRUCTIONS), 741 FD7_COUNTABLE(PERF_SP_FS_STAGE_FULL_ALU_INSTRUCTIONS), 742 FD7_COUNTABLE(PERF_SP_FS_STAGE_HALF_ALU_INSTRUCTIONS), 743 FD7_COUNTABLE(PERF_SP_FS_STAGE_BARY_INSTRUCTIONS), 744 FD7_COUNTABLE(PERF_SP_VS_INSTRUCTIONS), 745 FD7_COUNTABLE(PERF_SP_FS_INSTRUCTIONS), 746 FD7_COUNTABLE(PERF_SP_ADDR_LOCK_COUNT), 747 FD7_COUNTABLE(PERF_SP_UCHE_READ_TRANS), 748 FD7_COUNTABLE(PERF_SP_UCHE_WRITE_TRANS), 749 FD7_COUNTABLE(PERF_SP_EXPORT_VPC_TRANS), 750 FD7_COUNTABLE(PERF_SP_EXPORT_RB_TRANS), 751 FD7_COUNTABLE(PERF_SP_PIXELS_KILLED), 752 FD7_COUNTABLE(PERF_SP_ICL1_REQUESTS), 753 FD7_COUNTABLE(PERF_SP_ICL1_MISSES), 754 FD7_COUNTABLE(PERF_SP_HS_INSTRUCTIONS), 755 FD7_COUNTABLE(PERF_SP_DS_INSTRUCTIONS), 756 FD7_COUNTABLE(PERF_SP_GS_INSTRUCTIONS), 757 FD7_COUNTABLE(PERF_SP_CS_INSTRUCTIONS), 758 FD7_COUNTABLE(PERF_SP_GPR_READ), 759 FD7_COUNTABLE(PERF_SP_GPR_WRITE), 760 FD7_COUNTABLE(PERF_SP_FS_STAGE_HALF_EFU_INSTRUCTIONS), 761 FD7_COUNTABLE(PERF_SP_VS_STAGE_HALF_EFU_INSTRUCTIONS), 762 FD7_COUNTABLE(PERF_SP_LM_BANK_CONFLICTS), 763 FD7_COUNTABLE(PERF_SP_TEX_CONTROL_WORKING_CYCLES), 764 FD7_COUNTABLE(PERF_SP_LOAD_CONTROL_WORKING_CYCLES), 765 FD7_COUNTABLE(PERF_SP_FLOW_CONTROL_WORKING_CYCLES), 766 FD7_COUNTABLE(PERF_SP_LM_WORKING_CYCLES), 767 FD7_COUNTABLE(PERF_SP_DISPATCHER_WORKING_CYCLES), 768 FD7_COUNTABLE(PERF_SP_SEQUENCER_WORKING_CYCLES), 769 FD7_COUNTABLE(PERF_SP_LOW_EFFICIENCY_STARVED_BY_TP), 770 FD7_COUNTABLE(PERF_SP_STARVE_CYCLES_HLSQ), 771 FD7_COUNTABLE(PERF_SP_NON_EXECUTION_LS_CYCLES), 772 FD7_COUNTABLE(PERF_SP_WORKING_EU), 773 FD7_COUNTABLE(PERF_SP_ANY_EU_WORKING), 774 FD7_COUNTABLE(PERF_SP_WORKING_EU_FS_STAGE), 775 FD7_COUNTABLE(PERF_SP_ANY_EU_WORKING_FS_STAGE), 776 FD7_COUNTABLE(PERF_SP_WORKING_EU_VS_STAGE), 777 FD7_COUNTABLE(PERF_SP_ANY_EU_WORKING_VS_STAGE), 778 FD7_COUNTABLE(PERF_SP_WORKING_EU_CS_STAGE), 779 FD7_COUNTABLE(PERF_SP_ANY_EU_WORKING_CS_STAGE), 780 FD7_COUNTABLE(PERF_SP_GPR_READ_PREFETCH), 781 FD7_COUNTABLE(PERF_SP_GPR_READ_CONFLICT), 782 FD7_COUNTABLE(PERF_SP_GPR_WRITE_CONFLICT), 783 FD7_COUNTABLE(PERF_SP_GM_LOAD_LATENCY_CYCLES), 784 FD7_COUNTABLE(PERF_SP_GM_LOAD_LATENCY_SAMPLES), 785 FD7_COUNTABLE(PERF_SP_EXECUTABLE_WAVES), 786 FD7_COUNTABLE(PERF_SP_ICL1_MISS_FETCH_CYCLES), 787 FD7_COUNTABLE(PERF_SP_WORKING_EU_LPAC), 788 FD7_COUNTABLE(PERF_SP_BYPASS_BUSY_CYCLES), 789 FD7_COUNTABLE(PERF_SP_ANY_EU_WORKING_LPAC), 790 FD7_COUNTABLE(PERF_SP_WAVE_ALU_CYCLES), 791 FD7_COUNTABLE(PERF_SP_WAVE_EFU_CYCLES), 792 FD7_COUNTABLE(PERF_SP_WAVE_INT_CYCLES), 793 FD7_COUNTABLE(PERF_SP_WAVE_CSP_CYCLES), 794 FD7_COUNTABLE(PERF_SP_EWAVE_CONTEXTS), 795 FD7_COUNTABLE(PERF_SP_EWAVE_CONTEXT_CYCLES), 796 FD7_COUNTABLE(PERF_SP_LPAC_BUSY_CYCLES), 797 FD7_COUNTABLE(PERF_SP_LPAC_INSTRUCTIONS), 798 FD7_COUNTABLE(PERF_SP_FS_STAGE_1X_WAVES), 799 FD7_COUNTABLE(PERF_SP_FS_STAGE_2X_WAVES), 800 FD7_COUNTABLE(PERF_SP_QUADS), 801 FD7_COUNTABLE(PERF_SP_CS_INVOCATIONS), 802 FD7_COUNTABLE(PERF_SP_PIXELS), 803 FD7_COUNTABLE(PERF_SP_LPAC_DRAWCALLS), 804 FD7_COUNTABLE(PERF_SP_PI_WORKING_CYCLES), 805 FD7_COUNTABLE(PERF_SP_WAVE_INPUT_CYCLES), 806 FD7_COUNTABLE(PERF_SP_WAVE_OUTPUT_CYCLES), 807 FD7_COUNTABLE(PERF_SP_WAVE_HWAVE_WAIT_CYCLES), 808 FD7_COUNTABLE(PERF_SP_WAVE_HWAVE_SYNC), 809 FD7_COUNTABLE(PERF_SP_OUTPUT_3D_PIXELS), 810 FD7_COUNTABLE(PERF_SP_FULL_ALU_MAD_INSTRUCTIONS), 811 FD7_COUNTABLE(PERF_SP_HALF_ALU_MAD_INSTRUCTIONS), 812 FD7_COUNTABLE(PERF_SP_FULL_ALU_MUL_INSTRUCTIONS), 813 FD7_COUNTABLE(PERF_SP_HALF_ALU_MUL_INSTRUCTIONS), 814 FD7_COUNTABLE(PERF_SP_FULL_ALU_ADD_INSTRUCTIONS), 815 FD7_COUNTABLE(PERF_SP_HALF_ALU_ADD_INSTRUCTIONS), 816 FD7_COUNTABLE(PERF_SP_BARY_FP32_INSTRUCTIONS), 817 FD7_COUNTABLE(PERF_SP_ALU_GPR_READ_CYCLES), 818 FD7_COUNTABLE(PERF_SP_ALU_DATA_FORWARDING_CYCLES), 819 FD7_COUNTABLE(PERF_SP_LM_FULL_CYCLES), 820 FD7_COUNTABLE(PERF_SP_TEXTURE_FETCH_LATENCY_CYCLES), 821 FD7_COUNTABLE(PERF_SP_TEXTURE_FETCH_LATENCY_SAMPLES), 822 FD7_COUNTABLE(PERF_SP_FS_STAGE_PI_TEX_INSTRUCTION), 823 FD7_COUNTABLE(PERF_SP_RAY_QUERY_INSTRUCTIONS), 824 FD7_COUNTABLE(PERF_SP_RBRT_KICKOFF_FIBERS), 825 FD7_COUNTABLE(PERF_SP_RBRT_KICKOFF_DQUADS), 826 FD7_COUNTABLE(PERF_SP_RTU_BUSY_CYCLES), 827 FD7_COUNTABLE(PERF_SP_RTU_L0_HITS), 828 FD7_COUNTABLE(PERF_SP_RTU_L0_MISSES), 829 FD7_COUNTABLE(PERF_SP_RTU_L0_HIT_ON_MISS), 830 FD7_COUNTABLE(PERF_SP_RTU_STALL_CYCLES_WAVE_QUEUE), 831 FD7_COUNTABLE(PERF_SP_RTU_STALL_CYCLES_L0_HIT_QUEUE), 832 FD7_COUNTABLE(PERF_SP_RTU_STALL_CYCLES_L0_MISS_QUEUE), 833 FD7_COUNTABLE(PERF_SP_RTU_STALL_CYCLES_L0D_IDX_QUEUE), 834 FD7_COUNTABLE(PERF_SP_RTU_STALL_CYCLES_L0DATA), 835 FD7_COUNTABLE(PERF_SP_RTU_STALL_CYCLES_REPLACE_CNT), 836 FD7_COUNTABLE(PERF_SP_RTU_STALL_CYCLES_MRG_CNT), 837 FD7_COUNTABLE(PERF_SP_RTU_STALL_CYCLES_UCHE), 838 FD7_COUNTABLE(PERF_SP_RTU_OPERAND_FETCH_STALL_CYCLES_L0), 839 FD7_COUNTABLE(PERF_SP_RTU_OPERAND_FETCH_STALL_CYCLES_INS_FIFO), 840 FD7_COUNTABLE(PERF_SP_RTU_BVH_FETCH_LATENCY_CYCLES), 841 FD7_COUNTABLE(PERF_SP_RTU_BVH_FETCH_LATENCY_SAMPLES), 842 FD7_COUNTABLE(PERF_SP_STCHE_MISS_INC_VS), 843 FD7_COUNTABLE(PERF_SP_STCHE_MISS_INC_FS), 844 FD7_COUNTABLE(PERF_SP_STCHE_MISS_INC_BV), 845 FD7_COUNTABLE(PERF_SP_STCHE_MISS_INC_LPAC), 846 FD7_COUNTABLE(PERF_SP_VGPR_ACTIVE_CONTEXTS), 847 FD7_COUNTABLE(PERF_SP_PGPR_ALLOC_CONTEXTS), 848 FD7_COUNTABLE(PERF_SP_VGPR_ALLOC_CONTEXTS), 849 FD7_COUNTABLE(PERF_SP_RTU_RAY_BOX_INTERSECTIONS), 850 FD7_COUNTABLE(PERF_SP_RTU_RAY_TRIANGLE_INTERSECTIONS), 851 FD7_COUNTABLE(PERF_SP_SCH_STALL_CYCLES_RTU), 852 }; 853 854 static const struct fd_perfcntr_counter rb_counters[] = { 855 FD7_COUNTER(REG6(RB_PERFCTR_RB_SEL(0)), REG7(RBBM_PERFCTR_RB(0))), 856 FD7_COUNTER(REG6(RB_PERFCTR_RB_SEL(1)), REG7(RBBM_PERFCTR_RB(1))), 857 FD7_COUNTER(REG6(RB_PERFCTR_RB_SEL(2)), REG7(RBBM_PERFCTR_RB(2))), 858 FD7_COUNTER(REG6(RB_PERFCTR_RB_SEL(3)), REG7(RBBM_PERFCTR_RB(3))), 859 FD7_COUNTER(REG6(RB_PERFCTR_RB_SEL(4)), REG7(RBBM_PERFCTR_RB(4))), 860 FD7_COUNTER(REG6(RB_PERFCTR_RB_SEL(5)), REG7(RBBM_PERFCTR_RB(5))), 861 FD7_COUNTER(REG6(RB_PERFCTR_RB_SEL(6)), REG7(RBBM_PERFCTR_RB(6))), 862 FD7_COUNTER(REG6(RB_PERFCTR_RB_SEL(7)), REG7(RBBM_PERFCTR_RB(7))), 863 }; 864 865 static const struct fd_perfcntr_countable rb_countables[] = { 866 FD7_COUNTABLE(PERF_RB_BUSY_CYCLES), 867 FD7_COUNTABLE(PERF_RB_STALL_CYCLES_HLSQ), 868 FD7_COUNTABLE(PERF_RB_STALL_CYCLES_FIFO0_FULL), 869 FD7_COUNTABLE(PERF_RB_STALL_CYCLES_FIFO1_FULL), 870 FD7_COUNTABLE(PERF_RB_STALL_CYCLES_FIFO2_FULL), 871 FD7_COUNTABLE(PERF_RB_STARVE_CYCLES_SP), 872 FD7_COUNTABLE(PERF_RB_STARVE_CYCLES_LRZ_TILE), 873 FD7_COUNTABLE(PERF_RB_STARVE_CYCLES_CCU), 874 FD7_COUNTABLE(PERF_RB_STARVE_CYCLES_Z_PLANE), 875 FD7_COUNTABLE(PERF_RB_STARVE_CYCLES_BARY_PLANE), 876 FD7_COUNTABLE(PERF_RB_Z_WORKLOAD), 877 FD7_COUNTABLE(PERF_RB_HLSQ_ACTIVE), 878 FD7_COUNTABLE(PERF_RB_Z_READ), 879 FD7_COUNTABLE(PERF_RB_Z_WRITE), 880 FD7_COUNTABLE(PERF_RB_C_READ), 881 FD7_COUNTABLE(PERF_RB_C_WRITE), 882 FD7_COUNTABLE(PERF_RB_TOTAL_PASS), 883 FD7_COUNTABLE(PERF_RB_Z_PASS), 884 FD7_COUNTABLE(PERF_RB_Z_FAIL), 885 FD7_COUNTABLE(PERF_RB_S_FAIL), 886 FD7_COUNTABLE(PERF_RB_BLENDED_FXP_COMPONENTS), 887 FD7_COUNTABLE(PERF_RB_BLENDED_FP16_COMPONENTS), 888 FD7_COUNTABLE(PERF_RB_PS_INVOCATIONS), 889 FD7_COUNTABLE(PERF_RB_2D_ALIVE_CYCLES), 890 FD7_COUNTABLE(PERF_RB_2D_STALL_CYCLES_A2D), 891 FD7_COUNTABLE(PERF_RB_2D_STARVE_CYCLES_SRC), 892 FD7_COUNTABLE(PERF_RB_2D_STARVE_CYCLES_SP), 893 FD7_COUNTABLE(PERF_RB_2D_STARVE_CYCLES_DST), 894 FD7_COUNTABLE(PERF_RB_2D_VALID_PIXELS), 895 FD7_COUNTABLE(PERF_RB_3D_PIXELS), 896 FD7_COUNTABLE(PERF_RB_BLENDER_WORKING_CYCLES), 897 FD7_COUNTABLE(PERF_RB_ZPROC_WORKING_CYCLES), 898 FD7_COUNTABLE(PERF_RB_CPROC_WORKING_CYCLES), 899 FD7_COUNTABLE(PERF_RB_SAMPLER_WORKING_CYCLES), 900 FD7_COUNTABLE(PERF_RB_STALL_CYCLES_CCU_COLOR_READ), 901 FD7_COUNTABLE(PERF_RB_STALL_CYCLES_CCU_COLOR_WRITE), 902 FD7_COUNTABLE(PERF_RB_STALL_CYCLES_CCU_DEPTH_READ), 903 FD7_COUNTABLE(PERF_RB_STALL_CYCLES_CCU_DEPTH_WRITE), 904 FD7_COUNTABLE(PERF_RB_STALL_CYCLES_VPC), 905 FD7_COUNTABLE(PERF_RB_2D_INPUT_TRANS), 906 FD7_COUNTABLE(PERF_RB_2D_OUTPUT_RB_DST_TRANS), 907 FD7_COUNTABLE(PERF_RB_2D_OUTPUT_RB_SRC_TRANS), 908 FD7_COUNTABLE(PERF_RB_BLENDED_FP32_COMPONENTS), 909 FD7_COUNTABLE(PERF_RB_COLOR_PIX_TILES), 910 FD7_COUNTABLE(PERF_RB_STALL_CYCLES_CCU), 911 FD7_COUNTABLE(PERF_RB_EARLY_Z_ARB3_GRANT), 912 FD7_COUNTABLE(PERF_RB_LATE_Z_ARB3_GRANT), 913 FD7_COUNTABLE(PERF_RB_EARLY_Z_SKIP_GRANT), 914 FD7_COUNTABLE(PERF_RB_VRS_1x1_QUADS), 915 FD7_COUNTABLE(PERF_RB_VRS_2x1_QUADS), 916 FD7_COUNTABLE(PERF_RB_VRS_1x2_QUADS), 917 FD7_COUNTABLE(PERF_RB_VRS_2x2_QUADS), 918 FD7_COUNTABLE(PERF_RB_VRS_4x2_QUADS), 919 FD7_COUNTABLE(PERF_RB_VRS_4x4_QUADS), 920 }; 921 922 static const struct fd_perfcntr_counter vsc_counters[] = { 923 FD7_COUNTER(REG6(VSC_PERFCTR_VSC_SEL(0)), REG7(RBBM_PERFCTR_VSC(0))), 924 FD7_COUNTER(REG6(VSC_PERFCTR_VSC_SEL(1)), REG7(RBBM_PERFCTR_VSC(1))), 925 }; 926 927 static const struct fd_perfcntr_countable vsc_countables[] = { 928 FD7_COUNTABLE(PERF_VSC_BUSY_CYCLES), 929 FD7_COUNTABLE(PERF_VSC_WORKING_CYCLES), 930 FD7_COUNTABLE(PERF_VSC_STALL_CYCLES_UCHE), 931 FD7_COUNTABLE(PERF_VSC_EOT_NUM), 932 FD7_COUNTABLE(PERF_VSC_INPUT_TILES), 933 }; 934 935 static const struct fd_perfcntr_counter ccu_counters[] = { 936 FD7_COUNTER(REG6(RB_PERFCTR_CCU_SEL(0)), REG7(RBBM_PERFCTR_CCU(0))), 937 FD7_COUNTER(REG6(RB_PERFCTR_CCU_SEL(1)), REG7(RBBM_PERFCTR_CCU(1))), 938 FD7_COUNTER(REG6(RB_PERFCTR_CCU_SEL(2)), REG7(RBBM_PERFCTR_CCU(2))), 939 FD7_COUNTER(REG6(RB_PERFCTR_CCU_SEL(3)), REG7(RBBM_PERFCTR_CCU(3))), 940 FD7_COUNTER(REG6(RB_PERFCTR_CCU_SEL(4)), REG7(RBBM_PERFCTR_CCU(4))), 941 }; 942 943 static const struct fd_perfcntr_countable ccu_countables[] = { 944 FD7_COUNTABLE(PERF_CCU_BUSY_CYCLES), 945 FD7_COUNTABLE(PERF_CCU_STALL_CYCLES_RB_DEPTH_RETURN), 946 FD7_COUNTABLE(PERF_CCU_STALL_CYCLES_RB_COLOR_RETURN), 947 FD7_COUNTABLE(PERF_CCU_DEPTH_BLOCKS), 948 FD7_COUNTABLE(PERF_CCU_COLOR_BLOCKS), 949 FD7_COUNTABLE(PERF_CCU_DEPTH_BLOCK_HIT), 950 FD7_COUNTABLE(PERF_CCU_COLOR_BLOCK_HIT), 951 FD7_COUNTABLE(PERF_CCU_PARTIAL_BLOCK_READ), 952 FD7_COUNTABLE(PERF_CCU_GMEM_READ), 953 FD7_COUNTABLE(PERF_CCU_GMEM_WRITE), 954 FD7_COUNTABLE(PERF_CCU_2D_RD_REQ), 955 FD7_COUNTABLE(PERF_CCU_2D_WR_REQ), 956 FD7_COUNTABLE(PERF_CCU_UBWC_COLOR_BLOCKS_CONCURRENT), 957 FD7_COUNTABLE(PERF_CCU_UBWC_DEPTH_BLOCKS_CONCURRENT), 958 FD7_COUNTABLE(PERF_CCU_COLOR_RESOLVE_DROPPED), 959 FD7_COUNTABLE(PERF_CCU_DEPTH_RESOLVE_DROPPED), 960 FD7_COUNTABLE(PERF_CCU_COLOR_RENDER_CONCURRENT), 961 FD7_COUNTABLE(PERF_CCU_DEPTH_RENDER_CONCURRENT), 962 FD7_COUNTABLE(PERF_CCU_COLOR_RESOLVE_AFTER_RENDER), 963 FD7_COUNTABLE(PERF_CCU_DEPTH_RESOLVE_AFTER_RENDER), 964 FD7_COUNTABLE(PERF_CCU_GMEM_EXTRA_DEPTH_READ), 965 FD7_COUNTABLE(PERF_CCU_GMEM_COLOR_READ_4AA), 966 FD7_COUNTABLE(PERF_CCU_GMEM_COLOR_READ_4AA_FULL), 967 }; 968 969 static const struct fd_perfcntr_counter lrz_counters[] = { 970 FD7_COUNTER(REG6(GRAS_PERFCTR_LRZ_SEL(0)), REG7(RBBM_PERFCTR_LRZ(0))), 971 FD7_COUNTER(REG6(GRAS_PERFCTR_LRZ_SEL(1)), REG7(RBBM_PERFCTR_LRZ(1))), 972 FD7_COUNTER(REG6(GRAS_PERFCTR_LRZ_SEL(2)), REG7(RBBM_PERFCTR_LRZ(2))), 973 FD7_COUNTER(REG6(GRAS_PERFCTR_LRZ_SEL(3)), REG7(RBBM_PERFCTR_LRZ(3))), 974 }; 975 976 static const struct fd_perfcntr_countable lrz_countables[] = { 977 FD7_COUNTABLE(PERF_LRZ_BUSY_CYCLES), 978 FD7_COUNTABLE(PERF_LRZ_STARVE_CYCLES_RAS), 979 FD7_COUNTABLE(PERF_LRZ_STALL_CYCLES_RB), 980 FD7_COUNTABLE(PERF_LRZ_STALL_CYCLES_VSC), 981 FD7_COUNTABLE(PERF_LRZ_STALL_CYCLES_VPC), 982 FD7_COUNTABLE(PERF_LRZ_STALL_CYCLES_FLAG_PREFETCH), 983 FD7_COUNTABLE(PERF_LRZ_STALL_CYCLES_UCHE), 984 FD7_COUNTABLE(PERF_LRZ_LRZ_READ), 985 FD7_COUNTABLE(PERF_LRZ_LRZ_WRITE), 986 FD7_COUNTABLE(PERF_LRZ_READ_LATENCY), 987 FD7_COUNTABLE(PERF_LRZ_MERGE_CACHE_UPDATING), 988 FD7_COUNTABLE(PERF_LRZ_PRIM_KILLED_BY_MASKGEN), 989 FD7_COUNTABLE(PERF_LRZ_PRIM_KILLED_BY_LRZ), 990 FD7_COUNTABLE(PERF_LRZ_VISIBLE_PRIM_AFTER_LRZ), 991 FD7_COUNTABLE(PERF_LRZ_FULL_8X8_TILES), 992 FD7_COUNTABLE(PERF_LRZ_PARTIAL_8X8_TILES), 993 FD7_COUNTABLE(PERF_LRZ_TILE_KILLED), 994 FD7_COUNTABLE(PERF_LRZ_TOTAL_PIXEL), 995 FD7_COUNTABLE(PERF_LRZ_VISIBLE_PIXEL_AFTER_LRZ), 996 FD7_COUNTABLE(PERF_LRZ_FEEDBACK_ACCEPT), 997 FD7_COUNTABLE(PERF_LRZ_FEEDBACK_DISCARD), 998 FD7_COUNTABLE(PERF_LRZ_FEEDBACK_STALL), 999 FD7_COUNTABLE(PERF_LRZ_STALL_CYCLES_RB_ZPLANE), 1000 FD7_COUNTABLE(PERF_LRZ_STALL_CYCLES_RB_BPLANE), 1001 FD7_COUNTABLE(PERF_LRZ_RAS_MASK_TRANS), 1002 FD7_COUNTABLE(PERF_LRZ_STALL_CYCLES_MVC), 1003 FD7_COUNTABLE(PERF_LRZ_TILE_KILLED_BY_IMAGE_VRS), 1004 FD7_COUNTABLE(PERF_LRZ_TILE_KILLED_BY_Z), 1005 }; 1006 1007 static const struct fd_perfcntr_counter cmp_counters[] = { 1008 FD7_COUNTER(REG6(RB_PERFCTR_CMP_SEL(0)), REG7(RBBM_PERFCTR_CMP(0))), 1009 FD7_COUNTER(REG6(RB_PERFCTR_CMP_SEL(1)), REG7(RBBM_PERFCTR_CMP(1))), 1010 FD7_COUNTER(REG6(RB_PERFCTR_CMP_SEL(2)), REG7(RBBM_PERFCTR_CMP(2))), 1011 FD7_COUNTER(REG6(RB_PERFCTR_CMP_SEL(3)), REG7(RBBM_PERFCTR_CMP(3))), 1012 }; 1013 1014 static const struct fd_perfcntr_countable cmp_countables[] = { 1015 FD7_COUNTABLE(PERF_CMPDECMP_STALL_CYCLES_ARB), 1016 FD7_COUNTABLE(PERF_CMPDECMP_VBIF_LATENCY_CYCLES), 1017 FD7_COUNTABLE(PERF_CMPDECMP_VBIF_LATENCY_SAMPLES), 1018 FD7_COUNTABLE(PERF_CMPDECMP_VBIF_READ_DATA_CCU), 1019 FD7_COUNTABLE(PERF_CMPDECMP_VBIF_WRITE_DATA_CCU), 1020 FD7_COUNTABLE(PERF_CMPDECMP_VBIF_READ_REQUEST), 1021 FD7_COUNTABLE(PERF_CMPDECMP_VBIF_WRITE_REQUEST), 1022 FD7_COUNTABLE(PERF_CMPDECMP_VBIF_READ_DATA), 1023 FD7_COUNTABLE(PERF_CMPDECMP_VBIF_WRITE_DATA), 1024 FD7_COUNTABLE(PERF_CMPDECMP_DEPTH_WRITE_FLAG1_COUNT), 1025 FD7_COUNTABLE(PERF_CMPDECMP_DEPTH_WRITE_FLAG2_COUNT), 1026 FD7_COUNTABLE(PERF_CMPDECMP_DEPTH_WRITE_FLAG3_COUNT), 1027 FD7_COUNTABLE(PERF_CMPDECMP_DEPTH_WRITE_FLAG4_COUNT), 1028 FD7_COUNTABLE(PERF_CMPDECMP_DEPTH_WRITE_FLAG5_COUNT), 1029 FD7_COUNTABLE(PERF_CMPDECMP_DEPTH_WRITE_FLAG6_COUNT), 1030 FD7_COUNTABLE(PERF_CMPDECMP_DEPTH_WRITE_FLAG8_COUNT), 1031 FD7_COUNTABLE(PERF_CMPDECMP_COLOR_WRITE_FLAG1_COUNT), 1032 FD7_COUNTABLE(PERF_CMPDECMP_COLOR_WRITE_FLAG2_COUNT), 1033 FD7_COUNTABLE(PERF_CMPDECMP_COLOR_WRITE_FLAG3_COUNT), 1034 FD7_COUNTABLE(PERF_CMPDECMP_COLOR_WRITE_FLAG4_COUNT), 1035 FD7_COUNTABLE(PERF_CMPDECMP_COLOR_WRITE_FLAG5_COUNT), 1036 FD7_COUNTABLE(PERF_CMPDECMP_COLOR_WRITE_FLAG6_COUNT), 1037 FD7_COUNTABLE(PERF_CMPDECMP_COLOR_WRITE_FLAG8_COUNT), 1038 FD7_COUNTABLE(PERF_CMPDECMP_VBIF_READ_DATA_UCHE_CH0), 1039 FD7_COUNTABLE(PERF_CMPDECMP_VBIF_READ_DATA_UCHE_CH1), 1040 FD7_COUNTABLE(PERF_CMPDECMP_VBIF_WRITE_DATA_UCHE), 1041 FD7_COUNTABLE(PERF_CMPDECMP_DEPTH_WRITE_FLAG0_COUNT), 1042 FD7_COUNTABLE(PERF_CMPDECMP_COLOR_WRITE_FLAG0_COUNT), 1043 FD7_COUNTABLE(PERF_CMPDECMP_COLOR_WRITE_FLAGALPHA_COUNT), 1044 FD7_COUNTABLE(PERF_CMPDECMP_RESOLVE_EVENTS), 1045 FD7_COUNTABLE(PERF_CMPDECMP_CONCURRENT_RESOLVE_EVENTS), 1046 FD7_COUNTABLE(PERF_CMPDECMP_DROPPED_CLEAR_EVENTS), 1047 FD7_COUNTABLE(PERF_CMPDECMP_ST_BLOCKS_CONCURRENT), 1048 FD7_COUNTABLE(PERF_CMPDECMP_LRZ_ST_BLOCKS_CONCURRENT), 1049 FD7_COUNTABLE(PERF_CMPDECMP_DEPTH_READ_FLAG0_COUNT), 1050 FD7_COUNTABLE(PERF_CMPDECMP_DEPTH_READ_FLAG1_COUNT), 1051 FD7_COUNTABLE(PERF_CMPDECMP_DEPTH_READ_FLAG2_COUNT), 1052 FD7_COUNTABLE(PERF_CMPDECMP_DEPTH_READ_FLAG3_COUNT), 1053 FD7_COUNTABLE(PERF_CMPDECMP_DEPTH_READ_FLAG4_COUNT), 1054 FD7_COUNTABLE(PERF_CMPDECMP_DEPTH_READ_FLAG5_COUNT), 1055 FD7_COUNTABLE(PERF_CMPDECMP_DEPTH_READ_FLAG6_COUNT), 1056 FD7_COUNTABLE(PERF_CMPDECMP_DEPTH_READ_FLAG8_COUNT), 1057 FD7_COUNTABLE(PERF_CMPDECMP_COLOR_READ_FLAG0_COUNT), 1058 FD7_COUNTABLE(PERF_CMPDECMP_COLOR_READ_FLAG1_COUNT), 1059 FD7_COUNTABLE(PERF_CMPDECMP_COLOR_READ_FLAG2_COUNT), 1060 FD7_COUNTABLE(PERF_CMPDECMP_COLOR_READ_FLAG3_COUNT), 1061 FD7_COUNTABLE(PERF_CMPDECMP_COLOR_READ_FLAG4_COUNT), 1062 FD7_COUNTABLE(PERF_CMPDECMP_COLOR_READ_FLAG5_COUNT), 1063 FD7_COUNTABLE(PERF_CMPDECMP_COLOR_READ_FLAG6_COUNT), 1064 FD7_COUNTABLE(PERF_CMPDECMP_COLOR_READ_FLAG8_COUNT), 1065 }; 1066 1067 static const struct fd_perfcntr_counter ufc_counters[] = { 1068 FD7_COUNTER(REG7(RB_PERFCTR_UFC_SEL(0)), REG7(RBBM_PERFCTR_UFC(0))), 1069 FD7_COUNTER(REG7(RB_PERFCTR_UFC_SEL(1)), REG7(RBBM_PERFCTR_UFC(1))), 1070 FD7_COUNTER(REG7(RB_PERFCTR_UFC_SEL(2)), REG7(RBBM_PERFCTR_UFC(2))), 1071 FD7_COUNTER(REG7(RB_PERFCTR_UFC_SEL(3)), REG7(RBBM_PERFCTR_UFC(3))), 1072 }; 1073 1074 static const struct fd_perfcntr_countable ufc_countables[] = { 1075 FD7_COUNTABLE(PERF_UFC_BUSY_CYCLES), 1076 FD7_COUNTABLE(PERF_UFC_READ_DATA_VBIF), 1077 FD7_COUNTABLE(PERF_UFC_WRITE_DATA_VBIF), 1078 FD7_COUNTABLE(PERF_UFC_READ_REQUEST_VBIF), 1079 FD7_COUNTABLE(PERF_UFC_WRITE_REQUEST_VBIF), 1080 FD7_COUNTABLE(PERF_UFC_LRZ_FILTER_HIT), 1081 FD7_COUNTABLE(PERF_UFC_LRZ_FILTER_MISS), 1082 FD7_COUNTABLE(PERF_UFC_CRE_FILTER_HIT), 1083 FD7_COUNTABLE(PERF_UFC_CRE_FILTER_MISS), 1084 FD7_COUNTABLE(PERF_UFC_SP_FILTER_HIT), 1085 FD7_COUNTABLE(PERF_UFC_SP_FILTER_MISS), 1086 FD7_COUNTABLE(PERF_UFC_SP_REQUESTS), 1087 FD7_COUNTABLE(PERF_UFC_TP_FILTER_HIT), 1088 FD7_COUNTABLE(PERF_UFC_TP_FILTER_MISS), 1089 FD7_COUNTABLE(PERF_UFC_TP_REQUESTS), 1090 FD7_COUNTABLE(PERF_UFC_MAIN_HIT_LRZ_PREFETCH), 1091 FD7_COUNTABLE(PERF_UFC_MAIN_HIT_CRE_PREFETCH), 1092 FD7_COUNTABLE(PERF_UFC_MAIN_HIT_SP_PREFETCH), 1093 FD7_COUNTABLE(PERF_UFC_MAIN_HIT_TP_PREFETCH), 1094 FD7_COUNTABLE(PERF_UFC_MAIN_HIT_UBWC_READ), 1095 FD7_COUNTABLE(PERF_UFC_MAIN_HIT_UBWC_WRITE), 1096 FD7_COUNTABLE(PERF_UFC_MAIN_MISS_LRZ_PREFETCH), 1097 FD7_COUNTABLE(PERF_UFC_MAIN_MISS_CRE_PREFETCH), 1098 FD7_COUNTABLE(PERF_UFC_MAIN_MISS_SP_PREFETCH), 1099 FD7_COUNTABLE(PERF_UFC_MAIN_MISS_TP_PREFETCH), 1100 FD7_COUNTABLE(PERF_UFC_MAIN_MISS_UBWC_READ), 1101 FD7_COUNTABLE(PERF_UFC_MAIN_MISS_UBWC_WRITE), 1102 FD7_COUNTABLE(PERF_UFC_UBWC_READ_UFC_TRANS), 1103 FD7_COUNTABLE(PERF_UFC_UBWC_WRITE_UFC_TRANS), 1104 FD7_COUNTABLE(PERF_UFC_STALL_CYCLES_GBIF_CMD), 1105 FD7_COUNTABLE(PERF_UFC_STALL_CYCLES_GBIF_RDATA), 1106 FD7_COUNTABLE(PERF_UFC_STALL_CYCLES_GBIF_WDATA), 1107 FD7_COUNTABLE(PERF_UFC_STALL_CYCLES_UBWC_WR_FLAG), 1108 FD7_COUNTABLE(PERF_UFC_STALL_CYCLES_UBWC_FLAG_RTN), 1109 FD7_COUNTABLE(PERF_UFC_STALL_CYCLES_UBWC_EVENT), 1110 FD7_COUNTABLE(PERF_UFC_LRZ_PREFETCH_STALLED_CYCLES), 1111 FD7_COUNTABLE(PERF_UFC_CRE_PREFETCH_STALLED_CYCLES), 1112 FD7_COUNTABLE(PERF_UFC_SPTP_PREFETCH_STALLED_CYCLES), 1113 FD7_COUNTABLE(PERF_UFC_UBWC_RD_STALLED_CYCLES), 1114 FD7_COUNTABLE(PERF_UFC_UBWC_WR_STALLED_CYCLES), 1115 FD7_COUNTABLE(PERF_UFC_PREFETCH_STALLED_CYCLES), 1116 FD7_COUNTABLE(PERF_UFC_EVICTION_STALLED_CYCLES), 1117 FD7_COUNTABLE(PERF_UFC_LOCK_STALLED_CYCLES), 1118 FD7_COUNTABLE(PERF_UFC_MISS_LATENCY_CYCLES), 1119 FD7_COUNTABLE(PERF_UFC_MISS_LATENCY_SAMPLES), 1120 FD7_COUNTABLE(PERF_UFC_UBWC_REQ_STALLED_CYCLES), 1121 FD7_COUNTABLE(PERF_UFC_TP_HINT_TAG_MISS), 1122 FD7_COUNTABLE(PERF_UFC_TP_HINT_TAG_HIT_RDY), 1123 FD7_COUNTABLE(PERF_UFC_TP_HINT_TAG_HIT_NRDY), 1124 FD7_COUNTABLE(PERF_UFC_TP_HINT_IS_FCLEAR), 1125 FD7_COUNTABLE(PERF_UFC_TP_HINT_IS_ALPHA0), 1126 FD7_COUNTABLE(PERF_UFC_SP_L1_FILTER_HIT), 1127 FD7_COUNTABLE(PERF_UFC_SP_L1_FILTER_MISS), 1128 FD7_COUNTABLE(PERF_UFC_SP_L1_FILTER_REQUESTS), 1129 FD7_COUNTABLE(PERF_UFC_TP_L1_TAG_HIT_RDY), 1130 FD7_COUNTABLE(PERF_UFC_TP_L1_TAG_HIT_NRDY), 1131 FD7_COUNTABLE(PERF_UFC_TP_L1_TAG_MISS), 1132 FD7_COUNTABLE(PERF_UFC_TP_L1_FILTER_REQUESTS), 1133 }; 1134 1135 static const struct fd_perfcntr_counter bv_cp_counters[] = { 1136 FD7_COUNTER(REG7(CP_BV_PERFCTR_CP_SEL(0)), REG7(RBBM_PERFCTR2_CP(0))), 1137 FD7_COUNTER(REG7(CP_BV_PERFCTR_CP_SEL(1)), REG7(RBBM_PERFCTR2_CP(1))), 1138 FD7_COUNTER(REG7(CP_BV_PERFCTR_CP_SEL(2)), REG7(RBBM_PERFCTR2_CP(2))), 1139 FD7_COUNTER(REG7(CP_BV_PERFCTR_CP_SEL(3)), REG7(RBBM_PERFCTR2_CP(3))), 1140 FD7_COUNTER(REG7(CP_BV_PERFCTR_CP_SEL(4)), REG7(RBBM_PERFCTR2_CP(4))), 1141 FD7_COUNTER(REG7(CP_BV_PERFCTR_CP_SEL(5)), REG7(RBBM_PERFCTR2_CP(5))), 1142 FD7_COUNTER(REG7(CP_BV_PERFCTR_CP_SEL(6)), REG7(RBBM_PERFCTR2_CP(6))), 1143 }; 1144 1145 static const struct fd_perfcntr_counter bv_pc_counters[] = { 1146 FD7_COUNTER(REG7(PC_PERFCTR_PC_SEL(8)), REG7(RBBM_PERFCTR_BV_PC(0))), 1147 FD7_COUNTER(REG7(PC_PERFCTR_PC_SEL(9)), REG7(RBBM_PERFCTR_BV_PC(1))), 1148 FD7_COUNTER(REG7(PC_PERFCTR_PC_SEL(10)), REG7(RBBM_PERFCTR_BV_PC(2))), 1149 FD7_COUNTER(REG7(PC_PERFCTR_PC_SEL(11)), REG7(RBBM_PERFCTR_BV_PC(3))), 1150 FD7_COUNTER(REG7(PC_PERFCTR_PC_SEL(12)), REG7(RBBM_PERFCTR_BV_PC(4))), 1151 FD7_COUNTER(REG7(PC_PERFCTR_PC_SEL(13)), REG7(RBBM_PERFCTR_BV_PC(5))), 1152 FD7_COUNTER(REG7(PC_PERFCTR_PC_SEL(14)), REG7(RBBM_PERFCTR_BV_PC(6))), 1153 FD7_COUNTER(REG7(PC_PERFCTR_PC_SEL(15)), REG7(RBBM_PERFCTR_BV_PC(7))), 1154 }; 1155 1156 static const struct fd_perfcntr_counter bv_vfd_counters[] = { 1157 FD7_COUNTER(REG7(VFD_PERFCTR_VFD_SEL(8)), REG7(RBBM_PERFCTR_BV_VFD(0))), 1158 FD7_COUNTER(REG7(VFD_PERFCTR_VFD_SEL(9)), REG7(RBBM_PERFCTR_BV_VFD(1))), 1159 FD7_COUNTER(REG7(VFD_PERFCTR_VFD_SEL(10)), REG7(RBBM_PERFCTR_BV_VFD(2))), 1160 FD7_COUNTER(REG7(VFD_PERFCTR_VFD_SEL(11)), REG7(RBBM_PERFCTR_BV_VFD(3))), 1161 FD7_COUNTER(REG7(VFD_PERFCTR_VFD_SEL(12)), REG7(RBBM_PERFCTR_BV_VFD(4))), 1162 FD7_COUNTER(REG7(VFD_PERFCTR_VFD_SEL(13)), REG7(RBBM_PERFCTR_BV_VFD(5))), 1163 FD7_COUNTER(REG7(VFD_PERFCTR_VFD_SEL(14)), REG7(RBBM_PERFCTR_BV_VFD(6))), 1164 FD7_COUNTER(REG7(VFD_PERFCTR_VFD_SEL(15)), REG7(RBBM_PERFCTR_BV_VFD(7))), 1165 }; 1166 1167 static const struct fd_perfcntr_counter bv_vpc_counters[] = { 1168 FD7_COUNTER(REG7(VPC_PERFCTR_VPC_SEL(6)), REG7(RBBM_PERFCTR_BV_VPC(0))), 1169 FD7_COUNTER(REG7(VPC_PERFCTR_VPC_SEL(7)), REG7(RBBM_PERFCTR_BV_VPC(1))), 1170 FD7_COUNTER(REG7(VPC_PERFCTR_VPC_SEL(8)), REG7(RBBM_PERFCTR_BV_VPC(2))), 1171 FD7_COUNTER(REG7(VPC_PERFCTR_VPC_SEL(9)), REG7(RBBM_PERFCTR_BV_VPC(3))), 1172 FD7_COUNTER(REG7(VPC_PERFCTR_VPC_SEL(10)), REG7(RBBM_PERFCTR_BV_VPC(4))), 1173 FD7_COUNTER(REG7(VPC_PERFCTR_VPC_SEL(11)), REG7(RBBM_PERFCTR_BV_VPC(5))), 1174 }; 1175 1176 static const struct fd_perfcntr_counter bv_tp_counters[] = { 1177 FD7_COUNTER(REG7(TPL1_PERFCTR_TP_SEL(12)), REG7(RBBM_PERFCTR2_TP(0))), 1178 FD7_COUNTER(REG7(TPL1_PERFCTR_TP_SEL(13)), REG7(RBBM_PERFCTR2_TP(1))), 1179 FD7_COUNTER(REG7(TPL1_PERFCTR_TP_SEL(14)), REG7(RBBM_PERFCTR2_TP(2))), 1180 FD7_COUNTER(REG7(TPL1_PERFCTR_TP_SEL(15)), REG7(RBBM_PERFCTR2_TP(3))), 1181 FD7_COUNTER(REG7(TPL1_PERFCTR_TP_SEL(16)), REG7(RBBM_PERFCTR2_TP(4))), 1182 FD7_COUNTER(REG7(TPL1_PERFCTR_TP_SEL(17)), REG7(RBBM_PERFCTR2_TP(5))), 1183 }; 1184 1185 static const struct fd_perfcntr_counter bv_sp_counters[] = { 1186 FD7_COUNTER(REG7(SP_PERFCTR_SP_SEL(24)), REG7(RBBM_PERFCTR2_SP(0))), 1187 FD7_COUNTER(REG7(SP_PERFCTR_SP_SEL(25)), REG7(RBBM_PERFCTR2_SP(1))), 1188 FD7_COUNTER(REG7(SP_PERFCTR_SP_SEL(26)), REG7(RBBM_PERFCTR2_SP(2))), 1189 FD7_COUNTER(REG7(SP_PERFCTR_SP_SEL(27)), REG7(RBBM_PERFCTR2_SP(3))), 1190 FD7_COUNTER(REG7(SP_PERFCTR_SP_SEL(28)), REG7(RBBM_PERFCTR2_SP(4))), 1191 FD7_COUNTER(REG7(SP_PERFCTR_SP_SEL(29)), REG7(RBBM_PERFCTR2_SP(5))), 1192 FD7_COUNTER(REG7(SP_PERFCTR_SP_SEL(30)), REG7(RBBM_PERFCTR2_SP(6))), 1193 FD7_COUNTER(REG7(SP_PERFCTR_SP_SEL(31)), REG7(RBBM_PERFCTR2_SP(7))), 1194 FD7_COUNTER(REG7(SP_PERFCTR_SP_SEL(32)), REG7(RBBM_PERFCTR2_SP(8))), 1195 FD7_COUNTER(REG7(SP_PERFCTR_SP_SEL(33)), REG7(RBBM_PERFCTR2_SP(9))), 1196 FD7_COUNTER(REG7(SP_PERFCTR_SP_SEL(34)), REG7(RBBM_PERFCTR2_SP(10))), 1197 FD7_COUNTER(REG7(SP_PERFCTR_SP_SEL(35)), REG7(RBBM_PERFCTR2_SP(11))), 1198 }; 1199 1200 static const struct fd_perfcntr_counter bv_ufc_counters[] = { 1201 FD7_COUNTER(REG7(RB_PERFCTR_UFC_SEL(4)), REG7(RBBM_PERFCTR2_UFC(0))), 1202 FD7_COUNTER(REG7(RB_PERFCTR_UFC_SEL(5)), REG7(RBBM_PERFCTR2_UFC(1))), 1203 }; 1204 1205 static const struct fd_perfcntr_counter bv_tse_counters[] = { 1206 FD7_COUNTER(REG6(GRAS_PERFCTR_TSE_SEL(0)), REG7(RBBM_PERFCTR_BV_TSE(0))), 1207 FD7_COUNTER(REG6(GRAS_PERFCTR_TSE_SEL(1)), REG7(RBBM_PERFCTR_BV_TSE(1))), 1208 FD7_COUNTER(REG6(GRAS_PERFCTR_TSE_SEL(2)), REG7(RBBM_PERFCTR_BV_TSE(2))), 1209 FD7_COUNTER(REG6(GRAS_PERFCTR_TSE_SEL(3)), REG7(RBBM_PERFCTR_BV_TSE(3))), 1210 }; 1211 1212 static const struct fd_perfcntr_counter bv_ras_counters[] = { 1213 FD7_COUNTER(REG6(GRAS_PERFCTR_RAS_SEL(0)), REG7(RBBM_PERFCTR_BV_RAS(0))), 1214 FD7_COUNTER(REG6(GRAS_PERFCTR_RAS_SEL(1)), REG7(RBBM_PERFCTR_BV_RAS(1))), 1215 FD7_COUNTER(REG6(GRAS_PERFCTR_RAS_SEL(2)), REG7(RBBM_PERFCTR_BV_RAS(2))), 1216 FD7_COUNTER(REG6(GRAS_PERFCTR_RAS_SEL(3)), REG7(RBBM_PERFCTR_BV_RAS(3))), 1217 }; 1218 1219 static const struct fd_perfcntr_counter bv_lrz_counters[] = { 1220 FD7_COUNTER(REG6(GRAS_PERFCTR_LRZ_SEL(0)), REG7(RBBM_PERFCTR_BV_LRZ(0))), 1221 FD7_COUNTER(REG6(GRAS_PERFCTR_LRZ_SEL(1)), REG7(RBBM_PERFCTR_BV_LRZ(1))), 1222 FD7_COUNTER(REG6(GRAS_PERFCTR_LRZ_SEL(2)), REG7(RBBM_PERFCTR_BV_LRZ(2))), 1223 FD7_COUNTER(REG6(GRAS_PERFCTR_LRZ_SEL(3)), REG7(RBBM_PERFCTR_BV_LRZ(3))), 1224 }; 1225 1226 static const struct fd_perfcntr_counter bv_hlsq_counters[] = { 1227 FD7_COUNTER(REG7(SP_PERFCTR_HLSQ_SEL(0)), REG7(RBBM_PERFCTR2_HLSQ(0))), 1228 FD7_COUNTER(REG7(SP_PERFCTR_HLSQ_SEL(1)), REG7(RBBM_PERFCTR2_HLSQ(1))), 1229 FD7_COUNTER(REG7(SP_PERFCTR_HLSQ_SEL(2)), REG7(RBBM_PERFCTR2_HLSQ(2))), 1230 FD7_COUNTER(REG7(SP_PERFCTR_HLSQ_SEL(3)), REG7(RBBM_PERFCTR2_HLSQ(3))), 1231 FD7_COUNTER(REG7(SP_PERFCTR_HLSQ_SEL(4)), REG7(RBBM_PERFCTR2_HLSQ(4))), 1232 FD7_COUNTER(REG7(SP_PERFCTR_HLSQ_SEL(5)), REG7(RBBM_PERFCTR2_HLSQ(5))), 1233 }; 1234 1235 const struct fd_perfcntr_group a7xx_perfcntr_groups[] = { 1236 GROUP("CP", cp_counters, cp_countables), 1237 GROUP("RBBM", rbbm_counters, rbbm_countables), 1238 GROUP("PC", pc_counters, pc_countables), 1239 GROUP("VFD", vfd_counters, vfd_countables), 1240 GROUP("HLSQ", hlsq_counters, hlsq_countables), 1241 GROUP("VPC", vpc_counters, vpc_countables), 1242 GROUP("TSE", tse_counters, tse_countables), 1243 GROUP("RAS", ras_counters, ras_countables), 1244 GROUP("UCHE", uche_counters, uche_countables), 1245 GROUP("TP", tp_counters, tp_countables), 1246 GROUP("SP", sp_counters, sp_countables), 1247 GROUP("RB", rb_counters, rb_countables), 1248 GROUP("VSC", vsc_counters, vsc_countables), 1249 GROUP("CCU", ccu_counters, ccu_countables), 1250 GROUP("LRZ", lrz_counters, lrz_countables), 1251 GROUP("CMP", cmp_counters, cmp_countables), 1252 GROUP("UFC", ufc_counters, ufc_countables), 1253 GROUP("BV_CP", bv_cp_counters, cp_countables), 1254 GROUP("BV_PC", bv_pc_counters, pc_countables), 1255 GROUP("BV_VFD", bv_vfd_counters, vfd_countables), 1256 GROUP("BV_VPC", bv_vpc_counters, vpc_countables), 1257 GROUP("BV_TP", bv_tp_counters, tp_countables), 1258 GROUP("BV_SP", bv_sp_counters, sp_countables), 1259 GROUP("BV_UFC", bv_ufc_counters, ufc_countables), 1260 GROUP("BV_TSE", bv_tse_counters, tse_countables), 1261 GROUP("BV_RAS", bv_ras_counters, ras_countables), 1262 GROUP("BV_LRZ", bv_lrz_counters, lrz_countables), 1263 GROUP("BV_HLSQ", bv_hlsq_counters, hlsq_countables), 1264 }; 1265 1266 const unsigned a7xx_num_perfcntr_groups = ARRAY_SIZE(a7xx_perfcntr_groups); 1267 1268