xref: /aosp_15_r20/external/mesa3d/src/freedreno/isa/ir3-common.xml (revision 6104692788411f58d303aa86923a9ff6ecaded22) 
1<?xml version="1.0" encoding="UTF-8"?>
2<!--
3Copyright © 2020 Google, Inc.
4
5Permission is hereby granted, free of charge, to any person obtaining a
6copy of this software and associated documentation files (the "Software"),
7to deal in the Software without restriction, including without limitation
8the rights to use, copy, modify, merge, publish, distribute, sublicense,
9and/or sell copies of the Software, and to permit persons to whom the
10Software is furnished to do so, subject to the following conditions:
11
12The above copyright notice and this permission notice (including the next
13paragraph) shall be included in all copies or substantial portions of the
14Software.
15
16THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22SOFTWARE.
23 -->
24
25<isa>
26
27<!--
28	Helpers for cat2/cat3 nop encoding, which re-uses the SRC1_R/SRC2_R
29	fields to encode a # of nop delay slots following the instruction.
30 -->
31
32<expr name="#cat2-cat3-nop-encoding">
33	(({SRC1_R} != 0) || ({SRC2_R} != 0)) &amp;&amp; ({REPEAT} == 0)
34</expr>
35
36<expr name="#cat2-cat3-nop-value">
37	{SRC1_R} | ({SRC2_R} &lt;&lt; 1)
38</expr>
39
40<!--
41	Source/Dest gpr encoding.  In the gpr case, this handles the special
42	cases (p0.x/a0.x)
43 -->
44
45<expr name="#reg-gpr-a0">
46	{GPR} == 61 /* a0.* */
47</expr>
48
49<expr name="#reg-gpr-p0">
50	{GPR} == 62 /* p0.x */
51</expr>
52
53<bitset name="#reg-gpr" size="8">
54	<override expr="#reg-gpr-a0">
55		<display>
56			a0.{SWIZ}
57		</display>
58		<assert low="2" high="7">111101</assert>
59	</override>
60	<override expr="#reg-gpr-p0">
61		<display>
62			p0.{SWIZ}
63		</display>
64		<assert low="2" high="7">111110</assert>
65	</override>
66	<display>
67		r{GPR}.{SWIZ}
68	</display>
69	<field name="SWIZ" low="0" high="1" type="#swiz"/>
70	<field name="GPR" low="2"  high="7" type="uint"/>
71	<encode type="struct ir3_register *">
72		<map name="GPR">src->num >> 2</map>
73		<map name="SWIZ">src->num &amp; 0x3</map>
74	</encode>
75</bitset>
76
77<bitset name="#reg-const" size="11">
78	<display>
79		c{CONST}.{SWIZ}
80	</display>
81	<field name="SWIZ" low="0" high="1" type="#swiz"/>
82	<field name="CONST" low="2" high="10" type="uint"/>
83	<encode type="struct ir3_register *">
84		<map name="CONST">src->num >> 2</map>
85		<map name="SWIZ">src->num &amp; 0x3</map>
86	</encode>
87</bitset>
88
89<expr name="#offset-zero">
90	{OFFSET} == 0
91</expr>
92
93<bitset name="#reg-relative-gpr" size="10">
94	<override expr="#offset-zero">
95		<display>
96			r&lt;a0.x&gt;
97		</display>
98	</override>
99	<display>
100		r&lt;a0.x + {OFFSET}&gt;
101	</display>
102	<field name="OFFSET" low="0" high="9" type="int"/>
103	<encode type="struct ir3_register *">
104		<map name="OFFSET">src->array.offset</map>
105	</encode>
106</bitset>
107
108<bitset name="#reg-relative-const" size="10">
109	<override expr="#offset-zero">
110		<display>
111			c&lt;a0.x&gt;
112		</display>
113	</override>
114	<display>
115		c&lt;a0.x + {OFFSET}&gt;
116	</display>
117	<field name="OFFSET" low="0" high="9" type="int"/>
118	<encode type="struct ir3_register *">
119		<map name="OFFSET">src->array.offset</map>
120	</encode>
121</bitset>
122
123<!--
124	Source Register encoding, used in cat2 and cat4 where a src can be
125	either gpr/const/relative
126 -->
127
128<bitset name="#multisrc" size="16">
129	<doc>
130		Encoding for instruction source which can be GPR/CONST/IMMED
131		or relative GPR/CONST.
132	</doc>
133	<encode type="struct ir3_register *" case-prefix="REG_">
134		<map name="ABSNEG">extract_ABSNEG(src)</map>
135		<map name="SRC">src</map>
136	</encode>
137</bitset>
138
139<bitset name="#mulitsrc-immed" extends="#multisrc">
140	<override expr="#multisrc-half">
141		<display>
142			{ABSNEG}{SRC_R}h({IMMED})
143		</display>
144	</override>
145	<display>
146		{ABSNEG}{SRC_R}{IMMED}
147	</display>
148	<field name="IMMED" low="0"  high="10" type="int"/>
149	<pattern low="11" high="13">100</pattern>
150	<field name="ABSNEG" low="14" high="15" type="#absneg"/>
151	<encode>
152		<map name="IMMED">extract_reg_iim(src)</map>
153	</encode>
154</bitset>
155
156<bitset name="#mulitsrc-immed-flut" extends="#multisrc">
157	<doc>
158		Immediate with int->float lookup table:
159
160			0  -> 0.0
161			1  -> 0.5
162			2  -> 1.0
163			3  -> 2.0
164			4  -> e
165			5  -> pi
166			6  -> 1/pi
167			7  -> 1/log2(e)
168			8  -> log2(e)
169			9  -> 1/log2(10)
170			10 -> log2(10)
171			11 -> 4.0
172
173	</doc>
174	<field name="IMMED" low="0"  high="9" type="#flut"/>
175	<pattern low="11" high="13">101</pattern>
176	<field name="ABSNEG" low="14" high="15" type="#absneg"/>
177	<encode>
178		<map name="IMMED">extract_reg_uim(src)</map>
179	</encode>
180</bitset>
181
182<bitset name="#multisrc-immed-flut-full" extends="#mulitsrc-immed-flut">
183	<display>
184		{ABSNEG}{SRC_R}{IMMED}
185	</display>
186	<pattern pos="10">0</pattern>
187</bitset>
188
189<bitset name="#multisrc-immed-flut-half" extends="#mulitsrc-immed-flut">
190	<display>
191		{ABSNEG}{SRC_R}h{IMMED}
192	</display>
193	<pattern pos="10">1</pattern>
194</bitset>
195
196<expr name="#multisrc-half">
197	!{FULL}
198</expr>
199
200<bitset name="#multisrc-gpr" extends="#multisrc">
201	<display>
202		{LAST}{ABSNEG}{SRC_R}{HALF}{SRC}
203	</display>
204	<derived name="HALF" expr="#multisrc-half" type="bool" display="h"/>
205	<field name="SRC" low="0" high="7" type="#reg-gpr"/>
206	<pattern low="8" high="9">00</pattern>
207	<field name="LAST" pos="10" type="bool" display="(last)"/>
208	<pattern low="11" high="13">000</pattern>
209	<field name="ABSNEG" low="14" high="15" type="#absneg"/>
210	<encode>
211		<map name="LAST">!!(src->flags &amp; IR3_REG_LAST_USE)</map>
212	</encode>
213</bitset>
214
215<bitset name="#multisrc-const" extends="#multisrc">
216	<display>
217		{ABSNEG}{SRC_R}{HALF}{SRC}
218	</display>
219	<derived name="HALF" expr="#multisrc-half" type="bool" display="h"/>
220	<field name="SRC" low="0" high="10" type="#reg-const"/>
221	<pattern low="11" high="13">x10</pattern>
222	<field name="ABSNEG" low="14" high="15" type="#absneg"/>
223</bitset>
224
225<bitset name="#multisrc-relative" extends="#multisrc">
226	<pattern low="11" high="13">001</pattern>
227	<field name="ABSNEG" low="14" high="15" type="#absneg"/>
228</bitset>
229
230<bitset name="#multisrc-relative-gpr" extends="#multisrc-relative">
231	<display>
232		{ABSNEG}{SRC_R}{HALF}{SRC}
233	</display>
234	<derived name="HALF" expr="#multisrc-half" type="bool" display="h"/>
235	<field name="SRC" low="0" high="9" type="#reg-relative-gpr"/>
236	<pattern pos="10">0</pattern>
237</bitset>
238
239<bitset name="#multisrc-relative-const" extends="#multisrc-relative">
240	<display>
241		{ABSNEG}{SRC_R}{HALF}{SRC}
242	</display>
243	<derived name="HALF" expr="#multisrc-half" type="bool" display="h"/>
244	<field name="SRC" low="0" high="9" type="#reg-relative-const"/>
245	<pattern pos="10">1</pattern>
246</bitset>
247
248<!--
249	For cat2/cat4, the dst reg is full precision if {FULL} == {DEST_CONV}
250	In addition, for cat2 instructions that can write p0.x (cmps.*, and.b,
251	xor.b, etc), p0.x is never half (DEST_CONV is ignored)
252 -->
253<expr name="#dest-half">
254	({FULL} == {DST_CONV}) &amp;&amp; ({DST} &lt;= 0xf7 /* p0.x */)
255</expr>
256
257<expr name="#true">
258	1
259</expr>
260
261<expr name="#false">
262	0
263</expr>
264
265<!-- These make #true/#false a bit redundant, but I guess keep them for clarity -->
266<expr name="#zero">
267	0
268</expr>
269<expr name="#one">
270	1
271</expr>
272<expr name="#two">
273	2
274</expr>
275
276<!--
277	Enums used in various places:
278 -->
279
280<enum name="#rptN">
281	<value val="0" display=""/>
282	<value val="1" display="(rpt1)"/>
283	<value val="2" display="(rpt2)"/>
284	<value val="3" display="(rpt3)"/>
285	<value val="4" display="(rpt4)"/>
286	<value val="5" display="(rpt5)"/>
287</enum>
288
289<enum name="#cond">
290	<value val="0" display="lt"/>
291	<value val="1" display="le"/>
292	<value val="2" display="gt"/>
293	<value val="3" display="ge"/>
294	<value val="4" display="eq"/>
295	<value val="5" display="ne"/>
296</enum>
297
298<enum name="#swiz">
299	<value val="0" display="x"/>
300	<value val="1" display="y"/>
301	<value val="2" display="z"/>
302	<value val="3" display="w"/>
303</enum>
304
305<enum name="#type">
306	<value val="0" display="f16"/>
307	<value val="1" display="f32"/>
308	<value val="2" display="u16"/>
309	<value val="3" display="u32"/>
310	<value val="4" display="s16"/>
311	<value val="5" display="s32"/>
312	<value val="6" display="u8"/>
313	<value val="7" display="u8_32"/>
314</enum>
315
316<expr name="#type-half">
317	({TYPE} == 0) /* f16 */ ||
318	({TYPE} == 2) /* u16 */ ||
319	({TYPE} == 4) /* s16 */ ||
320	({TYPE} == 6) /* u8 */
321</expr>
322
323<enum name="#absneg">
324	<value val="0" display=""/>
325	<value val="1" display="(neg)"/>
326	<value val="2" display="(abs)"/>
327	<value val="3" display="(absneg)"/>
328</enum>
329
330<enum name="#flut">
331	<doc>int to float lookup table</doc>
332	<value val="0"  display="(0.0)"/>
333	<value val="1"  display="(0.5)"/>
334	<value val="2"  display="(1.0)"/>
335	<value val="3"  display="(2.0)"/>
336	<value val="4"  display="(e)"/>
337	<value val="5"  display="(pi)"/>
338	<value val="6"  display="(1/pi)"/>
339	<value val="7"  display="(1/log2(e))"/>
340	<value val="8"  display="(log2(e))"/>
341	<value val="9"  display="(1/log2(10))"/>
342	<value val="10" display="(log2(10))"/>
343	<value val="11" display="(4.0)"/>
344</enum>
345
346<enum name="#wrmask">
347	<value val="0"  display=""/>
348	<value val="1"  display="x"/>
349	<value val="2"  display="y"/>
350	<value val="3"  display="xy"/>
351	<value val="4"  display="z"/>
352	<value val="5"  display="xz"/>
353	<value val="6"  display="yz"/>
354	<value val="7"  display="xyz"/>
355	<value val="8"  display="w"/>
356	<value val="9"  display="xw"/>
357	<value val="10" display="yw"/>
358	<value val="11" display="xyw"/>
359	<value val="12" display="zw"/>
360	<value val="13" display="xzw"/>
361	<value val="14" display="yzw"/>
362	<value val="15" display="xyzw"/>
363</enum>
364
365</isa>
366