1 /*
2 * Copyright © 2016 Broadcom
3 * Copyright © 2020 Google LLC
4 * SPDX-License-Identifier: MIT
5 */
6
7 /* Unit test for disassembly of instructions.
8 *
9 * The goal is to take instructions we've seen the blob produce, and test that
10 * we can disassemble them correctly. For the next person investigating the
11 * behavior of this instruction, please include the testcase it was generated
12 * from, and the qcom disassembly as a comment if it differs from what we
13 * produce.
14 */
15
16 #include <stdio.h>
17 #include <stdlib.h>
18 #include <string.h>
19 #include "util/macros.h"
20 #include "util/u_vector.h"
21
22 #include "ir3.h"
23 #include "ir3_assembler.h"
24 #include "ir3_shader.h"
25
26 #include "freedreno/isa/ir3-isa.h"
27
28 /* clang-format off */
29 /* Note: @anholt's 4xx disasm was done on an a418 Nexus 5x */
30 #define INSTR_4XX(i, d, ...) { .gpu_id = 420, .instr = #i, .instr_raw = 0, .expected = d, __VA_ARGS__ }
31 #define INSTR_5XX(i, d, ...) { .gpu_id = 540, .instr = #i, .instr_raw = 0, .expected = d, __VA_ARGS__ }
32 #define INSTR_6XX(i, d, ...) { .gpu_id = 630, .instr = #i, .instr_raw = 0, .expected = d, __VA_ARGS__ }
33 #define INSTR_6XX_RAW(i, d, ...) { .gpu_id = 630, .instr = NULL, .instr_raw = i, .expected = d, __VA_ARGS__ }
34 #define INSTR_7XX(i, d, ...) { .chip_id = 0x07030001, .instr = #i, .instr_raw = 0, .expected = d, __VA_ARGS__ }
35 #define INSTR_7XX_RAW(i, d, ...) { .chip_id = 0x07030001, .instr = NULL, .instr_raw = i, .expected = d, __VA_ARGS__ }
36 /* clang-format on */
37
38 static const struct test {
39 int gpu_id;
40 int chip_id;
41 const char *instr;
42 uint64_t instr_raw;
43 const char *expected;
44 /**
45 * Do we expect asm parse fail (ie. for things not (yet) supported by
46 * ir3_parser.y)
47 */
48 bool parse_fail;
49 } tests[] = {
50 /* clang-format off */
51 /* cat0 */
52 INSTR_6XX(00000000_00000000, "nop"),
53 INSTR_6XX(00000200_00000000, "(rpt2)nop"),
54 INSTR_6XX(00010000_00000000, "(eq)nop"),
55 INSTR_6XX(03000000_00000000, "end"),
56 INSTR_6XX(00800000_00000004, "br p0.x, #4"),
57 INSTR_6XX(00800000_fffffffc, "br p0.x, #-4"),
58 INSTR_6XX(00900000_00000003, "br !p0.x, #3"),
59 INSTR_6XX(03820000_00000015, "shps #21"), /* emit */
60 INSTR_6XX(04021000_00000000, "(ss)shpe"), /* cut */
61 INSTR_6XX(02220000_00000004, "getlast.w8 #4"),
62 INSTR_6XX(02820000_00000014, "getone #20"), /* kill p0.x */
63 INSTR_6XX(00906020_00000007, "brao !p0.x, !p0.y, #7"),
64 INSTR_6XX(00804040_00000003, "braa p0.x, p0.y, #3"),
65 INSTR_6XX(07820000_00000000, "prede"),
66 INSTR_6XX(00800063_0000001e, "brac.3 #30"),
67 INSTR_6XX(06820000_00000000, "predt"),
68 INSTR_6XX(07020000_00000000, "predf"),
69 INSTR_6XX(07820000_00000000, "prede"),
70
71 /* cat1 */
72 INSTR_6XX(20244000_00000020, "mov.f32f32 r0.x, c8.x"),
73 INSTR_6XX(20200000_00000020, "mov.f16f16 hr0.x, hc8.x"),
74 INSTR_6XX(20150000_00000000, "cov.s32s16 hr0.x, r0.x"),
75 INSTR_6XX(20156004_00000c11, "(ul)mov.s32s32 r1.x, c<a0.x + 17>"),
76 INSTR_6XX(201100f4_00000000, "mova a0.x, hr0.x"),
77 INSTR_6XX(20244905_00000410, "(rpt1)mov.f32f32 r1.y, (r)c260.x"),
78 INSTR_6XX(20174004_00000008, "mov.s32s32 r<a0.x + 4>, r2.x"),
79 INSTR_6XX(20130000_00000005, "mov.s16s16 hr<a0.x>, hr1.y"),
80 INSTR_6XX(20110004_00000800, "mov.s16s16 hr1.x, hr<a0.x>"),
81 /* dEQP-VK.subgroups.ballot.compute.compute */
82 INSTR_6XX(260cc3c0_00000000, "movmsk.w128 r48.x"), /* movmsk.w128 sr48.x */
83
84 INSTR_6XX(240cc004_00030201, "swz.u32u32 r1.x, r0.w, r0.y, r0.z"),
85 INSTR_6XX(2400c105_04030201, "gat.f16u32 r1.y, hr0.y, hr0.z, hr0.w, hr1.x"),
86 INSTR_6XX(240c0205_04030201, "sct.u32f16 hr1.y, hr0.z, hr0.w, hr1.x, r0.y"),
87 INSTR_6XX(2400c205_04030201, "sct.f16u32 r1.y, r0.z, r0.w, r1.x, hr0.y"),
88
89 INSTR_6XX(20510005_0000ffff, "mov.s16s16 hr1.y, -1"),
90 INSTR_6XX(20400005_00003900, "mov.f16f16 hr1.y, h(0.625000)"),
91 INSTR_6XX(20400006_00003800, "mov.f16f16 hr1.z, h(0.500000)"),
92 INSTR_6XX(204880f5_00000000, "mova1 a1.x, 0"),
93
94 INSTR_7XX(2004c005_00000405, "cov.f32u32 r1.y, (last)r1.y"),
95
96 /* cat2 */
97 INSTR_6XX(40104002_0c210001, "add.f hr0.z, r0.y, c<a0.x + 33>"),
98 INSTR_6XX(40b80804_10408004, "(nop3) cmps.f.lt r1.x, (abs)r1.x, c16.x"),
99 INSTR_6XX(47308a02_00002000, "(rpt2)bary.f (ei)r0.z, (r)0, r0.x"),
100 INSTR_6XX(47348000_00002000, "flat.b (ei)r0.x, 0, r0.x"),
101 INSTR_6XX(43480801_00008001, "(nop3) absneg.s hr0.y, (abs)hr0.y"),
102 INSTR_6XX(50600004_2c010004, "(sy)mul.f hr1.x, hr1.x, h(0.5)"),
103 INSTR_6XX(42280807_27ff0000, "(nop3) add.s hr1.w, hr0.x, h(-1)"),
104 INSTR_6XX(40a500f8_2c000004, "cmps.f.ne p0.x, hr1.x, h(0.0)"),
105 INSTR_6XX(438000f8_20010009, "and.b p0.x, hr2.y, h(1)"),
106 INSTR_6XX(438000f9_00020001, "and.b p0.y, hr0.y, hr0.z"),
107 INSTR_6XX(40080902_50200006, "(rpt1)add.f hr0.z, (r)hr1.z, (neg)(r)hc8.x"),
108 INSTR_6XX(42380c01_00040001, "(sat)(nop3) add.s r0.y, r0.y, r1.x"),
109 INSTR_6XX(42480000_48801086, "(nop2) sub.u hr0.x, hc33.z, (neg)hr<a0.x + 128>"),
110 INSTR_6XX(46b00001_00001020, "clz.b r0.y, c8.x"),
111 INSTR_6XX(46700009_00000009, "bfrev.b r2.y, r2.y"),
112
113 INSTR_7XX(42380800_04010400, "(nop3) add.s r0.x, (last)r0.x, (last)r0.y"),
114 INSTR_7XX(42930000_04000406, "cmps.u.ge r0.x, (last)r1.z, (last)r0.x"),
115
116 /* cat3 */
117 INSTR_6XX(66000000_10421041, "sel.f16 hr0.x, hc16.y, hr0.x, hc16.z"),
118 INSTR_6XX(64848109_109a9099, "(rpt1)sel.b32 r2.y, c38.y, (r)r2.y, c38.z"),
119 INSTR_6XX(64810904_30521036, "(rpt1)sel.b32 r1.x, (r)c13.z, r0.z, (r)c20.z"),
120 INSTR_6XX(64818902_20041032, "(rpt1)sel.b32 r0.z, (r)c12.z, r0.w, (r)r1.x"),
121 INSTR_6XX(63820005_10315030, "mad.f32 r1.y, (neg)c12.x, r1.x, c12.y"),
122 INSTR_6XX(62050009_00091000, "mad.u24 r2.y, c0.x, r2.z, r2.y"),
123 INSTR_6XX(61828008_00081033, "madsh.m16 r2.x, c12.w, r1.y, r2.x"),
124 INSTR_6XX(65900820_100cb008, "(nop3) shlg hr8.x, 8, hr8.x, 12"), /* (nop3) shlg.b16 hr8.x, (r)8, (r)hr8.x, 12; */
125 INSTR_6XX(65ae085c_0002a001, "(nop3) shlg hr23.x, hr0.y, hr23.x, hr0.z"), /* not seen in blob */
126 INSTR_6XX(65900820_0c0aac05, "(nop3) shlg hr8.x, hc<a0.x + 5>, hr8.x, hc<a0.x + 10>"), /* not seen in blob */
127 INSTR_6XX(65ae0c5c_0002a001, "(nop3) shlg r23.x, r0.y, r23.x, r0.z"), /* (nop3) shlg.b32 r23.x, (r)r0.y, (r)r23.x, r0.z */
128 INSTR_6XX(64018802_0002e003, "(nop3) shrm hr0.z, (neg)hr0.w, hr0.w, hr0.z"),
129 INSTR_6XX(64818802_0002e003, "(nop3) shlm hr0.z, (neg)hr0.w, hr0.w, hr0.z"),
130 INSTR_6XX(65018802_0002e003, "(nop3) shrg hr0.z, (neg)hr0.w, hr0.w, hr0.z"),
131 INSTR_6XX(66018802_0002e003, "(nop3) andg hr0.z, (neg)hr0.w, hr0.w, hr0.z"),
132 INSTR_6XX(67018802_1002e003, "(nop3) wmm hr0.z, (neg)hr0.w, hr0.w, 2"), /* (nop3) wmm.f16f16 hr0.z, (abs)(r)hr0.w, (r)hr0.w, 2 */
133 INSTR_6XX(67018c02_1002e003, "(nop3) wmm.accu hr0.z, (neg)hr0.w, hr0.w, 2"),
134 INSTR_6XX(6701c802_9002a003, "(nop3) wmm r0.z, r0.w, r0.w, 2"), /* (nop3) wmm.f32f32 r0.z, (r)r0.w, (r)r0.w, 2 */
135 /* custom test with qcom_dot8 function from cl_qcom_dot_product8 */
136 INSTR_6XX(66818c02_0002e003, "(sat)(nop3) dp2acc.mixed.low r0.z, r0.w, r0.w, r0.z"), /* (nop3) dp2acc (sat)r0.z, (signed)(low)(r)r0.w, (low)(r)r0.w, r0.z */
137 INSTR_6XX(6681c802_8002a003, "(nop3) dp4acc.unsigned.low r0.z, r0.w, r0.w, (neg)r0.z"), /* (nop3) dp4acc r0.z, (unsigned)(r)r0.w, (r)r0.w, (neg)r0.z */
138
139 INSTR_7XX(61808000_04020400, "madsh.m16 r0.x, (last)r0.x, r0.y, (last)r0.z"),
140 INSTR_7XX(64838806_04088406, "(nop3) sel.b32 r1.z, (last)r1.z, r1.w, (last)r2.x"),
141
142 /* cat4 */
143 INSTR_6XX(8010000a_00000003, "rcp r2.z, r0.w"),
144
145 /* cat5 */
146 /* dEQP-VK.glsl.derivate.dfdx.uniform_if.float_mediump */
147 INSTR_6XX(a3801102_00000001, "dsx (f32)(x)r0.z, r0.x"), /* dsx (f32)(xOOO)r0.z, r0.x */
148 /* dEQP-VK.glsl.derivate.dfdy.uniform_if.float_mediump */
149 INSTR_6XX(a3c01102_00000001, "dsy (f32)(x)r0.z, r0.x"), /* dsy (f32)(xOOO)r0.z, r0.x */
150 /* dEQP-VK.glsl.derivate.dfdxfine.uniform_loop.float_highp */
151 INSTR_6XX(a6001105_00000001, "dsxpp.1 (x)r1.y, r0.x"), /* dsxpp.1 (xOOO)r1.y, r0.x */
152 INSTR_6XX(a6201105_00000001, "dsxpp.1.p (x)r1.y, r0.x"), /* dsxpp.1 (xOOO)r1.y, r0.x */
153
154 INSTR_6XX(a2802f00_00000001, "getsize (u16)(xyzw)hr0.x, r0.x, t#0"),
155 INSTR_6XX(a0c89f04_c4600005, "sam.base1 (f32)(xyzw)r1.x, r0.z, s#3, t#2"), /* sam.s2en.mode6.base1 (f32)(xyzw)r1.x, r0.z, 35 */
156 INSTR_6XX(a1c85f00_c0200005, "getlod.base0 (s32)(xyzw)r0.x, r0.z, s#1, t#0"), /* getlod.s2en.mode6.base0 (s32)(xyzw)r0.x, r0.z, 1 */
157 INSTR_6XX(a1000f00_00000004, "samb (f16)(xyzw)hr0.x, hr0.z, hr0.x, s#0, t#0"),
158 INSTR_6XX(a1000f00_00000003, "samb (f16)(xyzw)hr0.x, r0.y, r0.x, s#0, t#0"),
159 INSTR_6XX(a0c00f00_04400002, "sam (f16)(xyzw)hr0.x, hr0.y, s#2, t#2"),
160 INSTR_6XX(a6c02f00_00000000, "rgetinfo (u16)(xyzw)hr0.x"),
161 INSTR_6XX(a3482f08_c0000000, "getinfo.base0 (u16)(xyzw)hr2.x, t#0"),
162 /* dEQP-GLES31.functional.texture.texture_buffer.render.as_fragment_texture.buffer_size_65536 */
163 INSTR_5XX(a2c03102_00000000, "getbuf (u32)(x)r0.z, t#0"),
164 INSTR_6XX(a0c81f00_e0200005, "sam.base0 (f32)(xyzw)r0.x, r0.z, s#1, a1.x"),
165 INSTR_6XX(a0c81108_e2000001, "sam.base0 (f32)(x)r2.x, r0.x, s#16, a1.x"),
166 INSTR_6XX(a048d107_cc080a07, "isaml.base3 (s32)(x)r1.w, r0.w, r1.y, s#0, t#6"),
167 INSTR_6XX(a048d107_e0080a07, "isaml.base3 (s32)(x)r1.w, r0.w, r1.y, s#0, a1.x"),
168 INSTR_6XX(a1481606_e4803035, "saml.base0 (f32)(yz)r1.z, r6.z, r6.x, s#36, a1.x"),
169
170 INSTR_7XX(a0081f02_e2040001, "isam.base0 (f32)(xyzw)r0.z, r0.x, t#16, a1.x"),
171 INSTR_7XX(a0081f02_e2000001, "isam.base0.1d (f32)(xyzw)r0.z, r0.x, t#16, a1.x"),
172 INSTR_7XX(a148310d_e028302c, "saml.base2 (u32)(x)r3.y, hr5.z, hr6.x, t#1, a1.x"),
173
174 INSTR_7XX(a00c3101_c2040001, "isam.v.base0 (u32)(x)r0.y, r0.x, s#0, t#1"),
175 INSTR_7XX(a00c3101_c2000001, "isam.v.base0.1d (u32)(x)r0.y, r0.x, s#0, t#1"),
176 INSTR_7XX(a02c3f06_c2041003, "isam.v.base0 (u32)(xyzw)r1.z, r0.y+8, s#0, t#1"),
177
178 /* dEQP-VK.subgroups.arithmetic.compute.subgroupadd_float */
179 INSTR_6XX(a7c03102_00100003, "brcst.active.w8 (u32)(x)r0.z, r0.y"), /* brcst.active.w8 (u32)(xOOO)r0.z, r0.y */
180 /* dEQP-VK.subgroups.quad.graphics.subgroupquadbroadcast_int */
181 INSTR_6XX(b7e03107_00000401, "(sy)quad_shuffle.brcst (u32)(x)r1.w, r0.x, r0.z"), /* (sy)quad_shuffle.brcst (u32)(xOOO)r1.w, r0.x, r0.z */
182 /* dEQP-VK.subgroups.quad.graphics.subgroupquadswapdiagonal_int */
183 INSTR_6XX(b7e03104_00180001, "(sy)quad_shuffle.diag (u32)(x)r1.x, r0.x"), /* (sy)quad_shuffle.diag (u32)(xOOO)r1.x, r0.x */
184
185 INSTR_6XX(a7000000_00000000, "tcinv"),
186
187 /* cat6 */
188
189 INSTR_5XX(c6e60000_00010600, "ldgb.untyped.4d.u32.1 r0.x, g[0], r1.x, r0.x"), /* ldgb.a.untyped.1dtype.u32.1 r0.x, g[r1.x], r0.x, 0 */
190 INSTR_5XX(d7660204_02000a01, "(sy)stib.typed.2d.u32.1 g[1], r0.x, r0.z, r1.x"), /* (sy)stib.a.u32.2d.1 g[r1.x], r0.x, r0.z, 1. r1.x is offset in ibo, r0.x is value*/
191 /* dEQP-VK.image.load_store.1d_array.r8g8b8a8_unorm */
192 INSTR_5XX(c1a20006_0600ba01, "ldib.typed.2d.f32.4 r1.z, g[0], r0.z, r1.z"), /* ldib.a.f32.2d.4 r1.z, g[r0.z], r1.z, 0. r0.z is offset in ibo as src. r1.z */
193 /* dEQP-VK.image.load_store.3d.r32g32b32a32_sint */
194 INSTR_5XX(c1aa0003_0500fc01, "ldib.typed.3d.s32.4 r0.w, g[0], r0.w, r1.y"), /* ldib.a.s32.3d.4 r0.w, g[r0.w], r1.y, 0. r0.w is offset in ibo as src, and dst */
195 /* dEQP-VK.binding_model.shader_access.primary_cmd_buf.storage_image.vertex.descriptor_array.3d */
196 INSTR_5XX(c1a20204_0401fc01, "ldib.typed.3d.f32.4 r1.x, g[1], r1.w, r1.x"), /* ldib.a.f32.3d.4 r1.x, g[r1.w], r1.x, 1 */
197 /* dEQP-VK.binding_model.shader_access.secondary_cmd_buf.with_push.storage_texel_buffer.vertex_fragment.single_descriptor.offset_zero */
198 INSTR_5XX(c1a20005_0501be01, "ldib.typed.4d.f32.4 r1.y, g[0], r1.z, r1.y"), /* ldib.a.f32.1dtype.4 r1.y, g[r1.z], r1.y, 0 */
199 /* dEQP-VK.texture.filtering.cube.formats.r8g8b8a8_snorm_nearest */
200 INSTR_5XX(c1a60200_0000ba01, "ldib.typed.2d.u32.4 r0.x, g[1], r0.z, r0.x"), /* ldib.a.u32.2d.4 r0.x, g[r0.z], r0.x, 1 */
201
202 // TODO is this a real instruction? Or float -6.0 ?
203 // INSTR_6XX(c0c00000_00000000, "stg.f16 g[hr0.x], hr0.x, hr0.x", .parse_fail=true),
204 /* dEQP-GLES31.functional.tessellation.invariance.outer_edge_symmetry.isolines_equal_spacing_ccw */
205 INSTR_6XX(c0d20906_02800004, "stg.a.f32 g[r1.x+(r1.z)<<2], r0.z, 2"), /* stg.a.f32 g[r1.x+(r1.z<<2)], r0.z, 2 */
206 INSTR_6XX(c0da052e_01800042, "stg.a.s32 g[r0.z+(r11.z)<<2], r8.y, 1"), /* stg.a.s32 g[r0.z+(r11.z<<2)], r8.y, 1 */
207 INSTR_6XX(c0dc052e_01800042, "stg.a.u8 g[r0.z+(r11.z)<<2], hr8.y, 1"),
208 INSTR_6XX(c0ca0505_03800042, "stg.s32 g[r0.z+5], r8.y, 3"),
209 INSTR_6XX(c0ca0500_03800042, "stg.s32 g[r0.z], r8.y, 3"),
210 INSTR_6XX(c0ca0531_03800242, "stg.s32 g[r0.z+305], r8.y, 3"),
211 INSTR_5XX(c0ce0100_02800000, "stg.u8_32 g[r0.x], r0.x, 2"),
212 INSTR_5XX(c0c00100_02800000, "stg.f16 g[r0.x], hr0.x, 2"),
213
214 /* Customely crafted */
215 INSTR_6XX(c0d61104_01800228, "stg.a.u32 g[r2.x+(r1.x+1)<<2], r5.x, 1"),
216 INSTR_6XX(c0d61104_01802628, "stg.a.u32 g[r2.x+r1.x<<4+3<<2], r5.x, 1"),
217
218 INSTR_7XX(c0d20505_07bfc006, "stg.a.f32 g[r0.z+r1.y+255], r0.w, 7"),
219 INSTR_7XX(c0d20507_04812006, "stg.a.f32 g[c0.z+r1.w+4], r0.w, 4"),
220
221 INSTR_6XX(c0020011_04c08023, "ldg.a.f32 r4.y, g[r0.z+(r4.y)<<2], 4"), /* ldg.a.f32 r4.y, g[r0.z+(r4.y<<2)], 4 */
222 INSTR_6XX(c0060006_01c18017, "ldg.a.u32 r1.z, g[r1.z+(r2.w)<<2], 1"), /* ldg.a.u32 r1.z, g[r1.z+(r2.w<<2)], 1 */
223 INSTR_6XX(c0060006_0181800f, "ldg.u32 r1.z, g[r1.z+7], 1"),
224 INSTR_6XX(c0060006_01818001, "ldg.u32 r1.z, g[r1.z], 1"),
225 INSTR_6XX(c0060003_0180c269, "ldg.u32 r0.w, g[r0.w+308], 1"),
226 INSTR_6XX(c0040003_0180c269, "ldg.u16 hr0.w, g[r0.w+308], 1"),
227
228 /* Found in TCS/TES shaders of GTA V */
229 INSTR_6XX(c0020007_03c1420f, "ldg.a.f32 r1.w, g[r1.y+(r1.w+1)<<2], 3"), /* ldg.a.f32 r1.w, g[r1.y+((r1.w+1)<<2)], 3 */
230
231 /* Customely crafted */
232 INSTR_6XX(c0020007_03c1740f, "ldg.a.f32 r1.w, g[r1.y+r1.w<<5+2<<2], 3"),
233
234 INSTR_6XX(c0020011_04c08023, "ldg.a.f32 r4.y, g[r0.z+(r4.y)<<2], 4"), /* ldg.a.f32 r4.y, g[r0.z+(r4.y<<2)], 4 */
235 INSTR_6XX(c0060006_01c18017, "ldg.a.u32 r1.z, g[r1.z+(r2.w)<<2], 1"), /* ldg.a.u32 r1.z, g[r1.z+(r2.w<<2)], 1 */
236 INSTR_6XX(c0000006_01c18017, "ldg.a.f16 hr1.z, g[r1.z+(r2.w)<<2], 1"),
237 INSTR_6XX(c0060006_0181800f, "ldg.u32 r1.z, g[r1.z+7], 1"),
238 INSTR_6XX(c0060006_01818001, "ldg.u32 r1.z, g[r1.z], 1"),
239
240 INSTR_7XX(c0020411_04c08023, "ldg.a.f32 r4.y, g[r0.z+r4.y+2], 4"),
241 INSTR_7XX(c0004006_01c1a017, "ldg.a.f16 hr1.z, g[c1.z+r2.w+32], 1"),
242
243 /* dEQP-GLES3.functional.ubo.random.basic_arrays.0 */
244 INSTR_6XX(c7020020_01800000, "stc.f32 c[32], r0.x, 1"), /* stc c[32], r0.x, 1 */
245 /* dEQP-VK.image.image_size.cube_array.readonly_writeonly_1x1x12 */
246 INSTR_6XX(c7060020_03800000, "stc.u32 c[32], r0.x, 3"), /* stc c[32], r0.x, 3 */
247 /* A660 EQP-VK.robustness.robustness2.push.notemplate.r32i.unroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.1d.frag */
248 /* TODO: stc has a similar to stsc DST range */
249 /* INSTR_6XX(c702026e_0480025c, "stc.u32 c[366], r11.z, 4"), */ /* stc c[366], r11.z, 4 */
250
251 /* dEQP-VK.pipeline.monolithic.extended_dynamic_state.two_draws_static.stencil_state_face_both_single_gt_replace_clear_102_ref_103_depthfail */
252 INSTR_7XX(c7420000_0cc00000, "stsc.f32 c[0], 0, 12"),
253 /* dEQP-VK.pipeline.monolithic.push_constant.graphics_pipeline.overlap_4_shaders_vert_tess_frag */
254 INSTR_7XX(c7420000_08c00020, "stsc.f32 c[0], 16, 8"),
255 INSTR_7XX(c742006e_08c00220, "stsc.f32 c[366], 16, 8"),
256
257 /* custom */
258 INSTR_6XX(c7060100_03800000, "stc.u32 c[a1.x], r0.x, 3"), /* stc c[a1.x], r0.x, 3 */
259 INSTR_6XX(c7060120_03800000, "stc.u32 c[a1.x+32], r0.x, 3"), /* stc c[a1.x+32], r0.x, 3 */
260
261 /* dEQP-VK.image.image_size.cube_array.readonly_writeonly_1x1x12 */
262 INSTR_6XX(c0260200_03676100, "stib.b.untyped.1d.u32.3.imm.base0 r0.x, r0.w, 1"), /* stib.untyped.u32.1d.3.mode4.base0 r0.x, r0.w, 1 */
263
264 INSTR_6XX(c0240402_00674100, "stib.b.untyped.1d.u16.1.imm.base0 hr0.z, r0.x, 2"),
265 #if 0
266 /* TODO blob sometimes/frequently sets b0, although there does not seem
267 * to be an obvious pattern and our encoding never sets it. AFAICT it
268 * is a dontcare bit
269 */
270 /* dEQP-VK.texture.filtering.cube.formats.a8b8g8r8_srgb_nearest_mipmap_nearest.txt */
271 INSTR_6XX(c0220200_0361b801, "ldib.b.typed.1d.f32.4.imm r0.x, r0.w, 1"), /* ldib.f32.1d.4.mode0.base0 r0.x, r0.w, 1 */
272 #else
273 /* dEQP-VK.texture.filtering.cube.formats.a8b8g8r8_srgb_nearest_mipmap_nearest.txt */
274 INSTR_6XX(c0220200_0361b800, "ldib.b.typed.1d.f32.4.imm r0.x, r0.w, 1"), /* ldib.f32.1d.4.mode0.base0 r0.x, r0.w, 1 */
275 #endif
276
277 INSTR_7XX(d1260406_00e77100, "(sy)stib.b.untyped.1d.u32.4.imm.base0 r1.z, r0.x+4, 2"),
278 INSTR_7XX(c3260002_01e1b100, "ldib.b.untyped.1d.u32.4.imm.base0 r0.z, r0.y+12, 0"),
279
280 /* dEQP-GLES31.functional.tessellation.invariance.outer_edge_symmetry.isolines_equal_spacing_ccw */
281 INSTR_6XX(c2c21100_04800006, "stlw.f32 l[r2.x], r0.w, 4"),
282 INSTR_6XX(c2c20f00_01800004, "stlw.f32 l[r1.w], r0.z, 1"),
283 INSTR_6XX(c2860003_02808011, "ldlw.u32 r0.w, l[r0.z+8], 2"),
284
285 /* dEQP-VK.compute.basic.shared_var_single_group */
286 INSTR_6XX(c1060500_01800008, "stl.u32 l[r0.z], r1.x, 1"),
287 INSTR_6XX(c0460001_01804001, "ldl.u32 r0.y, l[r0.y], 1"),
288
289 INSTR_6XX(c0860018_03820001, "ldp.u32 r6.x, p[r2.x], 3"),
290 INSTR_6XX(c0420002_01808019, "ldl.f32 r0.z, l[r0.z+12], 1"),
291 INSTR_6XX(c1021710_04800000, "stl.f32 l[r2.w+16], r0.x, 4"),
292 INSTR_6XX(d7c60011_03c00000, "(sy)ldlv.u32 r4.y, l[0], 3"),
293
294 /* resinfo */
295 INSTR_6XX(c0260000_0063c200, "resinfo.b.untyped.2d.u32.1.imm r0.x, 0"), /* resinfo.u32.2d.mode0.base0 r0.x, 0 */
296 /* dEQP-GLES31.functional.image_load_store.buffer.image_size.writeonly_7.txt */
297 INSTR_6XX(c0260000_0063c000, "resinfo.b.untyped.1d.u32.1.imm r0.x, 0"), /* resinfo.u32.1d.mode0.base0 r0.x, 0 */
298 /* dEQP-VK.image.image_size.2d.readonly_12x34.txt */
299 INSTR_6XX(c0260000_0063c300, "resinfo.b.untyped.2d.u32.1.imm.base0 r0.x, 0"), /* resinfo.u32.2d.mode4.base0 r0.x, 0 */
300 /* Custom test */
301 INSTR_6XX(c0260000_0063c382, "resinfo.b.untyped.2d.u32.1.nonuniform.base1 r0.x, r0.x"), /* resinfo.u32.2d.mode6.base1 r0.x, r0.x */
302
303 /* dEQP-GLES31.functional.image_load_store.2d.image_size.readonly_writeonly_32x32.txt */
304 INSTR_5XX(c3e60000_00000200, "resinfo.u32.2d r0.x, g[0]"), /* resinfo.u32.2d r0.x, 0 */
305 #if 0
306 /* TODO our encoding differs in b11 ('typed'), which seems to be a dontcare bit */
307 /* dEQP-GLES31.functional.image_load_store.buffer.image_size.readonly_writeonly_7 */
308 INSTR_5XX(c3e60000_00000e00, "resinfo.u32.4d r0.x, g[0]"), /* resinfo.u32.1dtype r0.x, 0 */
309 /* dEQP-GLES31.functional.image_load_store.3d.image_size.readonly_writeonly_12x34x56 */
310 INSTR_5XX(c3e60000_00000c00, "resinfo.u32.3d r0.x, g[0]"), /* resinfo.u32.3d r0.x, 0 */
311 #else
312 /* dEQP-GLES31.functional.image_load_store.buffer.image_size.readonly_writeonly_7 */
313 INSTR_5XX(c3e60000_00000600, "resinfo.u32.4d r0.x, g[0]"), /* resinfo.u32.1dtype r0.x, 0 */
314 /* dEQP-GLES31.functional.image_load_store.2d.image_size.readonly_writeonly_32x32.txt */
315 INSTR_5XX(c3e60000_00000400, "resinfo.u32.3d r0.x, g[0]"), /* resinfo.u32.3d r0.x, 0 */
316 #endif
317
318 /* ldgb */
319 /* dEQP-GLES31.functional.ssbo.layout.single_basic_type.packed.mediump_vec4 */
320 INSTR_5XX(c6e20000_06003600, "ldgb.untyped.4d.f32.4 r0.x, g[0], r0.x, r1.z"), /* ldgb.a.untyped.1dtype.f32.4 r0.x, g[r0.x], r1.z, 0 */
321 /* dEQP-GLES31.functional.ssbo.layout.single_basic_type.packed.mediump_ivec4 */
322 INSTR_5XX(c6ea0000_06003600, "ldgb.untyped.4d.s32.4 r0.x, g[0], r0.x, r1.z"), /* ldgb.a.untyped.1dtype.s32.4 r0.x, g[r0.x], r1.z, 0 */
323 /* dEQP-GLES31.functional.ssbo.layout.single_basic_type.packed.mediump_float */
324 INSTR_5XX(c6e20000_02000600, "ldgb.untyped.4d.f32.1 r0.x, g[0], r0.x, r0.z"), /* ldgb.a.untyped.1dtype.f32.1 r0.x, g[r0.x], r0.z, 0 */
325 /* dEQP-GLES31.functional.ssbo.layout.random.vector_types.0 */
326 INSTR_5XX(c6ea0008_14002600, "ldgb.untyped.4d.s32.3 r2.x, g[0], r0.x, r5.x"), /* ldgb.a.untyped.1dtype.s32.3 r2.x, g[r0.x], r5.x, 0 */
327 INSTR_5XX(c6ea0204_1401a600, "ldgb.untyped.4d.s32.3 r1.x, g[1], r1.z, r5.x"), /* ldgb.a.untyped.1dtype.s32.3 r1.x, g[r1.z], r5.x, 1 */
328
329 /* stgb */
330 INSTR_5XX(c7220028_0480000d, "stgb.untyped.1d.f32.1 g[0], r1.z, 4, r10.x"), /* stgb.untyped.1d.1 g[r10.x], r1.z, 4, r0.x */
331 INSTR_5XX(c7260023_02800009, "stgb.untyped.1d.u32.1 g[0], r1.x, 2, r8.w"), /* stgb.untyped.1d.1 g[r8.w], r1.x, 2, r0.x */
332
333 /* discard stuff */
334 INSTR_6XX(42b400f8_20010004, "cmps.s.eq p0.x, r1.x, 1"),
335 INSTR_6XX(02800000_00000000, "kill p0.x"),
336
337 /* Immediates */
338 INSTR_6XX(40100007_68000008, "add.f r1.w, r2.x, (neg)(0.0)"),
339 INSTR_6XX(40100007_68010008, "add.f r1.w, r2.x, (neg)(0.5)"),
340 INSTR_6XX(40100007_68020008, "add.f r1.w, r2.x, (neg)(1.0)"),
341 INSTR_6XX(40100007_68030008, "add.f r1.w, r2.x, (neg)(2.0)"),
342 INSTR_6XX(40100007_68040008, "add.f r1.w, r2.x, (neg)(e)"),
343 INSTR_6XX(40100007_68050008, "add.f r1.w, r2.x, (neg)(pi)"),
344 INSTR_6XX(40100007_68060008, "add.f r1.w, r2.x, (neg)(1/pi)"),
345 INSTR_6XX(40100007_68070008, "add.f r1.w, r2.x, (neg)(1/log2(e))"),
346 INSTR_6XX(40100007_68080008, "add.f r1.w, r2.x, (neg)(log2(e))"),
347 INSTR_6XX(40100007_68090008, "add.f r1.w, r2.x, (neg)(1/log2(10))"),
348 INSTR_6XX(40100007_680a0008, "add.f r1.w, r2.x, (neg)(log2(10))"),
349 INSTR_6XX(40100007_680b0008, "add.f r1.w, r2.x, (neg)(4.0)"),
350
351 /* LDC. Our disasm differs greatly from qcom here, and we've got some
352 * important info they lack(?!), but same goes the other way.
353 */
354 /* dEQP-GLES31.functional.shaders.opaque_type_indexing.ubo.uniform_fragment */
355 INSTR_6XX(c0260000_00c78040, "ldc.offset0.1.uniform r0.x, 0, r0.x"), /* ldc.1.mode1.base0 r0.x, 0, r0.x */
356 INSTR_6XX(c0260201_00c78040, "ldc.offset0.1.uniform r0.y, 0, r0.y"), /* ldc.1.mode1.base0 r0.y, 0, r0.y */
357 /* dEQP-GLES31.functional.shaders.opaque_type_indexing.ubo.dynamically_uniform_fragment */
358 INSTR_6XX(c0260000_00c78080, "ldc.offset0.1.nonuniform r0.x, 0, r0.x"), /* ldc.1.mode2.base0 r0.x, 0, r0.x */
359 INSTR_6XX(c0260201_00c78080, "ldc.offset0.1.nonuniform r0.y, 0, r0.y"), /* ldc.1.mode2.base0 r0.y, 0, r0.y */
360
361 /* a4xx-a5xx has the exact same instrs in
362 * dEQP-GLES31.functional.shaders.opaque_type_indexing.ubo.(dynamically_)uniform_fragment
363 * with no change based on the mode. Note that we can't decode this yet.
364 */
365 /* INSTR_4XX(c7860000_00810001), */ /* ldc.1 r0.x, g[r1.x], 0, r0.x */
366 /* INSTR_5XX(c7860000_00800000), */ /* ldc.a.1 r0.x, g[r0.x], 0, r0.x */
367
368 /* custom */
369 INSTR_6XX(c0260201_ffc78080, "ldc.offset0.1.nonuniform r0.y, 255, r0.y"), /* ldc.1.mode2.base0 r0.y, 255, r0.y */
370
371 /* custom shaders, loading .x, .y, .z, .w from an array of vec4 in block 0 */
372 INSTR_6XX(c0260000_00478000, "ldc.offset0.1.imm r0.x, r0.x, 0"), /* ldc.1.mode0.base0 r0.x, r0.x, 0 */
373 INSTR_6XX(c0260000_00478200, "ldc.offset1.1.imm r0.x, r0.x, 0"), /* ldc.1.mode0.base0 r0.x, r0.x, 0 */
374 INSTR_6XX(c0260000_00478400, "ldc.offset2.1.imm r0.x, r0.x, 0"), /* ldc.1.mode0.base0 r0.x, r0.x, 0 */
375 INSTR_6XX(c0260000_00478600, "ldc.offset3.1.imm r0.x, r0.x, 0"), /* ldc.1.mode0.base0 r0.x, r0.x, 0 */
376
377 /* dEQP-VK.glsl.arrays.length.float_fragment */
378 INSTR_6XX(c02600c1_00c7a900, "ldc.u.offset0.3.imm.base0 r48.y, 0, 0"), /* ldc.u.3.mode4.base0 sr48.y, 0, 0 */
379
380 /* dEQP-VK.glsl.conditionals.if.if_else_vertex */
381 INSTR_6XX(c0360000_00c78100, "ldc.1.k.imm.base0 c[a1.x], 0, 0"), /* ldc.1.k.mode4.base0 c[a1.x], 0, 0 */
382 /* custom */
383 INSTR_6XX(c0360003_00c78100, "ldc.4.k.imm.base0 c[a1.x], 0, 0"), /* ldc.4.k.mode4.base0 c[a1.x], 0, 0 */
384
385 /* dEQP-VK.glsl.struct.local.nested_struct_array_dynamic_index_fragment */
386 INSTR_6XX(c1425b50_01803e02, "stp.f32 p[r11.y-176], r0.y, 1"),
387 INSTR_6XX(c1425b98_02803e14, "stp.f32 p[r11.y-104], r2.z, 2"),
388 INSTR_6XX(c1465ba0_01803e2a, "stp.u32 p[r11.y-96], r5.y, 1"),
389 INSTR_6XX(c0860008_01860001, "ldp.u32 r2.x, p[r6.x], 1"),
390 /* Custom stp based on above to catch a disasm bug. */
391 INSTR_6XX(c1465b00_0180022a, "stp.u32 p[r11.y+256], r5.y, 1"),
392
393 INSTR_6XX(c0160010_00b001a1, "ldg.k.u32 c[16], g[r48.x+208], 1"),
394 INSTR_6XX(c0160188_00b01261, "ldg.k.u32 c[a1.x+136], g[r48.x+2352], 1"),
395
396 /* Atomic: */
397 #if 0
398 /* TODO our encoding differs in b53 for these two */
399 INSTR_5XX(c4f60002_00008001, "atomic.s.inc.untyped.1d.u32.1.g r0.z, g[0], r0.z, r0.x, r0.x"),
400 INSTR_5XX(c4360205_03000001, "atomic.s.add.untyped.1d.u32.1.g r1.y, g[1], r0.x, r0.w, r0.x"),
401 #else
402 INSTR_5XX(c4f60002_00008001, "atomic.s.inc.untyped.1d.u32.1.g r0.z, g[0], r0.z, r0.x, r0.x"),
403 INSTR_5XX(c4360205_03000001, "atomic.s.add.untyped.1d.u32.1.g r1.y, g[1], r0.x, r0.w, r0.x"),
404 #endif
405 INSTR_6XX(d5c60003_03008001, "(sy)atomic.max.untyped.1d.u32.1.l r0.w, l[r0.z], r0.w"),
406
407 /* dEQP-VK.glsl.atomic_operations.add_unsigned_compute_reference */
408 INSTR_6XX(c4160002_02000001, "atomic.g.add.untyped.1d.u32.1.g r0.z, r0.x, r0.z"),
409
410 /* Bindless atomic: */
411 INSTR_6XX(c03a0003_01640000, "atomic.b.add.untyped.1d.s32.1.imm r0.w, r0.y, 0"), /* atomic.b.add.g.s32.1d.mode0.base0 r0.w,r0.y,0 */
412 INSTR_6XX(c03a0003_01660000, "atomic.b.and.untyped.1d.s32.1.imm r0.w, r0.y, 0"), /* atomic.b.and.g.s32.1d.mode0.base0 r0.w,r0.y,0 */
413 INSTR_6XX(c0360000_0365c800, "atomic.b.max.typed.1d.u32.1.imm r0.x, r0.w, 0"), /* atomic.b.max.g.u32.1d.mode0.base0 r0.x,r0.w,0 */
414
415 /* dEQP-GLES31.functional.shaders.opaque_type_indexing.sampler.const_literal.fragment.sampler2d */
416 INSTR_6XX(a0c01f04_0cc00005, "sam (f32)(xyzw)r1.x, r0.z, s#6, t#6"),
417
418 /* dEQP-GLES31.functional.shaders.opaque_type_indexing.sampler.uniform.fragment.sampler2d */
419 INSTR_4XX(a0c81f02_00800001, "sam.s2en.uniform (f32)(xyzw)r0.z, r0.x, hr1.x"), /* sam.s2en.mode0 (f32)(xyzw)r0.z, r0.x, hr1.x */ /* same for 5xx */
420 INSTR_6XX(a0c81f07_0100000b, "sam.s2en.uniform (f32)(xyzw)r1.w, r1.y, hr2.x"), /* sam.s2en.mode0 (f32)(xyzw)r1.w, r1.y, hr2.x */
421
422 /* dEQP-GLES31.functional.shaders.opaque_type_indexing.sampler.dynamically_uniform.fragment.sampler2d */
423 INSTR_4XX(a0c81f02_80800001, "sam.s2en.nonuniform (f32)(xyzw)r0.z, r0.x, hr1.x"), /* sam.s2en.uniform (f32)(xyzw)r0.z, r0.x, hr1.x */ /* same for 5xx */
424 INSTR_6XX(a0c81f07_8100000b, "sam.s2en.nonuniform (f32)(xyzw)r1.w, r1.y, hr2.x"), /* sam.s2en.mode4 (f32)(xyzw)r1.w, r1.y, hr2.x */
425
426 /* NonUniform: */
427 /* dEQP-VK.descriptor_indexing.storage_buffer */
428 INSTR_6XX(c0260c0a_0a61b180, "ldib.b.untyped.1d.u32.4.nonuniform.base0 r2.z, r2.z, r1.z"),
429 INSTR_6XX(d0260e0a_09677180, "(sy)stib.b.untyped.1d.u32.4.nonuniform.base0 r2.z, r2.y, r1.w"),
430 /* dEQP-VK.descriptor_indexing.uniform_texel_buffer */
431 INSTR_6XX(a0481f00_40000405, "isaml.s2en.nonuniform.base0 (f32)(xyzw)r0.x, r0.z, r0.z, r0.x"),
432 /* dEQP-VK.descriptor_indexing.storage_image */
433 INSTR_6XX(d0360c04_02640b80, "(sy)atomic.b.add.typed.2d.u32.1.nonuniform.base0 r1.x, r0.z, r1.z"),
434 /* dEQP-VK.descriptor_indexing.sampler */
435 INSTR_6XX(a0c81f00_40000005, "sam.s2en.nonuniform.base0 (f32)(xyzw)r0.x, r0.z, r0.x"),
436
437 /* dEQP-VK.subgroups.quad.graphics.subgroupquadbroadcast_int */
438 INSTR_6XX(c0260001_00c98000, "getfiberid.u32 r0.y"),
439
440 /* Custom test since we've never seen the blob emit these. */
441 INSTR_6XX(c0260004_00490000, "getspid.u32 r1.x"),
442 INSTR_6XX(c0260005_00494000, "getwid.u32 r1.y"),
443
444 /* cat7 */
445
446 /* dEQP-VK.compute.basic.ssbo_local_barrier_single_invocation */
447 INSTR_6XX(e0fa0000_00000000, "fence.g.l.r.w"),
448 INSTR_6XX(e09a0000_00000000, "fence.r.w"),
449 INSTR_6XX(f0420000_00000000, "(sy)bar.g"),
450 INSTR_6XX(e1080000_00000000, "sleep.l"),
451 INSTR_6XX(e2080000_00000000, "dccln.all"),
452 /* dEQP-VK.memory_model.message_passing.core11.u32.coherent.fence_fence.atomicwrite.device.payload_local.buffer.guard_local.buffer.comp */
453 INSTR_7XX(e2d20000_00000000, "ccinv"),
454
455 INSTR_7XX(e3c20000_00000000, "lock"),
456 INSTR_7XX(fbc21000_00000000, "(sy)(ss)(jp)lock"),
457
458 /* dEQP-VK.pipeline.monolithic.sampler.border_swizzle.r4g4b4a4_unorm_pack16.rg1a.opaque_white.gather_1.no_swizzle_hint */
459 INSTR_7XX(e45401a0_bfba7736, "alias.tex.b32.1 r40.x, (-1.456763)"),
460 /* dEQP-VK.synchronization.op.single_queue.event.write_draw_indexed_read_image_geometry.image_128x128_r32g32b32a32_sfloat */
461 INSTR_7XX(e44c0009_00000007, "alias.tex.b32.0 r2.y, c1.w"),
462
463 INSTR_6XX(ffffffff_ffffffff, "raw 0xFFFFFFFFFFFFFFFF"),
464 /* clang-format on */
465 };
466
467 static void
add_generated_tests(struct u_vector * all_tests,void * ctx)468 add_generated_tests(struct u_vector *all_tests, void *ctx) {
469 /* stib.b/ldib.b OFFSET_LO aliases what other instructions use for opcode */
470 for (int offset = 1; offset < 0x1f; offset++) {
471 char *stib = ralloc_asprintf(
472 ctx, "stib.b.untyped.1d.u32.4.imm.base0 r2.y, r5.z+%u, 4", offset);
473 *(struct test *)u_vector_add(all_tests) = (struct test)INSTR_6XX_RAW(
474 0xc026080916e77100ull + ((uint64_t)offset << 54), stib);
475
476 char *ldib = ralloc_asprintf(
477 ctx, "ldib.b.untyped.1d.u32.4.imm.base0 r0.z, r0.y+%u, 0", offset);
478 *(struct test *)u_vector_add(all_tests) = (struct test)INSTR_6XX_RAW(
479 0xc026000201e1b100ull + ((uint64_t)offset << 54), ldib);
480 }
481 }
482
483 static void
trim(char * string)484 trim(char *string)
485 {
486 for (int len = strlen(string); len > 0 && string[len - 1] == '\n'; len--)
487 string[len - 1] = 0;
488 }
489
490 int
main(int argc,char ** argv)491 main(int argc, char **argv)
492 {
493 int retval = 0;
494 int decode_fails = 0, asm_fails = 0, encode_fails = 0;
495 const int output_size = 4096;
496 char *disasm_output = malloc(output_size);
497 FILE *fdisasm = fmemopen(disasm_output, output_size, "w+");
498 if (!fdisasm) {
499 fprintf(stderr, "failed to fmemopen\n");
500 return 1;
501 }
502
503 void *ctx = ralloc_context(NULL);
504
505 struct u_vector all_tests = { 0 };
506 u_vector_init(&all_tests, ARRAY_SIZE(tests), sizeof(struct test));
507 for (uint32_t i = 0; i < ARRAY_SIZE(tests); i++) {
508 *(struct test *) u_vector_add(&all_tests) = tests[i];
509 }
510
511 add_generated_tests(&all_tests, ctx);
512
513 struct ir3_compiler *compilers[10] = {};
514 struct fd_dev_id dev_ids[ARRAY_SIZE(compilers)];
515
516 struct test *test;
517 u_vector_foreach (test, &all_tests) {
518 uint32_t code[2];
519 if (test->instr) {
520 code[0] = strtoll(&test->instr[9], NULL, 16);
521 code[1] = strtoll(&test->instr[0], NULL, 16);
522 } else {
523 code[0] = test->instr_raw;
524 code[1] = test->instr_raw >> 32;
525 }
526
527 printf("Testing a%d %08x_%08x: \"%s\"...\n", test->gpu_id, code[1], code[0],
528 test->expected);
529
530 struct fd_dev_id dev_id = {
531 .gpu_id = test->gpu_id,
532 .chip_id = test->chip_id,
533 };
534
535 const struct fd_dev_info *dev_info = fd_dev_info_raw(&dev_id);
536
537 rewind(fdisasm);
538 memset(disasm_output, 0, output_size);
539
540 /*
541 * Test disassembly:
542 */
543
544 ir3_isa_disasm(code, 8, fdisasm,
545 &(struct isa_decode_options){
546 .gpu_id = dev_info->chip * 100,
547 .show_errors = true,
548 .no_match_cb = print_raw,
549 });
550 fflush(fdisasm);
551
552 trim(disasm_output);
553
554 if (strcmp(disasm_output, test->expected) != 0) {
555 printf("FAIL: disasm\n");
556 printf(" Expected: \"%s\"\n", test->expected);
557 printf(" Got: \"%s\"\n", disasm_output);
558 retval = 1;
559 decode_fails++;
560 }
561
562 /*
563 * Test assembly, which should result in the identical binary:
564 */
565
566 if (!compilers[dev_info->chip]) {
567 dev_ids[dev_info->chip].gpu_id = test->gpu_id;
568 dev_ids[dev_info->chip].chip_id = test->chip_id;
569 compilers[dev_info->chip] =
570 ir3_compiler_create(NULL, &dev_ids[dev_info->chip],
571 fd_dev_info_raw(&dev_ids[dev_info->chip]),
572 &(struct ir3_compiler_options){});
573 }
574
575 FILE *fasm =
576 fmemopen((void *)test->expected, strlen(test->expected), "r");
577
578 struct ir3_kernel_info info = {};
579 struct ir3_shader *shader = ir3_parse_asm(compilers[dev_info->chip], &info, fasm);
580 fclose(fasm);
581 if (!shader) {
582 printf("FAIL: %sexpected assembler fail\n",
583 test->parse_fail ? "" : "un");
584 asm_fails++;
585 /* If this is an instruction that the asm parser is not expected
586 * to handle, don't count it as a fail.
587 */
588 if (!test->parse_fail)
589 retval = 1;
590 continue;
591 } else if (test->parse_fail) {
592 /* If asm parse starts passing, and we don't expect that, flag
593 * it as a fail so we don't forget to update the test vector:
594 */
595 printf(
596 "FAIL: unexpected parse success, please remove '.parse_fail=true'\n");
597 retval = 1;
598 }
599
600 struct ir3_shader_variant *v = shader->variants;
601 if (memcmp(v->bin, code, sizeof(code))) {
602 printf("FAIL: assembler\n");
603 printf(" Expected: %08x_%08x\n", code[1], code[0]);
604 printf(" Got: %08x_%08x\n", v->bin[1], v->bin[0]);
605 retval = 1;
606 encode_fails++;
607 }
608
609 ir3_shader_destroy(shader);
610 }
611
612 if (decode_fails)
613 printf("%d/%d decode fails\n", decode_fails, (int)ARRAY_SIZE(tests));
614 if (asm_fails)
615 printf("%d/%d assembler fails\n", asm_fails, (int)ARRAY_SIZE(tests));
616 if (encode_fails)
617 printf("%d/%d encode fails\n", encode_fails, (int)ARRAY_SIZE(tests));
618
619 if (retval) {
620 printf("FAILED!\n");
621 } else {
622 printf("PASSED!\n");
623 }
624
625 for (unsigned i = 0; i < ARRAY_SIZE(compilers); i++) {
626 if (!compilers[i])
627 continue;
628 ir3_compiler_destroy(compilers[i]);
629 }
630
631 u_vector_finish(&all_tests);
632 ralloc_free(ctx);
633 fclose(fdisasm);
634 free(disasm_output);
635
636 return retval;
637 }
638