1 /* 2 * Copyright © 2023 Igalia S.L. 3 * SPDX-License-Identifier: MIT 4 */ 5 6 #ifndef __FREEDRENO_STOMPABLE_REGS_H__ 7 #define __FREEDRENO_STOMPABLE_REGS_H__ 8 9 #include <stdint.h> 10 11 #include "a6xx.xml.h" 12 13 /* In order to debug issues with usage of stale reg data we need to have 14 * a list of regs which we allowed to stomp. 15 * The regs we are NOT allowed to stomp are: 16 * - Write protected; 17 * - Written by kernel but are not write protected; 18 * - Some regs that are not written by anyone but do affect the result. 19 * 20 * In addition, some regs are only emmitted during cmdbuf setup 21 * so we have to have additional filter to get a reduced list of regs 22 * stompable before each renderpass/blit. 23 */ 24 25 /* Stomping some regs is known to cause issues */ 26 static inline bool fd_reg_stomp_allowed(chip CHIP,uint16_t reg)27fd_reg_stomp_allowed(chip CHIP, uint16_t reg) 28 { 29 switch (CHIP) { 30 case A6XX: { 31 switch (reg) { 32 /* Faults in 33 * dEQP-VK.renderpass.suballocation.formats.r5g6b5_unorm_pack16.clear.clear 34 * It seems that PC_CCU_FLUSH_COLOR_TS reads REG_A6XX_RB_DEPTH_PLANE_CNTL. 35 */ 36 case REG_A6XX_RB_DEPTH_PLANE_CNTL: 37 /* Faults in 38 * dEQP-VK.conditional_rendering.draw.condition_host_memory_expect_noop.draw 39 */ 40 case REG_A6XX_HLSQ_VS_CNTL ... REG_A6XX_HLSQ_GS_CNTL: 41 case REG_A6XX_HLSQ_FS_CNTL: 42 /* Faults in 43 * dEQP-VK.memory_model.message_passing.ext.u32.coherent.atomic_atomic.atomicrmw.device.payload_local.image.guard_local.image.comp 44 * while there is even no fragment shaders. 45 */ 46 case REG_A6XX_SP_FS_OBJ_START ... REG_A6XX_SP_FS_OBJ_START + 1: 47 return false; 48 /* Not used on A6XX but causes failures when set */ 49 case REG_A6XX_TPL1_DBG_ECO_CNTL1: 50 return false; 51 } 52 break; 53 } 54 case A7XX: { 55 switch (reg) { 56 case REG_A6XX_RB_DEPTH_PLANE_CNTL: 57 case REG_A7XX_HLSQ_VS_CNTL: 58 case REG_A7XX_HLSQ_HS_CNTL: 59 case REG_A7XX_HLSQ_DS_CNTL: 60 case REG_A7XX_HLSQ_GS_CNTL: 61 case REG_A7XX_HLSQ_FS_CNTL: 62 case REG_A6XX_SP_VS_OBJ_START ... REG_A6XX_SP_VS_OBJ_START + 1: 63 case REG_A6XX_SP_FS_OBJ_START ... REG_A6XX_SP_FS_OBJ_START + 1: 64 /* There is a guess that GPU may not be able to handle different values of 65 * certain debug register between BR/BV. This one causes GPU to hang. 66 */ 67 case REG_A7XX_SP_UNKNOWN_AE73: 68 case REG_A7XX_RB_UNKNOWN_8E79: 69 case REG_A7XX_SP_UNKNOWN_AE09: 70 case REG_A6XX_TPL1_DBG_ECO_CNTL: 71 return false; 72 case REG_A7XX_SP_GS_VGPR_CONFIG: 73 case REG_A7XX_SP_FS_VGPR_CONFIG: 74 case REG_A7XX_SP_CS_VGPR_CONFIG: 75 return false; 76 } 77 break; 78 } 79 default: { 80 unreachable("Unknown GPU"); 81 } 82 } 83 84 return true; 85 } 86 87 #endif /* __FREEDRENO_STOMPABLE_REGS_H__ */ 88