1 /*
2 * Copyright (C) 2014-2015 Etnaviv Project
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Christian Gmeiner <[email protected]>
25 */
26
27 #ifndef ETNAVIV_DRMIF_H_
28 #define ETNAVIV_DRMIF_H_
29
30 #include <xf86drm.h>
31 #include <stdbool.h>
32 #include <stdint.h>
33
34 struct etna_bo;
35 struct etna_pipe;
36 struct etna_gpu;
37 struct etna_device;
38 struct etna_cmd_stream;
39 struct etna_perfmon;
40 struct etna_perfmon_domain;
41 struct etna_perfmon_signal;
42 struct etna_core_info;
43
44 enum etna_pipe_id {
45 ETNA_PIPE_3D = 0,
46 ETNA_PIPE_2D = 1,
47 ETNA_PIPE_VG = 2,
48 ETNA_PIPE_MAX
49 };
50
51 enum etna_param_id {
52 ETNA_GPU_MODEL = 0x1,
53 ETNA_GPU_REVISION = 0x2,
54 ETNA_GPU_FEATURES_0 = 0x3,
55 ETNA_GPU_FEATURES_1 = 0x4,
56 ETNA_GPU_FEATURES_2 = 0x5,
57 ETNA_GPU_FEATURES_3 = 0x6,
58 ETNA_GPU_FEATURES_4 = 0x7,
59 ETNA_GPU_FEATURES_5 = 0x8,
60 ETNA_GPU_FEATURES_6 = 0x9,
61 ETNA_GPU_FEATURES_7 = 0xa,
62 ETNA_GPU_FEATURES_8 = 0xb,
63 ETNA_GPU_FEATURES_9 = 0xc,
64 ETNA_GPU_FEATURES_10 = 0xd,
65 ETNA_GPU_FEATURES_11 = 0xe,
66 ETNA_GPU_FEATURES_12 = 0xf,
67
68 ETNA_GPU_STREAM_COUNT = 0x10,
69 ETNA_GPU_REGISTER_MAX = 0x11,
70 ETNA_GPU_THREAD_COUNT = 0x12,
71 ETNA_GPU_VERTEX_CACHE_SIZE = 0x13,
72 ETNA_GPU_SHADER_CORE_COUNT = 0x14,
73 ETNA_GPU_PIXEL_PIPES = 0x15,
74 ETNA_GPU_VERTEX_OUTPUT_BUFFER_SIZE = 0x16,
75 ETNA_GPU_BUFFER_SIZE = 0x17,
76 ETNA_GPU_INSTRUCTION_COUNT = 0x18,
77 ETNA_GPU_NUM_CONSTANTS = 0x19,
78 ETNA_GPU_NUM_VARYINGS = 0x1a,
79 ETNA_SOFTPIN_START_ADDR = 0x1b,
80 ETNA_GPU_PRODUCT_ID = 0x1c,
81 ETNA_GPU_CUSTOMER_ID = 0x1d,
82 ETNA_GPU_ECO_ID = 0x1e,
83 };
84
85 /* bo flags: */
86 #define DRM_ETNA_GEM_CACHE_CACHED 0x00010000
87 #define DRM_ETNA_GEM_CACHE_WC 0x00020000
88 #define DRM_ETNA_GEM_CACHE_UNCACHED 0x00040000
89 #define DRM_ETNA_GEM_CACHE_MASK 0x000f0000
90 /* map flags */
91 #define DRM_ETNA_GEM_FORCE_MMU 0x00100000
92
93 /* bo access flags: (keep aligned to ETNA_PREP_x) */
94 #define DRM_ETNA_PREP_READ 0x01
95 #define DRM_ETNA_PREP_WRITE 0x02
96 #define DRM_ETNA_PREP_NOSYNC 0x04
97
98 /* device functions:
99 */
100
101 #define ETNA_DRM_VERSION(major, minor) ((major) << 16 | (minor))
102
103 struct etna_device *etna_device_new(int fd);
104 struct etna_device *etna_device_new_dup(int fd);
105 struct etna_device *etna_device_ref(struct etna_device *dev);
106 void etna_device_del(struct etna_device *dev);
107 int etna_device_fd(struct etna_device *dev);
108 bool etnaviv_device_softpin_capable(struct etna_device *dev);
109 uint32_t etnaviv_device_version(struct etna_device *dev);
110
111 /* gpu functions:
112 */
113
114 struct etna_gpu *etna_gpu_new(struct etna_device *dev, unsigned int core);
115 void etna_gpu_del(struct etna_gpu *gpu);
116 int etna_gpu_get_param(struct etna_gpu *gpu, enum etna_param_id param,
117 uint64_t *value);
118 struct etna_core_info *etna_gpu_get_core_info(struct etna_gpu *gpu);
119
120
121 /* pipe functions:
122 */
123
124 struct etna_pipe *etna_pipe_new(struct etna_gpu *gpu, enum etna_pipe_id id);
125 void etna_pipe_del(struct etna_pipe *pipe);
126 int etna_pipe_wait_ns(struct etna_pipe *pipe, uint32_t timestamp, uint64_t ns);
127
128
129 /* buffer-object functions:
130 */
131
132 struct etna_bo *etna_bo_new(struct etna_device *dev,
133 uint32_t size, uint32_t flags);
134 struct etna_bo *etna_bo_from_name(struct etna_device *dev, uint32_t name);
135 struct etna_bo *etna_bo_from_dmabuf(struct etna_device *dev, int fd);
136 struct etna_bo *etna_bo_ref(struct etna_bo *bo);
137 void etna_bo_del(struct etna_bo *bo);
138 int etna_bo_get_name(struct etna_bo *bo, uint32_t *name);
139 uint32_t etna_bo_handle(struct etna_bo *bo);
140 int etna_bo_dmabuf(struct etna_bo *bo);
141 uint32_t etna_bo_size(struct etna_bo *bo);
142 uint32_t etna_bo_gpu_va(struct etna_bo *bo);
143 void * etna_bo_map(struct etna_bo *bo);
144 int etna_bo_cpu_prep(struct etna_bo *bo, uint32_t op);
145 void etna_bo_cpu_fini(struct etna_bo *bo);
146 int etna_bo_is_idle(struct etna_bo *bo);
147
148
149 /* cmd stream functions:
150 */
151
152 struct etna_cmd_stream {
153 uint32_t *buffer;
154 uint32_t offset; /* in 32-bit words */
155 uint32_t size; /* in 32-bit words */
156 };
157
158 struct etna_cmd_stream *etna_cmd_stream_new(struct etna_pipe *pipe, uint32_t size,
159 void (*reset_notify)(struct etna_cmd_stream *stream, void *priv),
160 void *priv);
161 void etna_cmd_stream_del(struct etna_cmd_stream *stream);
162 uint32_t etna_cmd_stream_timestamp(struct etna_cmd_stream *stream);
163 void etna_cmd_stream_flush(struct etna_cmd_stream *stream, int in_fence_fd,
164 int *out_fence_fd, bool is_noop);
165 void etna_cmd_stream_force_flush(struct etna_cmd_stream *stream);
166
etna_cmd_stream_avail(struct etna_cmd_stream * stream)167 static inline uint32_t etna_cmd_stream_avail(struct etna_cmd_stream *stream)
168 {
169 static const uint32_t END_CLEARANCE = 2; /* LINK op code */
170
171 return stream->size - stream->offset - END_CLEARANCE;
172 }
173
174 void etna_cmd_stream_realloc(struct etna_cmd_stream *stream, size_t n);
175
etna_cmd_stream_reserve(struct etna_cmd_stream * stream,size_t n)176 static inline void etna_cmd_stream_reserve(struct etna_cmd_stream *stream, size_t n)
177 {
178 if (etna_cmd_stream_avail(stream) < n)
179 etna_cmd_stream_realloc(stream, n);
180 }
181
etna_cmd_stream_emit(struct etna_cmd_stream * stream,uint32_t data)182 static inline void etna_cmd_stream_emit(struct etna_cmd_stream *stream, uint32_t data)
183 {
184 stream->buffer[stream->offset++] = data;
185 }
186
etna_cmd_stream_get(struct etna_cmd_stream * stream,uint32_t offset)187 static inline uint32_t etna_cmd_stream_get(struct etna_cmd_stream *stream, uint32_t offset)
188 {
189 return stream->buffer[offset];
190 }
191
etna_cmd_stream_set(struct etna_cmd_stream * stream,uint32_t offset,uint32_t data)192 static inline void etna_cmd_stream_set(struct etna_cmd_stream *stream, uint32_t offset,
193 uint32_t data)
194 {
195 stream->buffer[offset] = data;
196 }
197
etna_cmd_stream_offset(struct etna_cmd_stream * stream)198 static inline uint32_t etna_cmd_stream_offset(struct etna_cmd_stream *stream)
199 {
200 return stream->offset;
201 }
202
203 struct etna_reloc {
204 struct etna_bo *bo;
205 #define ETNA_RELOC_READ 0x0001
206 #define ETNA_RELOC_WRITE 0x0002
207 uint32_t flags;
208 uint32_t offset;
209 };
210
211 void etna_cmd_stream_reloc(struct etna_cmd_stream *stream, const struct etna_reloc *r);
212 void etna_cmd_stream_ref_bo(struct etna_cmd_stream *stream,
213 struct etna_bo *bo, uint32_t flags);
214
215 void etna_cmd_stream_mark_end_of_context_init(struct etna_cmd_stream *stream);
216
217 /* performance monitoring functions:
218 */
219
220 struct etna_perfmon *etna_perfmon_create(struct etna_pipe *pipe);
221 void etna_perfmon_del(struct etna_perfmon *perfmon);
222 struct etna_perfmon_domain *etna_perfmon_get_dom_by_name(struct etna_perfmon *pm, const char *name);
223 struct etna_perfmon_signal *etna_perfmon_get_sig_by_name(struct etna_perfmon_domain *dom, const char *name);
224
225 struct etna_perf {
226 #define ETNA_PM_PROCESS_PRE 0x0001
227 #define ETNA_PM_PROCESS_POST 0x0002
228 uint32_t flags;
229 uint32_t sequence;
230 struct etna_perfmon_signal *signal;
231 struct etna_bo *bo;
232 uint32_t offset;
233 };
234
235 void etna_cmd_stream_perf(struct etna_cmd_stream *stream, const struct etna_perf *p);
236
237 #endif /* ETNAVIV_DRMIF_H_ */
238