1 /**************************************************************************
2 *
3 * Copyright 2017 Advanced Micro Devices, Inc.
4 * Copyright 2023 Red Hat Inc.
5 * All Rights Reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
27 **************************************************************************/
28 #include "radv_buffer.h"
29 #include "radv_cs.h"
30 #include "radv_debug.h"
31 #include "radv_device_memory.h"
32 #include "radv_entrypoints.h"
33 #include "radv_image_view.h"
34 #include "radv_physical_device.h"
35 #include "radv_query.h"
36 #include "radv_video.h"
37
38 #include "ac_vcn_enc.h"
39
40 #define RENCODE_V4_FW_INTERFACE_MAJOR_VERSION 1
41 #define RENCODE_V4_FW_INTERFACE_MINOR_VERSION 7
42
43 #define RENCODE_V4_IB_PARAM_ENCODE_STATISTICS 0x0000001a
44
45 #define RENCODE_V3_FW_INTERFACE_MAJOR_VERSION 1
46 #define RENCODE_V3_FW_INTERFACE_MINOR_VERSION 27
47
48 #define RENCODE_V2_IB_PARAM_SESSION_INFO 0x00000001
49 #define RENCODE_V2_IB_PARAM_TASK_INFO 0x00000002
50 #define RENCODE_V2_IB_PARAM_SESSION_INIT 0x00000003
51 #define RENCODE_V2_IB_PARAM_LAYER_CONTROL 0x00000004
52 #define RENCODE_V2_IB_PARAM_LAYER_SELECT 0x00000005
53 #define RENCODE_V2_IB_PARAM_RATE_CONTROL_SESSION_INIT 0x00000006
54 #define RENCODE_V2_IB_PARAM_RATE_CONTROL_LAYER_INIT 0x00000007
55 #define RENCODE_V2_IB_PARAM_RATE_CONTROL_PER_PICTURE 0x00000008
56 #define RENCODE_V2_IB_PARAM_QUALITY_PARAMS 0x00000009
57 #define RENCODE_V2_IB_PARAM_DIRECT_OUTPUT_NALU 0x0000000a
58 #define RENCODE_V2_IB_PARAM_SLICE_HEADER 0x0000000b
59 #define RENCODE_V2_IB_PARAM_INPUT_FORMAT 0x0000000c
60 #define RENCODE_V2_IB_PARAM_OUTPUT_FORMAT 0x0000000d
61 #define RENCODE_V2_IB_PARAM_ENCODE_PARAMS 0x0000000f
62 #define RENCODE_V2_IB_PARAM_INTRA_REFRESH 0x00000010
63 #define RENCODE_V2_IB_PARAM_ENCODE_CONTEXT_BUFFER 0x00000011
64 #define RENCODE_V2_IB_PARAM_VIDEO_BITSTREAM_BUFFER 0x00000012
65 #define RENCODE_V2_IB_PARAM_FEEDBACK_BUFFER 0x00000015
66 #define RENCODE_V2_IB_PARAM_ENCODE_STATISTICS 0x00000019
67 #define RENCODE_V2_IB_PARAM_RATE_CONTROL_PER_PIC_EX 0x0000001d
68
69 #define RENCODE_V2_HEVC_IB_PARAM_SLICE_CONTROL 0x00100001
70 #define RENCODE_V2_HEVC_IB_PARAM_SPEC_MISC 0x00100002
71 #define RENCODE_V2_HEVC_IB_PARAM_LOOP_FILTER 0x00100003
72
73 #define RENCODE_V2_H264_IB_PARAM_SLICE_CONTROL 0x00200001
74 #define RENCODE_V2_H264_IB_PARAM_SPEC_MISC 0x00200002
75 #define RENCODE_V2_H264_IB_PARAM_ENCODE_PARAMS 0x00200003
76 #define RENCODE_V2_H264_IB_PARAM_DEBLOCKING_FILTER 0x00200004
77
78 #define RENCODE_V2_FW_INTERFACE_MAJOR_VERSION 1
79 #define RENCODE_V2_FW_INTERFACE_MINOR_VERSION 18
80
81 #define RENCODE_IB_PARAM_SESSION_INFO 0x00000001
82 #define RENCODE_IB_PARAM_TASK_INFO 0x00000002
83 #define RENCODE_IB_PARAM_SESSION_INIT 0x00000003
84 #define RENCODE_IB_PARAM_LAYER_CONTROL 0x00000004
85 #define RENCODE_IB_PARAM_LAYER_SELECT 0x00000005
86 #define RENCODE_IB_PARAM_RATE_CONTROL_SESSION_INIT 0x00000006
87 #define RENCODE_IB_PARAM_RATE_CONTROL_LAYER_INIT 0x00000007
88 #define RENCODE_IB_PARAM_RATE_CONTROL_PER_PICTURE 0x00000008
89 #define RENCODE_IB_PARAM_QUALITY_PARAMS 0x00000009
90 #define RENCODE_IB_PARAM_SLICE_HEADER 0x0000000a
91 #define RENCODE_IB_PARAM_ENCODE_PARAMS 0x0000000b
92 #define RENCODE_IB_PARAM_INTRA_REFRESH 0x0000000c
93 #define RENCODE_IB_PARAM_ENCODE_CONTEXT_BUFFER 0x0000000d
94 #define RENCODE_IB_PARAM_VIDEO_BITSTREAM_BUFFER 0x0000000e
95 #define RENCODE_IB_PARAM_FEEDBACK_BUFFER 0x00000010
96 #define RENCODE_IB_PARAM_RATE_CONTROL_PER_PIC_EX 0x0000001d
97 #define RENCODE_IB_PARAM_DIRECT_OUTPUT_NALU 0x00000020
98 #define RENCODE_IB_PARAM_ENCODE_STATISTICS 0x00000024
99
100 #define RENCODE_HEVC_IB_PARAM_SLICE_CONTROL 0x00100001
101 #define RENCODE_HEVC_IB_PARAM_SPEC_MISC 0x00100002
102 #define RENCODE_HEVC_IB_PARAM_DEBLOCKING_FILTER 0x00100003
103
104 #define RENCODE_H264_IB_PARAM_SLICE_CONTROL 0x00200001
105 #define RENCODE_H264_IB_PARAM_SPEC_MISC 0x00200002
106 #define RENCODE_H264_IB_PARAM_ENCODE_PARAMS 0x00200003
107 #define RENCODE_H264_IB_PARAM_DEBLOCKING_FILTER 0x00200004
108
109 #define RENCODE_FW_INTERFACE_MAJOR_VERSION 1
110 #define RENCODE_FW_INTERFACE_MINOR_VERSION 15
111
112 void
radv_probe_video_encode(struct radv_physical_device * pdev)113 radv_probe_video_encode(struct radv_physical_device *pdev)
114 {
115 pdev->video_encode_enabled = false;
116 if (pdev->info.vcn_ip_version >= VCN_4_0_0) {
117 if (pdev->info.vcn_enc_major_version != RENCODE_V4_FW_INTERFACE_MAJOR_VERSION)
118 return;
119 if (pdev->info.vcn_enc_minor_version < RENCODE_V4_FW_INTERFACE_MINOR_VERSION)
120 return;
121
122 /* VCN 4 FW 1.22 has all the necessary pieces to pass CTS */
123 if (pdev->info.vcn_enc_minor_version >= 22) {
124 pdev->video_encode_enabled = true;
125 return;
126 }
127 } else if (pdev->info.vcn_ip_version >= VCN_3_0_0) {
128 if (pdev->info.vcn_enc_major_version != RENCODE_V3_FW_INTERFACE_MAJOR_VERSION)
129 return;
130 if (pdev->info.vcn_enc_minor_version < RENCODE_V3_FW_INTERFACE_MINOR_VERSION)
131 return;
132 } else if (pdev->info.vcn_ip_version >= VCN_2_0_0) {
133 if (pdev->info.vcn_enc_major_version != RENCODE_V2_FW_INTERFACE_MAJOR_VERSION)
134 return;
135 if (pdev->info.vcn_enc_minor_version < RENCODE_V2_FW_INTERFACE_MINOR_VERSION)
136 return;
137 } else {
138 if (pdev->info.vcn_enc_major_version != RENCODE_FW_INTERFACE_MAJOR_VERSION)
139 return;
140 if (pdev->info.vcn_enc_minor_version < RENCODE_FW_INTERFACE_MINOR_VERSION)
141 return;
142 }
143
144 struct radv_instance *instance = radv_physical_device_instance(pdev);
145 pdev->video_encode_enabled = !!(instance->perftest_flags & RADV_PERFTEST_VIDEO_ENCODE);
146 }
147
148 void
radv_init_physical_device_encoder(struct radv_physical_device * pdev)149 radv_init_physical_device_encoder(struct radv_physical_device *pdev)
150 {
151 if (pdev->info.vcn_ip_version >= VCN_4_0_0) {
152 pdev->enc_hw_ver = RADV_VIDEO_ENC_HW_4;
153 pdev->encoder_interface_version = ((RENCODE_V4_FW_INTERFACE_MAJOR_VERSION << RENCODE_IF_MAJOR_VERSION_SHIFT) |
154 (RENCODE_V4_FW_INTERFACE_MINOR_VERSION << RENCODE_IF_MINOR_VERSION_SHIFT));
155 } else if (pdev->info.vcn_ip_version >= VCN_3_0_0) {
156 pdev->enc_hw_ver = RADV_VIDEO_ENC_HW_3;
157 pdev->encoder_interface_version = ((RENCODE_V3_FW_INTERFACE_MAJOR_VERSION << RENCODE_IF_MAJOR_VERSION_SHIFT) |
158 (RENCODE_V3_FW_INTERFACE_MINOR_VERSION << RENCODE_IF_MINOR_VERSION_SHIFT));
159 } else if (pdev->info.vcn_ip_version >= VCN_2_0_0) {
160 pdev->enc_hw_ver = RADV_VIDEO_ENC_HW_2;
161 pdev->encoder_interface_version = ((RENCODE_V2_FW_INTERFACE_MAJOR_VERSION << RENCODE_IF_MAJOR_VERSION_SHIFT) |
162 (RENCODE_V2_FW_INTERFACE_MINOR_VERSION << RENCODE_IF_MINOR_VERSION_SHIFT));
163 } else {
164 pdev->enc_hw_ver = RADV_VIDEO_ENC_HW_1_2;
165 pdev->encoder_interface_version = ((RENCODE_FW_INTERFACE_MAJOR_VERSION << RENCODE_IF_MAJOR_VERSION_SHIFT) |
166 (RENCODE_FW_INTERFACE_MINOR_VERSION << RENCODE_IF_MINOR_VERSION_SHIFT));
167 }
168
169 if (pdev->info.vcn_ip_version >= VCN_2_0_0) {
170 pdev->vcn_enc_cmds.session_info = RENCODE_V2_IB_PARAM_SESSION_INFO;
171 pdev->vcn_enc_cmds.task_info = RENCODE_V2_IB_PARAM_TASK_INFO;
172 pdev->vcn_enc_cmds.session_init = RENCODE_V2_IB_PARAM_SESSION_INIT;
173 pdev->vcn_enc_cmds.layer_control = RENCODE_V2_IB_PARAM_LAYER_CONTROL;
174 pdev->vcn_enc_cmds.layer_select = RENCODE_V2_IB_PARAM_LAYER_SELECT;
175 pdev->vcn_enc_cmds.rc_session_init = RENCODE_V2_IB_PARAM_RATE_CONTROL_SESSION_INIT;
176 pdev->vcn_enc_cmds.rc_layer_init = RENCODE_V2_IB_PARAM_RATE_CONTROL_LAYER_INIT;
177 pdev->vcn_enc_cmds.rc_per_pic = RENCODE_V2_IB_PARAM_RATE_CONTROL_PER_PIC_EX;
178 pdev->vcn_enc_cmds.quality_params = RENCODE_V2_IB_PARAM_QUALITY_PARAMS;
179 pdev->vcn_enc_cmds.nalu = RENCODE_V2_IB_PARAM_DIRECT_OUTPUT_NALU;
180 pdev->vcn_enc_cmds.slice_header = RENCODE_V2_IB_PARAM_SLICE_HEADER;
181 pdev->vcn_enc_cmds.input_format = RENCODE_V2_IB_PARAM_INPUT_FORMAT;
182 pdev->vcn_enc_cmds.output_format = RENCODE_V2_IB_PARAM_OUTPUT_FORMAT;
183 pdev->vcn_enc_cmds.enc_params = RENCODE_V2_IB_PARAM_ENCODE_PARAMS;
184 pdev->vcn_enc_cmds.intra_refresh = RENCODE_V2_IB_PARAM_INTRA_REFRESH;
185 pdev->vcn_enc_cmds.ctx = RENCODE_V2_IB_PARAM_ENCODE_CONTEXT_BUFFER;
186 pdev->vcn_enc_cmds.bitstream = RENCODE_V2_IB_PARAM_VIDEO_BITSTREAM_BUFFER;
187 pdev->vcn_enc_cmds.feedback = RENCODE_V2_IB_PARAM_FEEDBACK_BUFFER;
188 pdev->vcn_enc_cmds.slice_control_hevc = RENCODE_V2_HEVC_IB_PARAM_SLICE_CONTROL;
189 pdev->vcn_enc_cmds.spec_misc_hevc = RENCODE_V2_HEVC_IB_PARAM_SPEC_MISC;
190 pdev->vcn_enc_cmds.deblocking_filter_hevc = RENCODE_V2_HEVC_IB_PARAM_LOOP_FILTER;
191 pdev->vcn_enc_cmds.slice_control_h264 = RENCODE_V2_H264_IB_PARAM_SLICE_CONTROL;
192 pdev->vcn_enc_cmds.spec_misc_h264 = RENCODE_V2_H264_IB_PARAM_SPEC_MISC;
193 pdev->vcn_enc_cmds.enc_params_h264 = RENCODE_V2_H264_IB_PARAM_ENCODE_PARAMS;
194 pdev->vcn_enc_cmds.deblocking_filter_h264 = RENCODE_V2_H264_IB_PARAM_DEBLOCKING_FILTER;
195 if (pdev->enc_hw_ver == RADV_VIDEO_ENC_HW_4) {
196 pdev->vcn_enc_cmds.enc_statistics = RENCODE_V4_IB_PARAM_ENCODE_STATISTICS;
197 } else
198 pdev->vcn_enc_cmds.enc_statistics = RENCODE_V2_IB_PARAM_ENCODE_STATISTICS;
199 } else {
200 pdev->vcn_enc_cmds.session_info = RENCODE_IB_PARAM_SESSION_INFO;
201 pdev->vcn_enc_cmds.task_info = RENCODE_IB_PARAM_TASK_INFO;
202 pdev->vcn_enc_cmds.session_init = RENCODE_IB_PARAM_SESSION_INIT;
203 pdev->vcn_enc_cmds.layer_control = RENCODE_IB_PARAM_LAYER_CONTROL;
204 pdev->vcn_enc_cmds.layer_select = RENCODE_IB_PARAM_LAYER_SELECT;
205 pdev->vcn_enc_cmds.rc_session_init = RENCODE_IB_PARAM_RATE_CONTROL_SESSION_INIT;
206 pdev->vcn_enc_cmds.rc_layer_init = RENCODE_IB_PARAM_RATE_CONTROL_LAYER_INIT;
207 pdev->vcn_enc_cmds.rc_per_pic = RENCODE_IB_PARAM_RATE_CONTROL_PER_PIC_EX;
208 pdev->vcn_enc_cmds.quality_params = RENCODE_IB_PARAM_QUALITY_PARAMS;
209 pdev->vcn_enc_cmds.nalu = RENCODE_IB_PARAM_DIRECT_OUTPUT_NALU;
210 pdev->vcn_enc_cmds.slice_header = RENCODE_IB_PARAM_SLICE_HEADER;
211 pdev->vcn_enc_cmds.enc_params = RENCODE_IB_PARAM_ENCODE_PARAMS;
212 pdev->vcn_enc_cmds.intra_refresh = RENCODE_IB_PARAM_INTRA_REFRESH;
213 pdev->vcn_enc_cmds.ctx = RENCODE_IB_PARAM_ENCODE_CONTEXT_BUFFER;
214 pdev->vcn_enc_cmds.bitstream = RENCODE_IB_PARAM_VIDEO_BITSTREAM_BUFFER;
215 pdev->vcn_enc_cmds.feedback = RENCODE_IB_PARAM_FEEDBACK_BUFFER;
216 pdev->vcn_enc_cmds.slice_control_hevc = RENCODE_HEVC_IB_PARAM_SLICE_CONTROL;
217 pdev->vcn_enc_cmds.spec_misc_hevc = RENCODE_HEVC_IB_PARAM_SPEC_MISC;
218 pdev->vcn_enc_cmds.deblocking_filter_hevc = RENCODE_HEVC_IB_PARAM_DEBLOCKING_FILTER;
219 pdev->vcn_enc_cmds.slice_control_h264 = RENCODE_H264_IB_PARAM_SLICE_CONTROL;
220 pdev->vcn_enc_cmds.spec_misc_h264 = RENCODE_H264_IB_PARAM_SPEC_MISC;
221 pdev->vcn_enc_cmds.enc_params_h264 = RENCODE_H264_IB_PARAM_ENCODE_PARAMS;
222 pdev->vcn_enc_cmds.deblocking_filter_h264 = RENCODE_H264_IB_PARAM_DEBLOCKING_FILTER;
223 pdev->vcn_enc_cmds.enc_statistics = RENCODE_IB_PARAM_ENCODE_STATISTICS;
224 }
225 }
226
227 /* to process invalid frame rate */
228 static void
radv_vcn_enc_invalid_frame_rate(uint32_t * den,uint32_t * num)229 radv_vcn_enc_invalid_frame_rate(uint32_t *den, uint32_t *num)
230 {
231 if (*den == 0 || *num == 0) {
232 *den = 1;
233 *num = 30;
234 }
235 }
236
237 static uint32_t
radv_vcn_per_frame_integer(uint32_t bitrate,uint32_t den,uint32_t num)238 radv_vcn_per_frame_integer(uint32_t bitrate, uint32_t den, uint32_t num)
239 {
240 uint64_t rate_den = (uint64_t)bitrate * (uint64_t)den;
241
242 return (uint32_t)(rate_den / num);
243 }
244
245 static uint32_t
radv_vcn_per_frame_frac(uint32_t bitrate,uint32_t den,uint32_t num)246 radv_vcn_per_frame_frac(uint32_t bitrate, uint32_t den, uint32_t num)
247 {
248 uint64_t rate_den = (uint64_t)bitrate * (uint64_t)den;
249 uint64_t remainder = rate_den % num;
250
251 return (uint32_t)((remainder << 32) / num);
252 }
253
254 static void
radv_enc_set_emulation_prevention(struct radv_cmd_buffer * cmd_buffer,bool set)255 radv_enc_set_emulation_prevention(struct radv_cmd_buffer *cmd_buffer, bool set)
256 {
257 struct radv_enc_state *enc = &cmd_buffer->video.enc;
258 if (set != enc->emulation_prevention) {
259 enc->emulation_prevention = set;
260 enc->num_zeros = 0;
261 }
262 }
263
264 static uint32_t
radv_enc_value_bits(uint32_t value)265 radv_enc_value_bits(uint32_t value)
266 {
267 uint32_t i = 1;
268
269 while (value > 1) {
270 i++;
271 value >>= 1;
272 }
273
274 return i;
275 }
276
277 static const unsigned index_to_shifts[4] = {24, 16, 8, 0};
278
279 static void
radv_enc_output_one_byte(struct radv_cmd_buffer * cmd_buffer,unsigned char byte)280 radv_enc_output_one_byte(struct radv_cmd_buffer *cmd_buffer, unsigned char byte)
281 {
282 struct radeon_cmdbuf *cs = cmd_buffer->cs;
283 struct radv_enc_state *enc = &cmd_buffer->video.enc;
284 if (enc->byte_index == 0)
285 cs->buf[cs->cdw] = 0;
286 cs->buf[cs->cdw] |= ((unsigned int)(byte) << index_to_shifts[enc->byte_index]);
287 enc->byte_index++;
288
289 if (enc->byte_index >= 4) {
290 enc->byte_index = 0;
291 cs->cdw++;
292 }
293 }
294
295 static void
radv_enc_emulation_prevention(struct radv_cmd_buffer * cmd_buffer,unsigned char byte)296 radv_enc_emulation_prevention(struct radv_cmd_buffer *cmd_buffer, unsigned char byte)
297 {
298 struct radv_enc_state *enc = &cmd_buffer->video.enc;
299 if (enc->emulation_prevention) {
300 if ((enc->num_zeros >= 2) && ((byte == 0x00) || (byte == 0x01) || (byte == 0x02) || (byte == 0x03))) {
301 radv_enc_output_one_byte(cmd_buffer, 0x03);
302 enc->bits_output += 8;
303 enc->num_zeros = 0;
304 }
305 enc->num_zeros = (byte == 0 ? (enc->num_zeros + 1) : 0);
306 }
307 }
308
309 static void
radv_enc_code_fixed_bits(struct radv_cmd_buffer * cmd_buffer,unsigned int value,unsigned int num_bits)310 radv_enc_code_fixed_bits(struct radv_cmd_buffer *cmd_buffer, unsigned int value, unsigned int num_bits)
311 {
312 struct radv_enc_state *enc = &cmd_buffer->video.enc;
313 unsigned int bits_to_pack = 0;
314 enc->bits_size += num_bits;
315
316 while (num_bits > 0) {
317 unsigned int value_to_pack = value & (0xffffffff >> (32 - num_bits));
318 bits_to_pack = num_bits > (32 - enc->bits_in_shifter) ? (32 - enc->bits_in_shifter) : num_bits;
319
320 if (bits_to_pack < num_bits)
321 value_to_pack = value_to_pack >> (num_bits - bits_to_pack);
322
323 enc->shifter |= value_to_pack << (32 - enc->bits_in_shifter - bits_to_pack);
324 num_bits -= bits_to_pack;
325 enc->bits_in_shifter += bits_to_pack;
326
327 while (enc->bits_in_shifter >= 8) {
328 unsigned char output_byte = (unsigned char)(enc->shifter >> 24);
329 enc->shifter <<= 8;
330 radv_enc_emulation_prevention(cmd_buffer, output_byte);
331 radv_enc_output_one_byte(cmd_buffer, output_byte);
332 enc->bits_in_shifter -= 8;
333 enc->bits_output += 8;
334 }
335 }
336 }
337
338 static void
radv_enc_reset(struct radv_cmd_buffer * cmd_buffer)339 radv_enc_reset(struct radv_cmd_buffer *cmd_buffer)
340 {
341 struct radv_enc_state *enc = &cmd_buffer->video.enc;
342 enc->emulation_prevention = false;
343 enc->shifter = 0;
344 enc->bits_in_shifter = 0;
345 enc->bits_output = 0;
346 enc->num_zeros = 0;
347 enc->byte_index = 0;
348 enc->bits_size = 0;
349 }
350
351 static void
radv_enc_byte_align(struct radv_cmd_buffer * cmd_buffer)352 radv_enc_byte_align(struct radv_cmd_buffer *cmd_buffer)
353 {
354 struct radv_enc_state *enc = &cmd_buffer->video.enc;
355 unsigned int num_padding_zeros = (32 - enc->bits_in_shifter) % 8;
356
357 if (num_padding_zeros > 0)
358 radv_enc_code_fixed_bits(cmd_buffer, 0, num_padding_zeros);
359 }
360
361 static void
radv_enc_flush_headers(struct radv_cmd_buffer * cmd_buffer)362 radv_enc_flush_headers(struct radv_cmd_buffer *cmd_buffer)
363 {
364 struct radv_enc_state *enc = &cmd_buffer->video.enc;
365 struct radeon_cmdbuf *cs = cmd_buffer->cs;
366 if (enc->bits_in_shifter != 0) {
367 unsigned char output_byte = (unsigned char)(enc->shifter >> 24);
368 radv_enc_emulation_prevention(cmd_buffer, output_byte);
369 radv_enc_output_one_byte(cmd_buffer, output_byte);
370 enc->bits_output += enc->bits_in_shifter;
371 enc->shifter = 0;
372 enc->bits_in_shifter = 0;
373 enc->num_zeros = 0;
374 }
375
376 if (enc->byte_index > 0) {
377 cs->cdw++;
378 enc->byte_index = 0;
379 }
380 }
381
382 static void
radv_enc_code_ue(struct radv_cmd_buffer * cmd_buffer,unsigned int value)383 radv_enc_code_ue(struct radv_cmd_buffer *cmd_buffer, unsigned int value)
384 {
385 unsigned int x = 0;
386 unsigned int ue_code = value + 1;
387 value += 1;
388
389 while (value) {
390 value = (value >> 1);
391 x += 1;
392 }
393 if (x > 1)
394 radv_enc_code_fixed_bits(cmd_buffer, 0, x - 1);
395 radv_enc_code_fixed_bits(cmd_buffer, ue_code, x);
396 }
397
398 static void
radv_enc_code_se(struct radv_cmd_buffer * cmd_buffer,int value)399 radv_enc_code_se(struct radv_cmd_buffer *cmd_buffer, int value)
400 {
401 unsigned int v = 0;
402
403 if (value != 0)
404 v = (value < 0 ? ((unsigned int)(0 - value) << 1) : (((unsigned int)(value) << 1) - 1));
405
406 radv_enc_code_ue(cmd_buffer, v);
407 }
408
409 #define ENC_BEGIN \
410 { \
411 uint32_t begin = cs->cdw++;
412
413 #define ENC_END \
414 radeon_emit_direct(cs, begin, (cs->cdw - begin) * 4); \
415 cmd_buffer->video.enc.total_task_size += cs->buf[begin]; \
416 }
417
418 static void
radv_enc_session_info(struct radv_cmd_buffer * cmd_buffer)419 radv_enc_session_info(struct radv_cmd_buffer *cmd_buffer)
420 {
421 struct radv_device *device = radv_cmd_buffer_device(cmd_buffer);
422 const struct radv_physical_device *pdev = radv_device_physical(device);
423 struct radeon_cmdbuf *cs = cmd_buffer->cs;
424 ENC_BEGIN;
425 radeon_emit(cs, pdev->vcn_enc_cmds.session_info);
426 radeon_emit(cs, pdev->encoder_interface_version);
427
428 radv_cs_add_buffer(device->ws, cs, cmd_buffer->video.vid->sessionctx.mem->bo);
429 uint64_t va = radv_buffer_get_va(cmd_buffer->video.vid->sessionctx.mem->bo);
430 va += cmd_buffer->video.vid->sessionctx.offset;
431 radeon_emit(cs, va >> 32);
432 radeon_emit(cs, va & 0xffffffff);
433 radeon_emit(cs, RENCODE_ENGINE_TYPE_ENCODE);
434 ENC_END;
435 }
436
437 static void
radv_enc_task_info(struct radv_cmd_buffer * cmd_buffer,bool feedback)438 radv_enc_task_info(struct radv_cmd_buffer *cmd_buffer, bool feedback)
439 {
440 struct radv_device *device = radv_cmd_buffer_device(cmd_buffer);
441 const struct radv_physical_device *pdev = radv_device_physical(device);
442 struct radeon_cmdbuf *cs = cmd_buffer->cs;
443 struct radv_enc_state *enc = &cmd_buffer->video.enc;
444
445 enc->task_id++;
446 ENC_BEGIN;
447 radeon_emit(cs, pdev->vcn_enc_cmds.task_info);
448 enc->task_size_offset = cs->cdw++;
449 radeon_emit(cs, enc->task_id);
450 radeon_emit(cs, feedback ? 1 : 0);
451 ENC_END;
452 }
453
454 static void
radv_enc_session_init(struct radv_cmd_buffer * cmd_buffer,const struct VkVideoEncodeInfoKHR * enc_info)455 radv_enc_session_init(struct radv_cmd_buffer *cmd_buffer, const struct VkVideoEncodeInfoKHR *enc_info)
456 {
457 struct radv_device *device = radv_cmd_buffer_device(cmd_buffer);
458 const struct radv_physical_device *pdev = radv_device_physical(device);
459 struct radv_video_session *vid = cmd_buffer->video.vid;
460 struct radeon_cmdbuf *cs = cmd_buffer->cs;
461 unsigned alignment = 16;
462 if (vid->vk.op == VK_VIDEO_CODEC_OPERATION_ENCODE_H265_BIT_KHR) {
463 alignment = 64;
464 }
465
466 uint32_t w = enc_info->srcPictureResource.codedExtent.width;
467 uint32_t h = enc_info->srcPictureResource.codedExtent.height;
468 uint32_t aligned_picture_width = align(w, alignment);
469 uint32_t aligned_picture_height = align(h, alignment);
470 uint32_t padding_width = aligned_picture_width - w;
471 uint32_t padding_height = aligned_picture_height - h;
472
473 ENC_BEGIN;
474 radeon_emit(cs, pdev->vcn_enc_cmds.session_init);
475 radeon_emit(cs, vid->enc_session.encode_standard);
476 radeon_emit(cs, aligned_picture_width);
477 radeon_emit(cs, aligned_picture_height);
478 radeon_emit(cs, padding_width);
479 radeon_emit(cs, padding_height);
480 radeon_emit(cs, vid->enc_session.pre_encode_mode);
481 radeon_emit(cs, vid->enc_session.pre_encode_chroma_enabled);
482 if (pdev->enc_hw_ver >= RADV_VIDEO_ENC_HW_3) {
483 radeon_emit(cs, 0); // slice output enabled.
484 }
485 radeon_emit(cs, vid->enc_session.display_remote);
486 ENC_END;
487 }
488
489 static void
radv_enc_layer_control(struct radv_cmd_buffer * cmd_buffer,const rvcn_enc_layer_control_t * rc_layer_control)490 radv_enc_layer_control(struct radv_cmd_buffer *cmd_buffer, const rvcn_enc_layer_control_t *rc_layer_control)
491 {
492 struct radv_device *device = radv_cmd_buffer_device(cmd_buffer);
493 const struct radv_physical_device *pdev = radv_device_physical(device);
494 struct radeon_cmdbuf *cs = cmd_buffer->cs;
495 ENC_BEGIN;
496 radeon_emit(cs, pdev->vcn_enc_cmds.layer_control);
497 radeon_emit(cs, rc_layer_control->max_num_temporal_layers); // max num temporal layesr
498 radeon_emit(cs, rc_layer_control->num_temporal_layers); // num temporal layers
499 ENC_END;
500 }
501
502 static void
radv_enc_layer_select(struct radv_cmd_buffer * cmd_buffer,int tl_idx)503 radv_enc_layer_select(struct radv_cmd_buffer *cmd_buffer, int tl_idx)
504 {
505 struct radv_device *device = radv_cmd_buffer_device(cmd_buffer);
506 const struct radv_physical_device *pdev = radv_device_physical(device);
507 struct radeon_cmdbuf *cs = cmd_buffer->cs;
508 ENC_BEGIN;
509 radeon_emit(cs, pdev->vcn_enc_cmds.layer_select);
510 radeon_emit(cs, tl_idx); // temporal layer index
511 ENC_END;
512 }
513
514 static void
radv_enc_slice_control(struct radv_cmd_buffer * cmd_buffer,const struct VkVideoEncodeInfoKHR * enc_info)515 radv_enc_slice_control(struct radv_cmd_buffer *cmd_buffer, const struct VkVideoEncodeInfoKHR *enc_info)
516 {
517 struct radv_device *device = radv_cmd_buffer_device(cmd_buffer);
518 const struct radv_physical_device *pdev = radv_device_physical(device);
519 struct radeon_cmdbuf *cs = cmd_buffer->cs;
520
521 uint32_t num_mbs_in_slice;
522 uint32_t width_in_mbs = enc_info->srcPictureResource.codedExtent.width / 16;
523 uint32_t height_in_mbs = enc_info->srcPictureResource.codedExtent.height / 16;
524 num_mbs_in_slice = width_in_mbs * height_in_mbs;
525 ENC_BEGIN;
526 radeon_emit(cs, pdev->vcn_enc_cmds.slice_control_h264);
527 radeon_emit(cs, RENCODE_H264_SLICE_CONTROL_MODE_FIXED_MBS); // slice control mode
528 radeon_emit(cs, num_mbs_in_slice); // num mbs per slice
529 ENC_END;
530 }
531
532 static void
radv_enc_spec_misc_h264(struct radv_cmd_buffer * cmd_buffer,const struct VkVideoEncodeInfoKHR * enc_info)533 radv_enc_spec_misc_h264(struct radv_cmd_buffer *cmd_buffer, const struct VkVideoEncodeInfoKHR *enc_info)
534 {
535 struct radv_device *device = radv_cmd_buffer_device(cmd_buffer);
536 const struct radv_physical_device *pdev = radv_device_physical(device);
537 struct radeon_cmdbuf *cs = cmd_buffer->cs;
538 const struct VkVideoEncodeH264PictureInfoKHR *h264_picture_info =
539 vk_find_struct_const(enc_info->pNext, VIDEO_ENCODE_H264_PICTURE_INFO_KHR);
540 const StdVideoEncodeH264PictureInfo *pic = h264_picture_info->pStdPictureInfo;
541 const StdVideoH264SequenceParameterSet *sps =
542 vk_video_find_h264_enc_std_sps(&cmd_buffer->video.params->vk, pic->seq_parameter_set_id);
543 const StdVideoH264PictureParameterSet *pps =
544 vk_video_find_h264_enc_std_pps(&cmd_buffer->video.params->vk, pic->pic_parameter_set_id);
545 ENC_BEGIN;
546 radeon_emit(cs, pdev->vcn_enc_cmds.spec_misc_h264);
547 radeon_emit(cs, pps->flags.constrained_intra_pred_flag); // constrained_intra_pred_flag
548 radeon_emit(cs, pps->flags.entropy_coding_mode_flag); // cabac enable
549 radeon_emit(cs, 0); // cabac init idc
550 radeon_emit(cs, 1); // half pel enabled
551 radeon_emit(cs, 1); // quarter pel enabled
552 radeon_emit(cs, cmd_buffer->video.vid->vk.h264.profile_idc); // profile_idc
553 radeon_emit(cs, vk_video_get_h264_level(sps->level_idc));
554
555 if (pdev->enc_hw_ver >= RADV_VIDEO_ENC_HW_3) {
556 radeon_emit(cs, 0); // v3 b_picture_enabled
557 radeon_emit(cs, pps->weighted_bipred_idc); // v3 weighted bipred idc
558 }
559
560 ENC_END;
561 }
562
563 static void
radv_enc_spec_misc_hevc(struct radv_cmd_buffer * cmd_buffer,const struct VkVideoEncodeInfoKHR * enc_info)564 radv_enc_spec_misc_hevc(struct radv_cmd_buffer *cmd_buffer, const struct VkVideoEncodeInfoKHR *enc_info)
565 {
566 struct radv_device *device = radv_cmd_buffer_device(cmd_buffer);
567 const struct radv_physical_device *pdev = radv_device_physical(device);
568 struct radeon_cmdbuf *cs = cmd_buffer->cs;
569 const struct VkVideoEncodeH265PictureInfoKHR *h265_picture_info =
570 vk_find_struct_const(enc_info->pNext, VIDEO_ENCODE_H265_PICTURE_INFO_KHR);
571 const StdVideoEncodeH265PictureInfo *pic = h265_picture_info->pStdPictureInfo;
572 const VkVideoEncodeH265NaluSliceSegmentInfoKHR *h265_slice = &h265_picture_info->pNaluSliceSegmentEntries[0];
573 const StdVideoEncodeH265SliceSegmentHeader *slice = h265_slice->pStdSliceSegmentHeader;
574 const StdVideoH265SequenceParameterSet *sps =
575 vk_video_find_h265_enc_std_sps(&cmd_buffer->video.params->vk, pic->pps_seq_parameter_set_id);
576 const StdVideoH265PictureParameterSet *pps =
577 vk_video_find_h265_enc_std_pps(&cmd_buffer->video.params->vk, pic->pps_pic_parameter_set_id);
578 ENC_BEGIN;
579 radeon_emit(cs, pdev->vcn_enc_cmds.spec_misc_hevc);
580 radeon_emit(cs, sps->log2_min_luma_coding_block_size_minus3);
581 radeon_emit(cs, !sps->flags.amp_enabled_flag);
582 radeon_emit(cs, sps->flags.strong_intra_smoothing_enabled_flag);
583 radeon_emit(cs, pps->flags.constrained_intra_pred_flag);
584 radeon_emit(cs, slice->flags.cabac_init_flag);
585 radeon_emit(cs, 1); // enc->enc_pic.hevc_spec_misc.half_pel_enabled
586 radeon_emit(cs, 1); // enc->enc_pic.hevc_spec_misc.quarter_pel_enabled
587 if (pdev->enc_hw_ver >= RADV_VIDEO_ENC_HW_3) {
588 radeon_emit(cs, !pps->flags.transform_skip_enabled_flag);
589 radeon_emit(cs, pps->flags.cu_qp_delta_enabled_flag);
590 }
591 ENC_END;
592 }
593
594 static void
radv_enc_slice_control_hevc(struct radv_cmd_buffer * cmd_buffer,const struct VkVideoEncodeInfoKHR * enc_info)595 radv_enc_slice_control_hevc(struct radv_cmd_buffer *cmd_buffer, const struct VkVideoEncodeInfoKHR *enc_info)
596 {
597 struct radv_device *device = radv_cmd_buffer_device(cmd_buffer);
598 const struct radv_physical_device *pdev = radv_device_physical(device);
599 struct radeon_cmdbuf *cs = cmd_buffer->cs;
600 const struct VkVideoEncodeH265PictureInfoKHR *h265_picture_info =
601 vk_find_struct_const(enc_info->pNext, VIDEO_ENCODE_H265_PICTURE_INFO_KHR);
602 const StdVideoEncodeH265PictureInfo *pic = h265_picture_info->pStdPictureInfo;
603 const StdVideoH265SequenceParameterSet *sps =
604 vk_video_find_h265_enc_std_sps(&cmd_buffer->video.params->vk, pic->pps_seq_parameter_set_id);
605
606 uint32_t width_in_ctb, height_in_ctb, num_ctbs_in_slice;
607
608 width_in_ctb = sps->pic_width_in_luma_samples / 64;
609 height_in_ctb = sps->pic_height_in_luma_samples / 64;
610 num_ctbs_in_slice = width_in_ctb * height_in_ctb;
611 ENC_BEGIN;
612 radeon_emit(cs, pdev->vcn_enc_cmds.slice_control_hevc);
613 radeon_emit(cs, RENCODE_HEVC_SLICE_CONTROL_MODE_FIXED_CTBS);
614 radeon_emit(cs, num_ctbs_in_slice); // num_ctbs_in_slice
615 radeon_emit(cs, num_ctbs_in_slice); // num_ctbs_in_slice_segment
616 ENC_END;
617 }
618
619 static void
radv_enc_rc_session_init(struct radv_cmd_buffer * cmd_buffer)620 radv_enc_rc_session_init(struct radv_cmd_buffer *cmd_buffer)
621 {
622 struct radv_device *device = radv_cmd_buffer_device(cmd_buffer);
623 const struct radv_physical_device *pdev = radv_device_physical(device);
624 struct radeon_cmdbuf *cs = cmd_buffer->cs;
625 struct radv_video_session *vid = cmd_buffer->video.vid;
626 ENC_BEGIN;
627 radeon_emit(cs, pdev->vcn_enc_cmds.rc_session_init);
628 radeon_emit(cs, vid->enc_rate_control_method); // rate_control_method);
629 radeon_emit(cs, vid->enc_vbv_buffer_level); // vbv_buffer_level);
630 ENC_END;
631 }
632
633 static void
radv_enc_rc_layer_init(struct radv_cmd_buffer * cmd_buffer,rvcn_enc_rate_ctl_layer_init_t * layer_init)634 radv_enc_rc_layer_init(struct radv_cmd_buffer *cmd_buffer, rvcn_enc_rate_ctl_layer_init_t *layer_init)
635 {
636 struct radv_device *device = radv_cmd_buffer_device(cmd_buffer);
637 const struct radv_physical_device *pdev = radv_device_physical(device);
638 struct radeon_cmdbuf *cs = cmd_buffer->cs;
639 ENC_BEGIN;
640 radeon_emit(cs, pdev->vcn_enc_cmds.rc_layer_init);
641 radeon_emit(cs, layer_init->target_bit_rate); // target bit rate
642 radeon_emit(cs, layer_init->peak_bit_rate); // peak bit rate
643 radeon_emit(cs, layer_init->frame_rate_num); // frame rate num
644 radeon_emit(cs, layer_init->frame_rate_den); // frame rate dem
645 radeon_emit(cs, layer_init->vbv_buffer_size); // vbv buffer size
646 radeon_emit(cs, layer_init->avg_target_bits_per_picture); // avg target bits per picture
647 radeon_emit(cs, layer_init->peak_bits_per_picture_integer); // peak bit per picture int
648 radeon_emit(cs, layer_init->peak_bits_per_picture_fractional); // peak bit per picture fract
649 ENC_END;
650 }
651
652 static void
radv_enc_deblocking_filter_h264(struct radv_cmd_buffer * cmd_buffer,const VkVideoEncodeInfoKHR * enc_info)653 radv_enc_deblocking_filter_h264(struct radv_cmd_buffer *cmd_buffer, const VkVideoEncodeInfoKHR *enc_info)
654 {
655 struct radv_device *device = radv_cmd_buffer_device(cmd_buffer);
656 const struct radv_physical_device *pdev = radv_device_physical(device);
657 struct radeon_cmdbuf *cs = cmd_buffer->cs;
658 const struct VkVideoEncodeH264PictureInfoKHR *h264_picture_info =
659 vk_find_struct_const(enc_info->pNext, VIDEO_ENCODE_H264_PICTURE_INFO_KHR);
660 const VkVideoEncodeH264NaluSliceInfoKHR *h264_slice = &h264_picture_info->pNaluSliceEntries[0];
661 const StdVideoEncodeH264SliceHeader *slice = h264_slice->pStdSliceHeader;
662 ENC_BEGIN;
663 radeon_emit(cs, pdev->vcn_enc_cmds.deblocking_filter_h264);
664 radeon_emit(cs, slice->disable_deblocking_filter_idc);
665 radeon_emit(cs, slice->slice_alpha_c0_offset_div2);
666 radeon_emit(cs, slice->slice_beta_offset_div2);
667 radeon_emit(cs, 0); // cb qp offset
668 radeon_emit(cs, 0); // cr qp offset
669 ENC_END;
670 }
671
672 static void
radv_enc_deblocking_filter_hevc(struct radv_cmd_buffer * cmd_buffer,const VkVideoEncodeInfoKHR * enc_info)673 radv_enc_deblocking_filter_hevc(struct radv_cmd_buffer *cmd_buffer, const VkVideoEncodeInfoKHR *enc_info)
674 {
675 struct radv_device *device = radv_cmd_buffer_device(cmd_buffer);
676 const struct radv_physical_device *pdev = radv_device_physical(device);
677 struct radeon_cmdbuf *cs = cmd_buffer->cs;
678 const struct VkVideoEncodeH265PictureInfoKHR *h265_picture_info =
679 vk_find_struct_const(enc_info->pNext, VIDEO_ENCODE_H265_PICTURE_INFO_KHR);
680 const StdVideoEncodeH265PictureInfo *pic = h265_picture_info->pStdPictureInfo;
681 const VkVideoEncodeH265NaluSliceSegmentInfoKHR *h265_slice = &h265_picture_info->pNaluSliceSegmentEntries[0];
682 const StdVideoEncodeH265SliceSegmentHeader *slice = h265_slice->pStdSliceSegmentHeader;
683 const StdVideoH265SequenceParameterSet *sps =
684 vk_video_find_h265_enc_std_sps(&cmd_buffer->video.params->vk, pic->pps_seq_parameter_set_id);
685
686 ENC_BEGIN;
687 radeon_emit(cs, pdev->vcn_enc_cmds.deblocking_filter_hevc);
688 radeon_emit(cs, slice->flags.slice_loop_filter_across_slices_enabled_flag);
689 radeon_emit(cs, slice->flags.slice_deblocking_filter_disabled_flag);
690 radeon_emit(cs, slice->slice_beta_offset_div2);
691 radeon_emit(cs, slice->slice_tc_offset_div2);
692 radeon_emit(cs, slice->slice_cb_qp_offset);
693 radeon_emit(cs, slice->slice_cr_qp_offset);
694 if (pdev->enc_hw_ver >= RADV_VIDEO_ENC_HW_2)
695 radeon_emit(cs, !sps->flags.sample_adaptive_offset_enabled_flag);
696 ENC_END;
697 }
698
699 static void
radv_enc_quality_params(struct radv_cmd_buffer * cmd_buffer)700 radv_enc_quality_params(struct radv_cmd_buffer *cmd_buffer)
701 {
702 struct radv_device *device = radv_cmd_buffer_device(cmd_buffer);
703 const struct radv_physical_device *pdev = radv_device_physical(device);
704 struct radeon_cmdbuf *cs = cmd_buffer->cs;
705 ENC_BEGIN;
706 radeon_emit(cs, pdev->vcn_enc_cmds.quality_params);
707 radeon_emit(cs, 0);
708 radeon_emit(cs, 0);
709 radeon_emit(cs, 0);
710 radeon_emit(cs, 0);
711 if (pdev->enc_hw_ver >= RADV_VIDEO_ENC_HW_2)
712 radeon_emit(cs, 0);
713 ENC_END;
714 }
715
716 static void
radv_enc_slice_header(struct radv_cmd_buffer * cmd_buffer,const VkVideoEncodeInfoKHR * enc_info)717 radv_enc_slice_header(struct radv_cmd_buffer *cmd_buffer, const VkVideoEncodeInfoKHR *enc_info)
718 {
719 struct radv_enc_state *enc = &cmd_buffer->video.enc;
720 uint32_t instruction[RENCODE_SLICE_HEADER_TEMPLATE_MAX_NUM_INSTRUCTIONS] = {0};
721 uint32_t num_bits[RENCODE_SLICE_HEADER_TEMPLATE_MAX_NUM_INSTRUCTIONS] = {0};
722 const struct VkVideoEncodeH264PictureInfoKHR *h264_picture_info =
723 vk_find_struct_const(enc_info->pNext, VIDEO_ENCODE_H264_PICTURE_INFO_KHR);
724 int slice_count = h264_picture_info->naluSliceEntryCount;
725 const StdVideoEncodeH264PictureInfo *pic = h264_picture_info->pStdPictureInfo;
726 const StdVideoH264SequenceParameterSet *sps =
727 vk_video_find_h264_enc_std_sps(&cmd_buffer->video.params->vk, pic->seq_parameter_set_id);
728 const StdVideoH264PictureParameterSet *pps =
729 vk_video_find_h264_enc_std_pps(&cmd_buffer->video.params->vk, pic->pic_parameter_set_id);
730 const VkVideoEncodeH264NaluSliceInfoKHR *slice_info = &h264_picture_info->pNaluSliceEntries[0];
731
732 unsigned int inst_index = 0;
733 unsigned int cdw_start = 0;
734 unsigned int cdw_filled = 0;
735 unsigned int bits_copied = 0;
736
737 assert(slice_count <= 1);
738
739 struct radv_device *device = radv_cmd_buffer_device(cmd_buffer);
740 const struct radv_physical_device *pdev = radv_device_physical(device);
741 struct radeon_cmdbuf *cs = cmd_buffer->cs;
742 ENC_BEGIN;
743 radeon_emit(cs, pdev->vcn_enc_cmds.slice_header);
744 radv_enc_reset(cmd_buffer);
745 radv_enc_set_emulation_prevention(cmd_buffer, false);
746
747 cdw_start = cs->cdw;
748
749 if (pic->flags.IdrPicFlag)
750 radv_enc_code_fixed_bits(cmd_buffer, 0x65, 8);
751 else if (!pic->flags.is_reference)
752 radv_enc_code_fixed_bits(cmd_buffer, 0x01, 8);
753 else
754 radv_enc_code_fixed_bits(cmd_buffer, 0x41, 8);
755
756 radv_enc_flush_headers(cmd_buffer);
757 instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_COPY;
758 num_bits[inst_index] = enc->bits_output - bits_copied;
759 bits_copied = enc->bits_output;
760 inst_index++;
761
762 instruction[inst_index] = RENCODE_H264_HEADER_INSTRUCTION_FIRST_MB;
763 inst_index++;
764
765 switch (pic->primary_pic_type) {
766 case STD_VIDEO_H264_PICTURE_TYPE_I:
767 case STD_VIDEO_H264_PICTURE_TYPE_IDR:
768 default:
769 radv_enc_code_ue(cmd_buffer, 7);
770 break;
771 case STD_VIDEO_H264_PICTURE_TYPE_P:
772 radv_enc_code_ue(cmd_buffer, 5);
773 break;
774 case STD_VIDEO_H264_PICTURE_TYPE_B:
775 radv_enc_code_ue(cmd_buffer, 6);
776 break;
777 }
778 radv_enc_code_ue(cmd_buffer, 0x0);
779
780 unsigned int max_frame_num_bits = sps->log2_max_frame_num_minus4 + 4;
781 radv_enc_code_fixed_bits(cmd_buffer, pic->frame_num % (1 << max_frame_num_bits), max_frame_num_bits);
782 #if 0
783 if (enc->enc_pic.h264_enc_params.input_picture_structure !=
784 RENCODE_H264_PICTURE_STRUCTURE_FRAME) {
785 radv_enc_code_fixed_bits(cmd_buffer, 0x1, 1);
786 radv_enc_code_fixed_bits(cmd_buffer,
787 enc->enc_pic.h264_enc_params.input_picture_structure ==
788 RENCODE_H264_PICTURE_STRUCTURE_BOTTOM_FIELD
789 ? 1
790 : 0,
791 1);
792 }
793 #endif
794
795 if (pic->flags.IdrPicFlag)
796 radv_enc_code_ue(cmd_buffer, pic->idr_pic_id);
797
798 if (sps->pic_order_cnt_type == STD_VIDEO_H264_POC_TYPE_0) {
799 unsigned int max_poc_bits = sps->log2_max_pic_order_cnt_lsb_minus4 + 4;
800 radv_enc_code_fixed_bits(cmd_buffer, pic->PicOrderCnt % (1 << max_poc_bits), max_poc_bits);
801 }
802
803 if (pps->flags.redundant_pic_cnt_present_flag)
804 radv_enc_code_ue(cmd_buffer, 0);
805
806 if (pic->primary_pic_type == STD_VIDEO_H264_PICTURE_TYPE_B) {
807 radv_enc_code_fixed_bits(cmd_buffer, slice_info->pStdSliceHeader->flags.direct_spatial_mv_pred_flag, 1);
808 }
809 const StdVideoEncodeH264ReferenceListsInfo *ref_lists = pic->pRefLists;
810 /* ref_pic_list_modification() */
811 if (pic->primary_pic_type != STD_VIDEO_H264_PICTURE_TYPE_IDR &&
812 pic->primary_pic_type != STD_VIDEO_H264_PICTURE_TYPE_I) {
813
814 /* num ref idx active override flag */
815 radv_enc_code_fixed_bits(cmd_buffer, slice_info->pStdSliceHeader->flags.num_ref_idx_active_override_flag, 1);
816 if (slice_info->pStdSliceHeader->flags.num_ref_idx_active_override_flag) {
817 radv_enc_code_ue(cmd_buffer, ref_lists->num_ref_idx_l0_active_minus1);
818 if (pic->primary_pic_type == STD_VIDEO_H264_PICTURE_TYPE_B)
819 radv_enc_code_ue(cmd_buffer, ref_lists->num_ref_idx_l1_active_minus1);
820 }
821
822 radv_enc_code_fixed_bits(cmd_buffer, ref_lists->flags.ref_pic_list_modification_flag_l0, 1);
823 if (ref_lists->flags.ref_pic_list_modification_flag_l0) {
824 for (unsigned op = 0; op < ref_lists->refList0ModOpCount; op++) {
825 const StdVideoEncodeH264RefListModEntry *entry = &ref_lists->pRefList0ModOperations[op];
826
827 radv_enc_code_ue(cmd_buffer, entry->modification_of_pic_nums_idc);
828 if (entry->modification_of_pic_nums_idc ==
829 STD_VIDEO_H264_MODIFICATION_OF_PIC_NUMS_IDC_SHORT_TERM_SUBTRACT ||
830 entry->modification_of_pic_nums_idc == STD_VIDEO_H264_MODIFICATION_OF_PIC_NUMS_IDC_SHORT_TERM_ADD)
831 radv_enc_code_ue(cmd_buffer, entry->abs_diff_pic_num_minus1);
832 else if (entry->modification_of_pic_nums_idc == STD_VIDEO_H264_MODIFICATION_OF_PIC_NUMS_IDC_LONG_TERM)
833 radv_enc_code_ue(cmd_buffer, entry->long_term_pic_num);
834 }
835 }
836
837 if (pic->primary_pic_type == STD_VIDEO_H264_PICTURE_TYPE_B) {
838 radv_enc_code_fixed_bits(cmd_buffer, ref_lists->flags.ref_pic_list_modification_flag_l1, 1);
839 if (ref_lists->flags.ref_pic_list_modification_flag_l1) {
840 for (unsigned op = 0; op < ref_lists->refList1ModOpCount; op++) {
841 const StdVideoEncodeH264RefListModEntry *entry = &ref_lists->pRefList1ModOperations[op];
842
843 radv_enc_code_ue(cmd_buffer, entry->modification_of_pic_nums_idc);
844 if (entry->modification_of_pic_nums_idc ==
845 STD_VIDEO_H264_MODIFICATION_OF_PIC_NUMS_IDC_SHORT_TERM_SUBTRACT ||
846 entry->modification_of_pic_nums_idc == STD_VIDEO_H264_MODIFICATION_OF_PIC_NUMS_IDC_SHORT_TERM_ADD)
847 radv_enc_code_ue(cmd_buffer, entry->abs_diff_pic_num_minus1);
848 else if (entry->modification_of_pic_nums_idc == STD_VIDEO_H264_MODIFICATION_OF_PIC_NUMS_IDC_LONG_TERM)
849 radv_enc_code_ue(cmd_buffer, entry->long_term_pic_num);
850 }
851 }
852 }
853 }
854
855 if (pic->flags.IdrPicFlag) {
856 radv_enc_code_fixed_bits(cmd_buffer, 0x0, 1);
857 radv_enc_code_fixed_bits(cmd_buffer, pic->flags.long_term_reference_flag, 1); /* long_term_reference_flag */
858 } else if (pic->flags.is_reference) {
859 radv_enc_code_fixed_bits(cmd_buffer, ref_lists->refPicMarkingOpCount > 0 ? 1 : 0, 1);
860 for (unsigned op = 0; op < ref_lists->refPicMarkingOpCount; op++) {
861 const StdVideoEncodeH264RefPicMarkingEntry *entry = &ref_lists->pRefPicMarkingOperations[op];
862 radv_enc_code_ue(cmd_buffer, entry->memory_management_control_operation);
863 if (entry->memory_management_control_operation == STD_VIDEO_H264_MEM_MGMT_CONTROL_OP_UNMARK_SHORT_TERM ||
864 entry->memory_management_control_operation == STD_VIDEO_H264_MEM_MGMT_CONTROL_OP_MARK_LONG_TERM)
865 radv_enc_code_ue(cmd_buffer, entry->difference_of_pic_nums_minus1);
866 if (entry->memory_management_control_operation == STD_VIDEO_H264_MEM_MGMT_CONTROL_OP_UNMARK_LONG_TERM)
867 radv_enc_code_ue(cmd_buffer, entry->long_term_pic_num);
868 if (entry->memory_management_control_operation == STD_VIDEO_H264_MEM_MGMT_CONTROL_OP_MARK_LONG_TERM ||
869 entry->memory_management_control_operation == STD_VIDEO_H264_MEM_MGMT_CONTROL_OP_MARK_CURRENT_AS_LONG_TERM)
870 radv_enc_code_ue(cmd_buffer, entry->long_term_frame_idx);
871 if (entry->memory_management_control_operation == STD_VIDEO_H264_MEM_MGMT_CONTROL_OP_SET_MAX_LONG_TERM_INDEX)
872 radv_enc_code_ue(cmd_buffer, entry->max_long_term_frame_idx_plus1);
873 if (entry->memory_management_control_operation == STD_VIDEO_H264_MEM_MGMT_CONTROL_OP_END)
874 break;
875 }
876 }
877
878 if (pic->primary_pic_type != STD_VIDEO_H264_PICTURE_TYPE_IDR &&
879 pic->primary_pic_type != STD_VIDEO_H264_PICTURE_TYPE_I && pps->flags.entropy_coding_mode_flag)
880 radv_enc_code_ue(cmd_buffer, slice_info->pStdSliceHeader->cabac_init_idc);
881
882 radv_enc_flush_headers(cmd_buffer);
883 instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_COPY;
884 num_bits[inst_index] = enc->bits_output - bits_copied;
885 bits_copied = enc->bits_output;
886 inst_index++;
887
888 instruction[inst_index] = RENCODE_H264_HEADER_INSTRUCTION_SLICE_QP_DELTA;
889 inst_index++;
890
891 if (pps->flags.deblocking_filter_control_present_flag) {
892 radv_enc_code_ue(cmd_buffer, slice_info->pStdSliceHeader->disable_deblocking_filter_idc);
893 if (!slice_info->pStdSliceHeader->disable_deblocking_filter_idc) {
894 radv_enc_code_se(cmd_buffer, slice_info->pStdSliceHeader->slice_alpha_c0_offset_div2);
895 radv_enc_code_se(cmd_buffer, slice_info->pStdSliceHeader->slice_beta_offset_div2);
896 }
897 }
898
899 radv_enc_flush_headers(cmd_buffer);
900 instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_COPY;
901 num_bits[inst_index] = enc->bits_output - bits_copied;
902 bits_copied = enc->bits_output;
903 inst_index++;
904
905 instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_END;
906
907 cdw_filled = cs->cdw - cdw_start;
908 for (int i = 0; i < RENCODE_SLICE_HEADER_TEMPLATE_MAX_TEMPLATE_SIZE_IN_DWORDS - cdw_filled; i++)
909 radeon_emit(cs, 0x00000000);
910 for (int j = 0; j < RENCODE_SLICE_HEADER_TEMPLATE_MAX_NUM_INSTRUCTIONS; j++) {
911 radeon_emit(cs, instruction[j]);
912 radeon_emit(cs, num_bits[j]);
913 }
914 ENC_END;
915 }
916
917 static void
radv_enc_slice_header_hevc(struct radv_cmd_buffer * cmd_buffer,const VkVideoEncodeInfoKHR * enc_info)918 radv_enc_slice_header_hevc(struct radv_cmd_buffer *cmd_buffer, const VkVideoEncodeInfoKHR *enc_info)
919 {
920 struct radv_enc_state *enc = &cmd_buffer->video.enc;
921 uint32_t instruction[RENCODE_SLICE_HEADER_TEMPLATE_MAX_NUM_INSTRUCTIONS] = {0};
922 uint32_t num_bits[RENCODE_SLICE_HEADER_TEMPLATE_MAX_NUM_INSTRUCTIONS] = {0};
923 const struct VkVideoEncodeH265PictureInfoKHR *h265_picture_info =
924 vk_find_struct_const(enc_info->pNext, VIDEO_ENCODE_H265_PICTURE_INFO_KHR);
925 const StdVideoEncodeH265PictureInfo *pic = h265_picture_info->pStdPictureInfo;
926 const VkVideoEncodeH265NaluSliceSegmentInfoKHR *h265_slice = &h265_picture_info->pNaluSliceSegmentEntries[0];
927 const StdVideoEncodeH265SliceSegmentHeader *slice = h265_slice->pStdSliceSegmentHeader;
928 const StdVideoH265SequenceParameterSet *sps =
929 vk_video_find_h265_enc_std_sps(&cmd_buffer->video.params->vk, pic->pps_seq_parameter_set_id);
930 const StdVideoH265PictureParameterSet *pps =
931 vk_video_find_h265_enc_std_pps(&cmd_buffer->video.params->vk, pic->pps_pic_parameter_set_id);
932 unsigned int inst_index = 0;
933 unsigned int cdw_start = 0;
934 unsigned int cdw_filled = 0;
935 unsigned int bits_copied = 0;
936 struct radv_device *device = radv_cmd_buffer_device(cmd_buffer);
937 const struct radv_physical_device *pdev = radv_device_physical(device);
938 struct radeon_cmdbuf *cs = cmd_buffer->cs;
939 unsigned nal_unit_type = vk_video_get_h265_nal_unit(pic);
940
941 ENC_BEGIN;
942 radeon_emit(cs, pdev->vcn_enc_cmds.slice_header);
943 radv_enc_reset(cmd_buffer);
944 radv_enc_set_emulation_prevention(cmd_buffer, false);
945
946 cdw_start = cs->cdw;
947 radv_enc_code_fixed_bits(cmd_buffer, 0x0, 1);
948 radv_enc_code_fixed_bits(cmd_buffer, nal_unit_type, 6);
949 radv_enc_code_fixed_bits(cmd_buffer, 0x0, 6);
950 radv_enc_code_fixed_bits(cmd_buffer, 0x1, 3);
951
952 radv_enc_flush_headers(cmd_buffer);
953 instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_COPY;
954 num_bits[inst_index] = enc->bits_output - bits_copied;
955 bits_copied = enc->bits_output;
956 inst_index++;
957
958 instruction[inst_index] = RENCODE_HEVC_HEADER_INSTRUCTION_FIRST_SLICE;
959 inst_index++;
960
961 if ((nal_unit_type >= 16) && (nal_unit_type <= 23))
962 radv_enc_code_fixed_bits(cmd_buffer, 0x0, 1);
963
964 radv_enc_code_ue(cmd_buffer, pic->pps_pic_parameter_set_id);
965
966 radv_enc_flush_headers(cmd_buffer);
967 instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_COPY;
968 num_bits[inst_index] = enc->bits_output - bits_copied;
969 bits_copied = enc->bits_output;
970 inst_index++;
971
972 instruction[inst_index] = RENCODE_HEVC_HEADER_INSTRUCTION_SLICE_SEGMENT;
973 inst_index++;
974
975 instruction[inst_index] = RENCODE_HEVC_HEADER_INSTRUCTION_DEPENDENT_SLICE_END;
976 inst_index++;
977
978 /* slice_type */
979 switch (pic->pic_type) {
980 case STD_VIDEO_H265_PICTURE_TYPE_I:
981 case STD_VIDEO_H265_PICTURE_TYPE_IDR:
982 radv_enc_code_ue(cmd_buffer, 0x2);
983 break;
984 case STD_VIDEO_H265_PICTURE_TYPE_P:
985 radv_enc_code_ue(cmd_buffer, 0x1);
986 break;
987 case STD_VIDEO_H265_PICTURE_TYPE_B:
988 radv_enc_code_ue(cmd_buffer, 0x0);
989 break;
990 default:
991 radv_enc_code_ue(cmd_buffer, 0x1);
992 }
993
994 if ((nal_unit_type != 19) && nal_unit_type != 20) {
995 /* slice_pic_order_cnt_lsb */
996 unsigned int max_poc_bits = sps->log2_max_pic_order_cnt_lsb_minus4 + 4;
997 radv_enc_code_fixed_bits(cmd_buffer, pic->PicOrderCntVal % (1 << max_poc_bits), max_poc_bits);
998 radv_enc_code_fixed_bits(cmd_buffer, pic->flags.short_term_ref_pic_set_sps_flag, 0x1);
999 if (!pic->flags.short_term_ref_pic_set_sps_flag) {
1000 int st_rps_idx = sps->num_short_term_ref_pic_sets;
1001 const StdVideoH265ShortTermRefPicSet *rps = &pic->pShortTermRefPicSet[st_rps_idx];
1002
1003 if (st_rps_idx != 0)
1004 radv_enc_code_fixed_bits(cmd_buffer, rps->flags.inter_ref_pic_set_prediction_flag, 0x1);
1005
1006 if (rps->flags.inter_ref_pic_set_prediction_flag) {
1007 int ref_rps_idx = st_rps_idx - (rps->delta_idx_minus1 + 1);
1008 if (st_rps_idx == sps->num_short_term_ref_pic_sets)
1009 radv_enc_code_ue(cmd_buffer, rps->delta_idx_minus1);
1010 radv_enc_code_fixed_bits(cmd_buffer, rps->flags.delta_rps_sign, 0x1);
1011 radv_enc_code_ue(cmd_buffer, rps->abs_delta_rps_minus1);
1012
1013 const StdVideoH265ShortTermRefPicSet *rps_ref = &sps->pShortTermRefPicSet[ref_rps_idx];
1014 int num_delta_pocs = rps_ref->num_negative_pics + rps_ref->num_positive_pics;
1015 for (int j = 0; j < num_delta_pocs; j++) {
1016 radv_enc_code_fixed_bits(cmd_buffer, !!(rps->used_by_curr_pic_flag & (1 << j)), 0x1);
1017 if (!(rps->used_by_curr_pic_flag & (1 << j))) {
1018 radv_enc_code_fixed_bits(cmd_buffer, !!(rps->use_delta_flag & (1 << j)), 0x1);
1019 }
1020 }
1021 } else {
1022 radv_enc_code_ue(cmd_buffer, rps->num_negative_pics);
1023 radv_enc_code_ue(cmd_buffer, rps->num_positive_pics);
1024
1025 for (int i = 0; i < rps->num_negative_pics; i++) {
1026 radv_enc_code_ue(cmd_buffer, rps->delta_poc_s0_minus1[i]);
1027 radv_enc_code_fixed_bits(cmd_buffer, !!(rps->used_by_curr_pic_s0_flag & (1 << i)), 0x1);
1028 }
1029 for (int i = 0; i < rps->num_positive_pics; i++) {
1030 radv_enc_code_ue(cmd_buffer, rps->delta_poc_s1_minus1[i]);
1031 radv_enc_code_fixed_bits(cmd_buffer, !!(rps->used_by_curr_pic_s1_flag & (1 << i)), 0x1);
1032 }
1033 }
1034 } else if (sps->num_short_term_ref_pic_sets > 1)
1035 radv_enc_code_ue(cmd_buffer, pic->short_term_ref_pic_set_idx);
1036
1037 if (sps->flags.sps_temporal_mvp_enabled_flag)
1038 radv_enc_code_fixed_bits(cmd_buffer, pic->flags.slice_temporal_mvp_enabled_flag, 1);
1039 }
1040
1041 if (sps->flags.sample_adaptive_offset_enabled_flag) {
1042 radv_enc_flush_headers(cmd_buffer);
1043 instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_COPY;
1044 num_bits[inst_index] = enc->bits_output - bits_copied;
1045 bits_copied = enc->bits_output;
1046 inst_index++;
1047
1048 instruction[inst_index] = RENCODE_HEVC_HEADER_INSTRUCTION_SAO_ENABLE;
1049 inst_index++;
1050 }
1051
1052 if ((pic->pic_type == STD_VIDEO_H265_PICTURE_TYPE_P) || (pic->pic_type == STD_VIDEO_H265_PICTURE_TYPE_B)) {
1053 radv_enc_code_fixed_bits(cmd_buffer, slice->flags.num_ref_idx_active_override_flag, 1);
1054 if (slice->flags.num_ref_idx_active_override_flag) {
1055 radv_enc_code_ue(cmd_buffer, pic->pRefLists->num_ref_idx_l0_active_minus1);
1056 if (pic->pic_type == STD_VIDEO_H265_PICTURE_TYPE_B)
1057 radv_enc_code_ue(cmd_buffer, pic->pRefLists->num_ref_idx_l1_active_minus1);
1058 }
1059 if (pic->pic_type == STD_VIDEO_H265_PICTURE_TYPE_B)
1060 radv_enc_code_fixed_bits(cmd_buffer, slice->flags.mvd_l1_zero_flag, 1);
1061 if (pps->flags.cabac_init_present_flag)
1062 radv_enc_code_fixed_bits(cmd_buffer, slice->flags.cabac_init_flag, 1);
1063 if (pic->flags.slice_temporal_mvp_enabled_flag) {
1064 if (pic->pic_type == STD_VIDEO_H265_PICTURE_TYPE_B)
1065 radv_enc_code_fixed_bits(cmd_buffer, slice->flags.collocated_from_l0_flag, 1);
1066 }
1067 radv_enc_code_ue(cmd_buffer, 5 - slice->MaxNumMergeCand);
1068 }
1069
1070 radv_enc_flush_headers(cmd_buffer);
1071 instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_COPY;
1072 num_bits[inst_index] = enc->bits_output - bits_copied;
1073 bits_copied = enc->bits_output;
1074 inst_index++;
1075
1076 instruction[inst_index] = RENCODE_HEVC_HEADER_INSTRUCTION_SLICE_QP_DELTA;
1077 inst_index++;
1078
1079 if (pps->flags.pps_slice_chroma_qp_offsets_present_flag) {
1080 radv_enc_code_se(cmd_buffer, slice->slice_cb_qp_offset);
1081 radv_enc_code_se(cmd_buffer, slice->slice_cr_qp_offset);
1082 }
1083
1084 if (pps->flags.pps_slice_act_qp_offsets_present_flag) {
1085 radv_enc_code_se(cmd_buffer, slice->slice_act_y_qp_offset);
1086 radv_enc_code_se(cmd_buffer, slice->slice_act_cb_qp_offset);
1087 radv_enc_code_se(cmd_buffer, slice->slice_act_cr_qp_offset);
1088 }
1089
1090 if (pps->flags.chroma_qp_offset_list_enabled_flag) {
1091 radv_enc_code_fixed_bits(cmd_buffer, slice->flags.cu_chroma_qp_offset_enabled_flag, 1);
1092 }
1093
1094 if (pps->flags.deblocking_filter_override_enabled_flag) {
1095 radv_enc_code_fixed_bits(cmd_buffer, slice->flags.deblocking_filter_override_flag, 1);
1096 if (slice->flags.deblocking_filter_override_flag) {
1097 radv_enc_code_fixed_bits(cmd_buffer, slice->flags.slice_deblocking_filter_disabled_flag, 1);
1098 if (!slice->flags.slice_deblocking_filter_disabled_flag) {
1099 radv_enc_code_se(cmd_buffer, slice->slice_beta_offset_div2);
1100 radv_enc_code_se(cmd_buffer, slice->slice_tc_offset_div2);
1101 }
1102 }
1103 }
1104 if ((pps->flags.pps_loop_filter_across_slices_enabled_flag) &&
1105 (!slice->flags.slice_deblocking_filter_disabled_flag || slice->flags.slice_sao_luma_flag ||
1106 slice->flags.slice_sao_chroma_flag)) {
1107
1108 if (slice->flags.slice_sao_luma_flag || slice->flags.slice_sao_chroma_flag) {
1109 instruction[inst_index] = RENCODE_HEVC_HEADER_INSTRUCTION_LOOP_FILTER_ACROSS_SLICES_ENABLE;
1110 inst_index++;
1111 } else {
1112 radv_enc_code_fixed_bits(cmd_buffer, slice->flags.slice_loop_filter_across_slices_enabled_flag, 1);
1113 radv_enc_flush_headers(cmd_buffer);
1114 instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_COPY;
1115 num_bits[inst_index] = enc->bits_output - bits_copied;
1116 bits_copied = enc->bits_output;
1117 inst_index++;
1118 }
1119 }
1120
1121 instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_END;
1122
1123 cdw_filled = cs->cdw - cdw_start;
1124 for (int i = 0; i < RENCODE_SLICE_HEADER_TEMPLATE_MAX_TEMPLATE_SIZE_IN_DWORDS - cdw_filled; i++)
1125 radeon_emit(cs, 0x00000000);
1126 for (int j = 0; j < RENCODE_SLICE_HEADER_TEMPLATE_MAX_NUM_INSTRUCTIONS; j++) {
1127 radeon_emit(cs, instruction[j]);
1128 radeon_emit(cs, num_bits[j]);
1129 }
1130 ENC_END;
1131 }
1132
1133 static void
radv_enc_ctx(struct radv_cmd_buffer * cmd_buffer,const VkVideoEncodeInfoKHR * info)1134 radv_enc_ctx(struct radv_cmd_buffer *cmd_buffer, const VkVideoEncodeInfoKHR *info)
1135 {
1136 struct radv_device *device = radv_cmd_buffer_device(cmd_buffer);
1137 const struct radv_physical_device *pdev = radv_device_physical(device);
1138 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1139 struct radv_image_view *dpb_iv = NULL;
1140 struct radv_image *dpb = NULL;
1141 struct radv_image_plane *dpb_luma = NULL;
1142 struct radv_image_plane *dpb_chroma = NULL;
1143 uint64_t va = 0;
1144 uint32_t luma_pitch = 0;
1145 int max_ref_slot_idx = 0;
1146
1147 if (info->pSetupReferenceSlot) {
1148 dpb_iv = radv_image_view_from_handle(info->pSetupReferenceSlot->pPictureResource->imageViewBinding);
1149 if (info->pSetupReferenceSlot->slotIndex > max_ref_slot_idx)
1150 max_ref_slot_idx = info->pSetupReferenceSlot->slotIndex;
1151 }
1152
1153 if (info->referenceSlotCount > 0) {
1154 dpb_iv = radv_image_view_from_handle(info->pReferenceSlots[0].pPictureResource->imageViewBinding);
1155 for (unsigned i = 0; i < info->referenceSlotCount; i++) {
1156 if (info->pReferenceSlots[i].slotIndex > max_ref_slot_idx)
1157 max_ref_slot_idx = info->pReferenceSlots[i].slotIndex;
1158 }
1159 }
1160
1161 if (dpb_iv) {
1162 dpb = dpb_iv->image;
1163 dpb_luma = &dpb->planes[0];
1164 dpb_chroma = &dpb->planes[1];
1165 radv_cs_add_buffer(device->ws, cs, dpb->bindings[0].bo);
1166 va = radv_buffer_get_va(dpb->bindings[0].bo) + dpb->bindings[0].offset; // TODO DPB resource
1167 luma_pitch = dpb_luma->surface.u.gfx9.surf_pitch * dpb_luma->surface.blk_w; // rec_luma_pitch
1168 }
1169
1170 uint32_t swizzle_mode = 0;
1171
1172 if (pdev->enc_hw_ver >= RADV_VIDEO_ENC_HW_4)
1173 swizzle_mode = RENCODE_REC_SWIZZLE_MODE_256B_D;
1174 else if (pdev->enc_hw_ver >= RADV_VIDEO_ENC_HW_2)
1175 swizzle_mode = RENCODE_REC_SWIZZLE_MODE_256B_S;
1176 ENC_BEGIN;
1177 radeon_emit(cs, pdev->vcn_enc_cmds.ctx);
1178 radeon_emit(cs, va >> 32);
1179 radeon_emit(cs, va & 0xffffffff);
1180 radeon_emit(cs, swizzle_mode);
1181 radeon_emit(cs, luma_pitch); // rec_luma_pitch
1182 radeon_emit(cs, luma_pitch); // rec_luma_pitch0); //rec_chromma_pitch
1183 radeon_emit(cs, max_ref_slot_idx + 1); // num_reconstructed_pictures
1184
1185 int i;
1186 for (i = 0; i < max_ref_slot_idx + 1; i++) {
1187 radeon_emit(cs, dpb_luma ? dpb_luma->surface.u.gfx9.surf_offset + i * dpb_luma->surface.u.gfx9.surf_slice_size
1188 : 0); // luma offset
1189 radeon_emit(cs, dpb_chroma
1190 ? dpb_chroma->surface.u.gfx9.surf_offset + i * dpb_chroma->surface.u.gfx9.surf_slice_size
1191 : 0); // chroma offset
1192
1193 if (pdev->enc_hw_ver >= RADV_VIDEO_ENC_HW_4) {
1194 radeon_emit(cs, 0); /* unused offset 1 */
1195 radeon_emit(cs, 0); /* unused offset 2 */
1196 }
1197 }
1198
1199 for (; i < RENCODE_MAX_NUM_RECONSTRUCTED_PICTURES; i++) {
1200 radeon_emit(cs, 0);
1201 radeon_emit(cs, 0);
1202 if (pdev->enc_hw_ver >= RADV_VIDEO_ENC_HW_4) {
1203 radeon_emit(cs, 0); /* unused offset 1 */
1204 radeon_emit(cs, 0); /* unused offset 2 */
1205 }
1206 }
1207
1208 if (pdev->enc_hw_ver == RADV_VIDEO_ENC_HW_3) {
1209 radeon_emit(cs, 0); // colloc buffer offset
1210 }
1211 radeon_emit(cs, 0); // enc pic pre encode luma pitch
1212 radeon_emit(cs, 0); // enc pic pre encode chroma pitch
1213
1214 for (i = 0; i < RENCODE_MAX_NUM_RECONSTRUCTED_PICTURES; i++) {
1215 radeon_emit(cs, 0); // pre encode luma offset
1216 radeon_emit(cs, 0); // pre encode chroma offset
1217 if (pdev->enc_hw_ver >= RADV_VIDEO_ENC_HW_4) {
1218 radeon_emit(cs, 0); /* unused offset 1 */
1219 radeon_emit(cs, 0); /* unused offset 2 */
1220 }
1221 }
1222
1223 if (pdev->enc_hw_ver == RADV_VIDEO_ENC_HW_2) {
1224 radeon_emit(cs, 0); // enc pic yuv luma offset
1225 radeon_emit(cs, 0); // enc pic yuv chroma offset
1226
1227 radeon_emit(cs, 0); // two pass search center map offset
1228
1229 // rgboffsets
1230 radeon_emit(cs, 0); // red
1231 radeon_emit(cs, 0); // green
1232 radeon_emit(cs, 0); // blue
1233 } else if (pdev->enc_hw_ver >= RADV_VIDEO_ENC_HW_3) {
1234 radeon_emit(cs, 0); // red
1235 radeon_emit(cs, 0); // green
1236 radeon_emit(cs, 0); // blue
1237 radeon_emit(cs, 0); // v3 two pass search center map offset
1238 radeon_emit(cs, 0);
1239 if (pdev->enc_hw_ver == RADV_VIDEO_ENC_HW_3) {
1240 radeon_emit(cs, 0);
1241 }
1242 }
1243 ENC_END;
1244 }
1245
1246 static void
radv_enc_bitstream(struct radv_cmd_buffer * cmd_buffer,struct radv_buffer * buffer,VkDeviceSize offset)1247 radv_enc_bitstream(struct radv_cmd_buffer *cmd_buffer, struct radv_buffer *buffer, VkDeviceSize offset)
1248 {
1249 struct radv_device *device = radv_cmd_buffer_device(cmd_buffer);
1250 const struct radv_physical_device *pdev = radv_device_physical(device);
1251 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1252 uint64_t va = radv_buffer_get_va(buffer->bo) + buffer->offset;
1253 radv_cs_add_buffer(device->ws, cs, buffer->bo);
1254
1255 ENC_BEGIN;
1256 radeon_emit(cs, pdev->vcn_enc_cmds.bitstream);
1257 radeon_emit(cs, RENCODE_REC_SWIZZLE_MODE_LINEAR);
1258 radeon_emit(cs, va >> 32);
1259 radeon_emit(cs, va & 0xffffffff);
1260 radeon_emit(cs, buffer->vk.size);
1261 radeon_emit(cs, offset);
1262 ENC_END;
1263 }
1264
1265 static void
radv_enc_feedback(struct radv_cmd_buffer * cmd_buffer,uint64_t feedback_query_va)1266 radv_enc_feedback(struct radv_cmd_buffer *cmd_buffer, uint64_t feedback_query_va)
1267 {
1268 struct radv_device *device = radv_cmd_buffer_device(cmd_buffer);
1269 const struct radv_physical_device *pdev = radv_device_physical(device);
1270 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1271 ENC_BEGIN;
1272
1273 radeon_emit(cs, pdev->vcn_enc_cmds.feedback);
1274 radeon_emit(cs, RENCODE_FEEDBACK_BUFFER_MODE_LINEAR);
1275 radeon_emit(cs, feedback_query_va >> 32);
1276 radeon_emit(cs, feedback_query_va & 0xffffffff);
1277 radeon_emit(cs, 16); // buffer_size
1278 radeon_emit(cs, 40); // data_size
1279 ENC_END;
1280 }
1281
1282 static void
radv_enc_intra_refresh(struct radv_cmd_buffer * cmd_buffer)1283 radv_enc_intra_refresh(struct radv_cmd_buffer *cmd_buffer)
1284 {
1285 struct radv_device *device = radv_cmd_buffer_device(cmd_buffer);
1286 const struct radv_physical_device *pdev = radv_device_physical(device);
1287 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1288 ENC_BEGIN;
1289 radeon_emit(cs, pdev->vcn_enc_cmds.intra_refresh);
1290 radeon_emit(cs, 0); // intra refresh mode
1291 radeon_emit(cs, 0); // intra ref offset
1292 radeon_emit(cs, 0); // intra region size
1293 ENC_END;
1294 }
1295
1296 static void
radv_enc_rc_per_pic(struct radv_cmd_buffer * cmd_buffer,const VkVideoEncodeInfoKHR * enc_info,rvcn_enc_rate_ctl_per_picture_t * per_pic)1297 radv_enc_rc_per_pic(struct radv_cmd_buffer *cmd_buffer, const VkVideoEncodeInfoKHR *enc_info,
1298 rvcn_enc_rate_ctl_per_picture_t *per_pic)
1299 {
1300 struct radv_video_session *vid = cmd_buffer->video.vid;
1301 struct radv_device *device = radv_cmd_buffer_device(cmd_buffer);
1302 const struct radv_physical_device *pdev = radv_device_physical(device);
1303 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1304
1305 unsigned qp = per_pic->qp_i;
1306
1307 if (vid->enc_rate_control_method == RENCODE_RATE_CONTROL_METHOD_NONE && !vid->enc_rate_control_default) {
1308 switch (vid->vk.op) {
1309 case VK_VIDEO_CODEC_OPERATION_ENCODE_H264_BIT_KHR: {
1310 const struct VkVideoEncodeH264PictureInfoKHR *h264_picture_info =
1311 vk_find_struct_const(enc_info->pNext, VIDEO_ENCODE_H264_PICTURE_INFO_KHR);
1312 const VkVideoEncodeH264NaluSliceInfoKHR *h264_slice = &h264_picture_info->pNaluSliceEntries[0];
1313 qp = h264_slice->constantQp;
1314 break;
1315 }
1316 case VK_VIDEO_CODEC_OPERATION_ENCODE_H265_BIT_KHR: {
1317 const struct VkVideoEncodeH265PictureInfoKHR *h265_picture_info =
1318 vk_find_struct_const(enc_info->pNext, VIDEO_ENCODE_H265_PICTURE_INFO_KHR);
1319 const VkVideoEncodeH265NaluSliceSegmentInfoKHR *h265_slice = &h265_picture_info->pNaluSliceSegmentEntries[0];
1320 qp = h265_slice->constantQp;
1321 break;
1322 }
1323 default:
1324 break;
1325 }
1326 }
1327 ENC_BEGIN;
1328 radeon_emit(cs, pdev->vcn_enc_cmds.rc_per_pic);
1329 radeon_emit(cs, qp); // qp_i
1330 radeon_emit(cs, qp); // qp_p
1331 radeon_emit(cs, qp); // qp_b
1332 radeon_emit(cs, per_pic->min_qp_i);
1333 radeon_emit(cs, per_pic->max_qp_i);
1334 radeon_emit(cs, per_pic->min_qp_p);
1335 radeon_emit(cs, per_pic->max_qp_p);
1336 radeon_emit(cs, per_pic->min_qp_b);
1337 radeon_emit(cs, per_pic->max_qp_b);
1338 radeon_emit(cs, per_pic->max_au_size_i);
1339 radeon_emit(cs, per_pic->max_au_size_p);
1340 radeon_emit(cs, per_pic->max_au_size_b);
1341 radeon_emit(cs, per_pic->enabled_filler_data);
1342 radeon_emit(cs, per_pic->skip_frame_enable);
1343 radeon_emit(cs, per_pic->enforce_hrd);
1344 radeon_emit(cs, 0xFFFFFFFF); // reserved_0xff
1345 ENC_END;
1346 }
1347
1348 static void
radv_enc_params(struct radv_cmd_buffer * cmd_buffer,const VkVideoEncodeInfoKHR * enc_info)1349 radv_enc_params(struct radv_cmd_buffer *cmd_buffer, const VkVideoEncodeInfoKHR *enc_info)
1350 {
1351 const struct VkVideoEncodeH264PictureInfoKHR *h264_picture_info =
1352 vk_find_struct_const(enc_info->pNext, VIDEO_ENCODE_H264_PICTURE_INFO_KHR);
1353 const struct VkVideoEncodeH265PictureInfoKHR *h265_picture_info =
1354 vk_find_struct_const(enc_info->pNext, VIDEO_ENCODE_H265_PICTURE_INFO_KHR);
1355 const StdVideoEncodeH264PictureInfo *h264_pic = h264_picture_info ? h264_picture_info->pStdPictureInfo : NULL;
1356 const StdVideoEncodeH265PictureInfo *h265_pic = h265_picture_info ? h265_picture_info->pStdPictureInfo : NULL;
1357 struct radv_image_view *src_iv = radv_image_view_from_handle(enc_info->srcPictureResource.imageViewBinding);
1358 struct radv_image *src_img = src_iv->image;
1359 struct radv_device *device = radv_cmd_buffer_device(cmd_buffer);
1360 const struct radv_physical_device *pdev = radv_device_physical(device);
1361 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1362 uint64_t va = radv_buffer_get_va(src_img->bindings[0].bo) + src_img->bindings[0].offset;
1363 uint64_t luma_va = va + src_img->planes[0].surface.u.gfx9.surf_offset;
1364 uint64_t chroma_va = va + src_img->planes[1].surface.u.gfx9.surf_offset;
1365 uint32_t pic_type;
1366 unsigned int slot_idx = 0xffffffff;
1367
1368 radv_cs_add_buffer(device->ws, cs, src_img->bindings[0].bo);
1369 if (h264_pic) {
1370 switch (h264_pic->primary_pic_type) {
1371 case STD_VIDEO_H264_PICTURE_TYPE_P:
1372 slot_idx = enc_info->pReferenceSlots[0].slotIndex;
1373 pic_type = RENCODE_PICTURE_TYPE_P;
1374 break;
1375 case STD_VIDEO_H264_PICTURE_TYPE_B:
1376 slot_idx = enc_info->pReferenceSlots[0].slotIndex;
1377 pic_type = RENCODE_PICTURE_TYPE_B;
1378 break;
1379 case STD_VIDEO_H264_PICTURE_TYPE_I:
1380 case STD_VIDEO_H264_PICTURE_TYPE_IDR:
1381 default:
1382 pic_type = RENCODE_PICTURE_TYPE_I;
1383 break;
1384 }
1385 radv_enc_layer_select(cmd_buffer, h264_pic->temporal_id);
1386 } else if (h265_pic) {
1387 switch (h265_pic->pic_type) {
1388 case STD_VIDEO_H265_PICTURE_TYPE_P:
1389 slot_idx = enc_info->pReferenceSlots[0].slotIndex;
1390 pic_type = RENCODE_PICTURE_TYPE_P;
1391 break;
1392 case STD_VIDEO_H265_PICTURE_TYPE_B:
1393 slot_idx = enc_info->pReferenceSlots[0].slotIndex;
1394 pic_type = RENCODE_PICTURE_TYPE_B;
1395 break;
1396 case STD_VIDEO_H265_PICTURE_TYPE_I:
1397 case STD_VIDEO_H265_PICTURE_TYPE_IDR:
1398 default:
1399 pic_type = RENCODE_PICTURE_TYPE_I;
1400 break;
1401 }
1402 radv_enc_layer_select(cmd_buffer, h265_pic->TemporalId);
1403 } else {
1404 assert(0);
1405 return;
1406 }
1407
1408 ENC_BEGIN;
1409 radeon_emit(cs, pdev->vcn_enc_cmds.enc_params);
1410 radeon_emit(cs, pic_type); // pic type
1411 radeon_emit(cs, enc_info->dstBufferRange); // allowed max bitstream size
1412 radeon_emit(cs, luma_va >> 32);
1413 radeon_emit(cs, luma_va & 0xffffffff);
1414 radeon_emit(cs, chroma_va >> 32);
1415 radeon_emit(cs, chroma_va & 0xffffffff);
1416 radeon_emit(cs, src_img->planes[0].surface.u.gfx9.surf_pitch); // luma pitch
1417 radeon_emit(cs, src_img->planes[1].surface.u.gfx9.surf_pitch); // chroma pitch
1418 radeon_emit(cs, src_img->planes[0].surface.u.gfx9.swizzle_mode); // swizzle mode
1419 radeon_emit(cs, slot_idx); // ref0_idx
1420
1421 if (enc_info->pSetupReferenceSlot)
1422 radeon_emit(cs, enc_info->pSetupReferenceSlot->slotIndex); // reconstructed picture index
1423 else
1424 radeon_emit(cs, 0);
1425 ENC_END;
1426 }
1427
1428 static void
radv_enc_params_h264(struct radv_cmd_buffer * cmd_buffer)1429 radv_enc_params_h264(struct radv_cmd_buffer *cmd_buffer)
1430 {
1431 struct radv_device *device = radv_cmd_buffer_device(cmd_buffer);
1432 const struct radv_physical_device *pdev = radv_device_physical(device);
1433 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1434 ENC_BEGIN;
1435 radeon_emit(cs, pdev->vcn_enc_cmds.enc_params_h264);
1436
1437 if (pdev->enc_hw_ver < RADV_VIDEO_ENC_HW_3) {
1438 radeon_emit(cs, RENCODE_H264_PICTURE_STRUCTURE_FRAME);
1439 radeon_emit(cs, RENCODE_H264_INTERLACING_MODE_PROGRESSIVE);
1440 radeon_emit(cs, RENCODE_H264_PICTURE_STRUCTURE_FRAME);
1441 radeon_emit(cs, 0xffffffff); // reference_picture1_index
1442 } else {
1443 // V3
1444 radeon_emit(cs, RENCODE_H264_PICTURE_STRUCTURE_FRAME);
1445 radeon_emit(cs, 0); // input pic order cnt
1446 radeon_emit(cs, RENCODE_H264_INTERLACING_MODE_PROGRESSIVE);
1447 radeon_emit(cs, 0); // l0 ref pic0 pic_type
1448 radeon_emit(cs, 0); // l0 ref pic0 is long term
1449 radeon_emit(cs, 0); // l0 ref pic0 picture structure
1450 radeon_emit(cs, 0); // l0 ref pic0 pic order cnt
1451 radeon_emit(cs, 0xffffffff); // l0 ref pic1 index
1452 radeon_emit(cs, 0); // l0 ref pic1 pic_type
1453 radeon_emit(cs, 0); // l0 ref pic1 is long term
1454 radeon_emit(cs, 0); // l0 ref pic1 picture structure
1455 radeon_emit(cs, 0); // l0 ref pic1 pic order cnt
1456 radeon_emit(cs, 0xffffffff); // l1 ref pic0 index
1457 radeon_emit(cs, 0); // l1 ref pic0 pic_type
1458 radeon_emit(cs, 0); // l1 ref pic0 is long term
1459 radeon_emit(cs, 0); // l1 ref pic0 picture structure
1460 radeon_emit(cs, 0); // l1 ref pic0 pic order cnt
1461 }
1462 ENC_END;
1463 }
1464
1465 static void
radv_enc_op_init(struct radv_cmd_buffer * cmd_buffer)1466 radv_enc_op_init(struct radv_cmd_buffer *cmd_buffer)
1467 {
1468 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1469 ENC_BEGIN;
1470 radeon_emit(cs, RENCODE_IB_OP_INITIALIZE);
1471 ENC_END;
1472 }
1473
1474 static void
radv_enc_op_enc(struct radv_cmd_buffer * cmd_buffer)1475 radv_enc_op_enc(struct radv_cmd_buffer *cmd_buffer)
1476 {
1477 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1478 ENC_BEGIN;
1479 radeon_emit(cs, RENCODE_IB_OP_ENCODE);
1480 ENC_END;
1481 }
1482
1483 static void
radv_enc_op_init_rc(struct radv_cmd_buffer * cmd_buffer)1484 radv_enc_op_init_rc(struct radv_cmd_buffer *cmd_buffer)
1485 {
1486 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1487 ENC_BEGIN;
1488 radeon_emit(cs, RENCODE_IB_OP_INIT_RC);
1489 ENC_END;
1490 }
1491
1492 static void
radv_enc_op_init_rc_vbv(struct radv_cmd_buffer * cmd_buffer)1493 radv_enc_op_init_rc_vbv(struct radv_cmd_buffer *cmd_buffer)
1494 {
1495 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1496 ENC_BEGIN;
1497 radeon_emit(cs, RENCODE_IB_OP_INIT_RC_VBV_BUFFER_LEVEL);
1498 ENC_END;
1499 }
1500
1501 static void
radv_enc_op_preset(struct radv_cmd_buffer * cmd_buffer,const VkVideoEncodeInfoKHR * enc_info)1502 radv_enc_op_preset(struct radv_cmd_buffer *cmd_buffer, const VkVideoEncodeInfoKHR *enc_info)
1503 {
1504 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1505 struct radv_video_session *vid = cmd_buffer->video.vid;
1506 uint32_t preset_mode;
1507
1508 switch (vid->vk.op) {
1509 case VK_VIDEO_CODEC_OPERATION_ENCODE_H265_BIT_KHR: {
1510 const struct VkVideoEncodeH265PictureInfoKHR *h265_picture_info =
1511 vk_find_struct_const(enc_info->pNext, VIDEO_ENCODE_H265_PICTURE_INFO_KHR);
1512 const StdVideoEncodeH265PictureInfo *pic = h265_picture_info->pStdPictureInfo;
1513 const StdVideoH265SequenceParameterSet *sps =
1514 vk_video_find_h265_enc_std_sps(&cmd_buffer->video.params->vk, pic->pps_seq_parameter_set_id);
1515 if (sps->flags.sample_adaptive_offset_enabled_flag && vid->enc_preset_mode == RENCODE_PRESET_MODE_SPEED) {
1516 preset_mode = RENCODE_IB_OP_SET_BALANCE_ENCODING_MODE;
1517 return;
1518 }
1519 break;
1520 }
1521 default:
1522 break;
1523 }
1524
1525 if (vid->enc_preset_mode == RENCODE_PRESET_MODE_QUALITY)
1526 preset_mode = RENCODE_IB_OP_SET_QUALITY_ENCODING_MODE;
1527 else if (vid->enc_preset_mode == RENCODE_PRESET_MODE_BALANCE)
1528 preset_mode = RENCODE_IB_OP_SET_BALANCE_ENCODING_MODE;
1529 else
1530 preset_mode = RENCODE_IB_OP_SET_SPEED_ENCODING_MODE;
1531 ENC_BEGIN;
1532 radeon_emit(cs, preset_mode);
1533 ENC_END;
1534 }
1535
1536 static void
radv_enc_input_format(struct radv_cmd_buffer * cmd_buffer)1537 radv_enc_input_format(struct radv_cmd_buffer *cmd_buffer)
1538 {
1539 struct radv_device *device = radv_cmd_buffer_device(cmd_buffer);
1540 const struct radv_physical_device *pdev = radv_device_physical(device);
1541 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1542 struct radv_video_session *vid = cmd_buffer->video.vid;
1543 uint32_t color_bit_depth;
1544 uint32_t color_packing_format;
1545
1546 switch (vid->vk.picture_format) {
1547 case VK_FORMAT_G8_B8R8_2PLANE_420_UNORM:
1548 color_bit_depth = RENCODE_COLOR_BIT_DEPTH_8_BIT;
1549 color_packing_format = RENCODE_COLOR_PACKING_FORMAT_NV12;
1550 break;
1551 case VK_FORMAT_G10X6_B10X6R10X6_2PLANE_420_UNORM_3PACK16:
1552 color_bit_depth = RENCODE_COLOR_BIT_DEPTH_10_BIT;
1553 color_packing_format = RENCODE_COLOR_PACKING_FORMAT_P010;
1554 break;
1555 default:
1556 assert(0);
1557 return;
1558 }
1559
1560 ENC_BEGIN;
1561 radeon_emit(cs, pdev->vcn_enc_cmds.input_format);
1562 radeon_emit(cs, 0); // input color volume
1563 radeon_emit(cs, 0); // input color space
1564 radeon_emit(cs, RENCODE_COLOR_RANGE_STUDIO); // input color range
1565 radeon_emit(cs, 0); // input chroma subsampling
1566 radeon_emit(cs, 0); // input chroma location
1567 radeon_emit(cs, color_bit_depth); // input color bit depth
1568 radeon_emit(cs, color_packing_format); // input color packing format
1569 ENC_END;
1570 }
1571
1572 static void
radv_enc_output_format(struct radv_cmd_buffer * cmd_buffer)1573 radv_enc_output_format(struct radv_cmd_buffer *cmd_buffer)
1574 {
1575 struct radv_device *device = radv_cmd_buffer_device(cmd_buffer);
1576 const struct radv_physical_device *pdev = radv_device_physical(device);
1577 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1578 struct radv_video_session *vid = cmd_buffer->video.vid;
1579 uint32_t color_bit_depth;
1580
1581 switch (vid->vk.op) {
1582 case VK_VIDEO_CODEC_OPERATION_ENCODE_H264_BIT_KHR:
1583 color_bit_depth = RENCODE_COLOR_BIT_DEPTH_8_BIT;
1584 break;
1585 case VK_VIDEO_CODEC_OPERATION_ENCODE_H265_BIT_KHR:
1586 if (vid->vk.h265.profile_idc == STD_VIDEO_H265_PROFILE_IDC_MAIN_10)
1587 color_bit_depth = RENCODE_COLOR_BIT_DEPTH_10_BIT;
1588 else
1589 color_bit_depth = RENCODE_COLOR_BIT_DEPTH_8_BIT;
1590 break;
1591 default:
1592 assert(0);
1593 return;
1594 }
1595
1596 ENC_BEGIN;
1597 radeon_emit(cs, pdev->vcn_enc_cmds.output_format);
1598 radeon_emit(cs, 0); // output color volume
1599 radeon_emit(cs, RENCODE_COLOR_RANGE_STUDIO); // output color range
1600 radeon_emit(cs, 0); // output chroma location
1601 radeon_emit(cs, color_bit_depth); // output color bit depth
1602 ENC_END;
1603 }
1604
1605 static void
radv_enc_headers_h264(struct radv_cmd_buffer * cmd_buffer,const VkVideoEncodeInfoKHR * enc_info)1606 radv_enc_headers_h264(struct radv_cmd_buffer *cmd_buffer, const VkVideoEncodeInfoKHR *enc_info)
1607 {
1608 radv_enc_slice_header(cmd_buffer, enc_info);
1609 radv_enc_params(cmd_buffer, enc_info);
1610 radv_enc_params_h264(cmd_buffer);
1611 }
1612
1613 static void
radv_enc_headers_hevc(struct radv_cmd_buffer * cmd_buffer,const VkVideoEncodeInfoKHR * enc_info)1614 radv_enc_headers_hevc(struct radv_cmd_buffer *cmd_buffer, const VkVideoEncodeInfoKHR *enc_info)
1615 {
1616 radv_enc_slice_header_hevc(cmd_buffer, enc_info);
1617 radv_enc_params(cmd_buffer, enc_info);
1618 }
1619
1620 static void
begin(struct radv_cmd_buffer * cmd_buffer,const VkVideoEncodeInfoKHR * enc_info)1621 begin(struct radv_cmd_buffer *cmd_buffer, const VkVideoEncodeInfoKHR *enc_info)
1622 {
1623 struct radv_video_session *vid = cmd_buffer->video.vid;
1624
1625 radv_enc_op_init(cmd_buffer);
1626 radv_enc_session_init(cmd_buffer, enc_info);
1627 if (vid->vk.op == VK_VIDEO_CODEC_OPERATION_ENCODE_H264_BIT_KHR) {
1628 radv_enc_slice_control(cmd_buffer, enc_info);
1629 radv_enc_spec_misc_h264(cmd_buffer, enc_info);
1630 radv_enc_deblocking_filter_h264(cmd_buffer, enc_info);
1631 } else if (vid->vk.op == VK_VIDEO_CODEC_OPERATION_ENCODE_H265_BIT_KHR) {
1632 radv_enc_slice_control_hevc(cmd_buffer, enc_info);
1633 radv_enc_spec_misc_hevc(cmd_buffer, enc_info);
1634 radv_enc_deblocking_filter_hevc(cmd_buffer, enc_info);
1635 }
1636 radv_enc_layer_control(cmd_buffer, &vid->rc_layer_control);
1637 radv_enc_rc_session_init(cmd_buffer);
1638 radv_enc_quality_params(cmd_buffer);
1639 // temporal layers init
1640 unsigned i = 0;
1641 do {
1642 radv_enc_layer_select(cmd_buffer, i);
1643 radv_enc_rc_layer_init(cmd_buffer, &vid->rc_layer_init[i]);
1644 radv_enc_layer_select(cmd_buffer, i);
1645 radv_enc_rc_per_pic(cmd_buffer, enc_info, &vid->rc_per_pic[i]);
1646 } while (++i < vid->rc_layer_control.num_temporal_layers);
1647 radv_enc_op_init_rc(cmd_buffer);
1648 radv_enc_op_init_rc_vbv(cmd_buffer);
1649 }
1650
1651 static void
radv_vcn_encode_video(struct radv_cmd_buffer * cmd_buffer,const VkVideoEncodeInfoKHR * enc_info)1652 radv_vcn_encode_video(struct radv_cmd_buffer *cmd_buffer, const VkVideoEncodeInfoKHR *enc_info)
1653 {
1654 VK_FROM_HANDLE(radv_buffer, dst_buffer, enc_info->dstBuffer);
1655 struct radv_video_session *vid = cmd_buffer->video.vid;
1656 struct radv_device *device = radv_cmd_buffer_device(cmd_buffer);
1657 const struct radv_physical_device *pdev = radv_device_physical(device);
1658 struct radv_enc_state *enc = &cmd_buffer->video.enc;
1659 uint64_t feedback_query_va;
1660 switch (vid->vk.op) {
1661 case VK_VIDEO_CODEC_OPERATION_ENCODE_H264_BIT_KHR:
1662 case VK_VIDEO_CODEC_OPERATION_ENCODE_H265_BIT_KHR:
1663 break;
1664 default:
1665 assert(0);
1666 return;
1667 }
1668
1669 const struct VkVideoInlineQueryInfoKHR *inline_queries = NULL;
1670 if (vid->vk.flags & VK_VIDEO_SESSION_CREATE_INLINE_QUERIES_BIT_KHR) {
1671 inline_queries = vk_find_struct_const(enc_info->pNext, VIDEO_INLINE_QUERY_INFO_KHR);
1672
1673 if (inline_queries) {
1674 VK_FROM_HANDLE(radv_query_pool, pool, inline_queries->queryPool);
1675 feedback_query_va = radv_buffer_get_va(pool->bo);
1676 feedback_query_va += pool->stride * inline_queries->firstQuery;
1677 }
1678 }
1679
1680 if (!inline_queries)
1681 feedback_query_va = cmd_buffer->video.feedback_query_va;
1682
1683 // before encode
1684 // session info
1685 radv_enc_session_info(cmd_buffer);
1686
1687 cmd_buffer->video.enc.total_task_size = 0;
1688
1689 // task info
1690 radv_enc_task_info(cmd_buffer, true);
1691
1692 if (vid->enc_need_begin) {
1693 begin(cmd_buffer, enc_info);
1694 vid->enc_need_begin = false;
1695 } else {
1696 // temporal layers init
1697 unsigned i = 0;
1698 do {
1699 if (vid->enc_need_rate_control) {
1700 radv_enc_layer_select(cmd_buffer, i);
1701 radv_enc_rc_layer_init(cmd_buffer, &vid->rc_layer_init[i]);
1702 vid->enc_need_rate_control = false;
1703 }
1704 radv_enc_layer_select(cmd_buffer, i);
1705 radv_enc_rc_per_pic(cmd_buffer, enc_info, &vid->rc_per_pic[i]);
1706 } while (++i < vid->rc_layer_control.num_temporal_layers);
1707 }
1708
1709 // encode headers
1710 // ctx
1711 if (vid->vk.op == VK_VIDEO_CODEC_OPERATION_ENCODE_H264_BIT_KHR) {
1712 radv_enc_headers_h264(cmd_buffer, enc_info);
1713 radv_enc_ctx(cmd_buffer, enc_info);
1714 } else if (vid->vk.op == VK_VIDEO_CODEC_OPERATION_ENCODE_H265_BIT_KHR) {
1715 radv_enc_headers_hevc(cmd_buffer, enc_info);
1716 radv_enc_ctx(cmd_buffer, enc_info);
1717 }
1718 // bitstream
1719 radv_enc_bitstream(cmd_buffer, dst_buffer, enc_info->dstBufferOffset);
1720
1721 // feedback
1722 radv_enc_feedback(cmd_buffer, feedback_query_va);
1723
1724 // v2 encode statistics
1725 if (pdev->enc_hw_ver >= RADV_VIDEO_ENC_HW_2) {
1726 }
1727 // intra_refresh
1728 radv_enc_intra_refresh(cmd_buffer);
1729 // v2 input format
1730 if (pdev->enc_hw_ver >= RADV_VIDEO_ENC_HW_2) {
1731 radv_enc_input_format(cmd_buffer);
1732 radv_enc_output_format(cmd_buffer);
1733 }
1734 // v2 output format
1735
1736 // op_preset
1737 radv_enc_op_preset(cmd_buffer, enc_info);
1738 // op_enc
1739 radv_enc_op_enc(cmd_buffer);
1740
1741 radeon_emit_direct(cmd_buffer->cs, enc->task_size_offset, enc->total_task_size);
1742 }
1743
1744 static void
set_rate_control_defaults(struct radv_video_session * vid)1745 set_rate_control_defaults(struct radv_video_session *vid)
1746 {
1747 uint32_t frame_rate_den = 1, frame_rate_num = 30;
1748 vid->enc_rate_control_method = RENCODE_RATE_CONTROL_METHOD_NONE;
1749 vid->enc_vbv_buffer_level = 64;
1750 vid->rc_layer_control.num_temporal_layers = 1;
1751 vid->rc_layer_control.max_num_temporal_layers = 1;
1752 vid->rc_per_pic[0].qp_i = 26;
1753 vid->rc_per_pic[0].qp_p = 26;
1754 vid->rc_per_pic[0].qp_b = 26;
1755 vid->rc_per_pic[0].min_qp_i = 0;
1756 vid->rc_per_pic[0].max_qp_i = 51;
1757 vid->rc_per_pic[0].min_qp_p = 0;
1758 vid->rc_per_pic[0].max_qp_p = 51;
1759 vid->rc_per_pic[0].min_qp_b = 0;
1760 vid->rc_per_pic[0].max_qp_b = 51;
1761 vid->rc_per_pic[0].max_au_size_i = 0;
1762 vid->rc_per_pic[0].max_au_size_p = 0;
1763 vid->rc_per_pic[0].max_au_size_b = 0;
1764 vid->rc_per_pic[0].enabled_filler_data = 1;
1765 vid->rc_per_pic[0].skip_frame_enable = 0;
1766 vid->rc_per_pic[0].enforce_hrd = 1;
1767 vid->rc_layer_init[0].frame_rate_den = frame_rate_den;
1768 vid->rc_layer_init[0].frame_rate_num = frame_rate_num;
1769 vid->rc_layer_init[0].vbv_buffer_size = 20000000; // rate_control->virtualBufferSizeInMs;
1770 vid->rc_layer_init[0].target_bit_rate = 16000;
1771 vid->rc_layer_init[0].peak_bit_rate = 32000;
1772 vid->rc_layer_init[0].avg_target_bits_per_picture =
1773 radv_vcn_per_frame_integer(16000, frame_rate_den, frame_rate_num);
1774 vid->rc_layer_init[0].peak_bits_per_picture_integer =
1775 radv_vcn_per_frame_integer(32000, frame_rate_den, frame_rate_num);
1776 vid->rc_layer_init[0].peak_bits_per_picture_fractional =
1777 radv_vcn_per_frame_frac(32000, frame_rate_den, frame_rate_num);
1778 return;
1779 }
1780
1781 void
radv_video_enc_control_video_coding(struct radv_cmd_buffer * cmd_buffer,const VkVideoCodingControlInfoKHR * control_info)1782 radv_video_enc_control_video_coding(struct radv_cmd_buffer *cmd_buffer, const VkVideoCodingControlInfoKHR *control_info)
1783 {
1784 struct radv_video_session *vid = cmd_buffer->video.vid;
1785
1786 switch (vid->vk.op) {
1787 case VK_VIDEO_CODEC_OPERATION_ENCODE_H264_BIT_KHR:
1788 case VK_VIDEO_CODEC_OPERATION_ENCODE_H265_BIT_KHR:
1789 break;
1790 default:
1791 unreachable("Unsupported\n");
1792 }
1793
1794 if (control_info->flags & VK_VIDEO_CODING_CONTROL_RESET_BIT_KHR) {
1795 set_rate_control_defaults(vid);
1796 vid->enc_need_begin = true;
1797 }
1798
1799 if (control_info->flags & VK_VIDEO_CODING_CONTROL_ENCODE_RATE_CONTROL_BIT_KHR) {
1800 const VkVideoEncodeRateControlInfoKHR *rate_control = (VkVideoEncodeRateControlInfoKHR *)vk_find_struct_const(
1801 control_info->pNext, VIDEO_ENCODE_RATE_CONTROL_INFO_KHR);
1802
1803 assert(rate_control);
1804 const VkVideoEncodeH264RateControlInfoKHR *h264_rate_control =
1805 (VkVideoEncodeH264RateControlInfoKHR *)vk_find_struct_const(rate_control->pNext,
1806 VIDEO_ENCODE_H264_RATE_CONTROL_INFO_KHR);
1807 const VkVideoEncodeH265RateControlInfoKHR *h265_rate_control =
1808 (VkVideoEncodeH265RateControlInfoKHR *)vk_find_struct_const(rate_control->pNext,
1809 VIDEO_ENCODE_H265_RATE_CONTROL_INFO_KHR);
1810
1811 uint32_t rate_control_method = RENCODE_RATE_CONTROL_METHOD_NONE;
1812
1813 vid->enc_rate_control_default = false;
1814
1815 if (rate_control->rateControlMode == VK_VIDEO_ENCODE_RATE_CONTROL_MODE_DEFAULT_KHR) {
1816 vid->enc_rate_control_default = true;
1817 set_rate_control_defaults(vid);
1818 } else if (rate_control->rateControlMode == VK_VIDEO_ENCODE_RATE_CONTROL_MODE_CBR_BIT_KHR)
1819 rate_control_method = RENCODE_RATE_CONTROL_METHOD_CBR;
1820 else if (rate_control->rateControlMode == VK_VIDEO_ENCODE_RATE_CONTROL_MODE_VBR_BIT_KHR)
1821 rate_control_method = RENCODE_RATE_CONTROL_METHOD_PEAK_CONSTRAINED_VBR;
1822
1823 vid->enc_need_rate_control = true;
1824 if (vid->enc_rate_control_method != rate_control_method)
1825 vid->enc_need_begin = true;
1826
1827 vid->enc_rate_control_method = rate_control_method;
1828
1829 if (rate_control->rateControlMode == VK_VIDEO_ENCODE_RATE_CONTROL_MODE_DEFAULT_KHR)
1830 return;
1831
1832 if (h264_rate_control) {
1833 vid->rc_layer_control.max_num_temporal_layers = h264_rate_control->temporalLayerCount;
1834 vid->rc_layer_control.num_temporal_layers = h264_rate_control->temporalLayerCount;
1835 } else if (h265_rate_control) {
1836 vid->rc_layer_control.max_num_temporal_layers = h265_rate_control->subLayerCount;
1837 vid->rc_layer_control.num_temporal_layers = h265_rate_control->subLayerCount;
1838 }
1839
1840 for (unsigned l = 0; l < rate_control->layerCount; l++) {
1841 const VkVideoEncodeRateControlLayerInfoKHR *layer = &rate_control->pLayers[l];
1842 const VkVideoEncodeH264RateControlLayerInfoKHR *h264_layer =
1843 (VkVideoEncodeH264RateControlLayerInfoKHR *)vk_find_struct_const(
1844 layer->pNext, VIDEO_ENCODE_H264_RATE_CONTROL_LAYER_INFO_KHR);
1845 const VkVideoEncodeH265RateControlLayerInfoKHR *h265_layer =
1846 (VkVideoEncodeH265RateControlLayerInfoKHR *)vk_find_struct_const(
1847 layer->pNext, VIDEO_ENCODE_H265_RATE_CONTROL_LAYER_INFO_KHR);
1848 uint32_t frame_rate_den, frame_rate_num;
1849 vid->rc_layer_init[l].target_bit_rate = layer->averageBitrate;
1850 vid->rc_layer_init[l].peak_bit_rate = layer->maxBitrate;
1851 frame_rate_den = layer->frameRateDenominator;
1852 frame_rate_num = layer->frameRateNumerator;
1853 radv_vcn_enc_invalid_frame_rate(&frame_rate_den, &frame_rate_num);
1854 vid->rc_layer_init[l].frame_rate_den = frame_rate_den;
1855 vid->rc_layer_init[l].frame_rate_num = frame_rate_num;
1856 vid->rc_layer_init[l].vbv_buffer_size =
1857 (rate_control->virtualBufferSizeInMs / 1000.) * layer->averageBitrate;
1858 vid->rc_layer_init[l].avg_target_bits_per_picture =
1859 radv_vcn_per_frame_integer(layer->averageBitrate, frame_rate_den, frame_rate_num);
1860 vid->rc_layer_init[l].peak_bits_per_picture_integer =
1861 radv_vcn_per_frame_integer(layer->maxBitrate, frame_rate_den, frame_rate_num);
1862 vid->rc_layer_init[l].peak_bits_per_picture_fractional =
1863 radv_vcn_per_frame_frac(layer->maxBitrate, frame_rate_den, frame_rate_num);
1864
1865 if (h264_layer) {
1866 vid->rc_per_pic[l].min_qp_i = h264_layer->useMinQp ? h264_layer->minQp.qpI : 0;
1867 vid->rc_per_pic[l].min_qp_p = h264_layer->useMinQp ? h264_layer->minQp.qpP : 0;
1868 vid->rc_per_pic[l].min_qp_b = h264_layer->useMinQp ? h264_layer->minQp.qpB : 0;
1869 vid->rc_per_pic[l].max_qp_i = h264_layer->useMaxQp ? h264_layer->maxQp.qpI : 51;
1870 vid->rc_per_pic[l].max_qp_p = h264_layer->useMaxQp ? h264_layer->maxQp.qpP : 51;
1871 vid->rc_per_pic[l].max_qp_b = h264_layer->useMaxQp ? h264_layer->maxQp.qpB : 51;
1872 vid->rc_per_pic[l].max_au_size_i = h264_layer->useMaxFrameSize ? h264_layer->maxFrameSize.frameISize : 0;
1873 vid->rc_per_pic[l].max_au_size_p = h264_layer->useMaxFrameSize ? h264_layer->maxFrameSize.framePSize : 0;
1874 vid->rc_per_pic[l].max_au_size_b = h264_layer->useMaxFrameSize ? h264_layer->maxFrameSize.frameBSize : 0;
1875 } else if (h265_layer) {
1876 vid->rc_per_pic[l].min_qp_i = h265_layer->useMinQp ? h265_layer->minQp.qpI : 0;
1877 vid->rc_per_pic[l].min_qp_p = h265_layer->useMinQp ? h265_layer->minQp.qpP : 0;
1878 vid->rc_per_pic[l].min_qp_b = h265_layer->useMinQp ? h265_layer->minQp.qpB : 0;
1879 vid->rc_per_pic[l].max_qp_i = h265_layer->useMaxQp ? h265_layer->maxQp.qpI : 51;
1880 vid->rc_per_pic[l].max_qp_p = h265_layer->useMaxQp ? h265_layer->maxQp.qpP : 51;
1881 vid->rc_per_pic[l].max_qp_b = h265_layer->useMaxQp ? h265_layer->maxQp.qpB : 51;
1882 vid->rc_per_pic[l].max_au_size_i = h265_layer->useMaxFrameSize ? h265_layer->maxFrameSize.frameISize : 0;
1883 vid->rc_per_pic[l].max_au_size_p = h265_layer->useMaxFrameSize ? h265_layer->maxFrameSize.framePSize : 0;
1884 vid->rc_per_pic[l].max_au_size_b = h265_layer->useMaxFrameSize ? h265_layer->maxFrameSize.frameBSize : 0;
1885 }
1886
1887 vid->rc_per_pic[l].enabled_filler_data = 1;
1888 vid->rc_per_pic[l].skip_frame_enable = 0;
1889 vid->rc_per_pic[l].enforce_hrd = 1;
1890 }
1891
1892 if (rate_control->virtualBufferSizeInMs > 0)
1893 vid->enc_vbv_buffer_level =
1894 lroundf((float)rate_control->initialVirtualBufferSizeInMs / rate_control->virtualBufferSizeInMs * 64);
1895 }
1896 }
1897
1898 VKAPI_ATTR void VKAPI_CALL
radv_CmdEncodeVideoKHR(VkCommandBuffer commandBuffer,const VkVideoEncodeInfoKHR * pEncodeInfo)1899 radv_CmdEncodeVideoKHR(VkCommandBuffer commandBuffer, const VkVideoEncodeInfoKHR *pEncodeInfo)
1900 {
1901 VK_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1902 radv_vcn_encode_video(cmd_buffer, pEncodeInfo);
1903 }
1904
1905 VKAPI_ATTR VkResult VKAPI_CALL
radv_GetPhysicalDeviceVideoEncodeQualityLevelPropertiesKHR(VkPhysicalDevice physicalDevice,const VkPhysicalDeviceVideoEncodeQualityLevelInfoKHR * pQualityLevelInfo,VkVideoEncodeQualityLevelPropertiesKHR * pQualityLevelProperties)1906 radv_GetPhysicalDeviceVideoEncodeQualityLevelPropertiesKHR(
1907 VkPhysicalDevice physicalDevice, const VkPhysicalDeviceVideoEncodeQualityLevelInfoKHR *pQualityLevelInfo,
1908 VkVideoEncodeQualityLevelPropertiesKHR *pQualityLevelProperties)
1909 {
1910 return VK_SUCCESS;
1911 }
1912
1913 void
radv_video_patch_encode_session_parameters(struct vk_video_session_parameters * params)1914 radv_video_patch_encode_session_parameters(struct vk_video_session_parameters *params)
1915 {
1916 switch (params->op) {
1917 case VK_VIDEO_CODEC_OPERATION_ENCODE_H264_BIT_KHR:
1918 break;
1919 case VK_VIDEO_CODEC_OPERATION_ENCODE_H265_BIT_KHR: {
1920 /*
1921 * AMD firmware requires these flags to be set in h265 with RC modes,
1922 * VCN 3 need 1.27 and VCN 4 needs 1.7 or newer to pass the CTS tests,
1923 * dEQP-VK.video.encode.h265_rc_*.
1924 */
1925 for (unsigned i = 0; i < params->h265_enc.h265_pps_count; i++) {
1926 params->h265_enc.h265_pps[i].base.flags.cu_qp_delta_enabled_flag = 1;
1927 params->h265_enc.h265_pps[i].base.diff_cu_qp_delta_depth = 0;
1928 }
1929 break;
1930 }
1931 default:
1932 break;
1933 }
1934 }
1935
1936 VKAPI_ATTR VkResult VKAPI_CALL
radv_GetEncodedVideoSessionParametersKHR(VkDevice device,const VkVideoEncodeSessionParametersGetInfoKHR * pVideoSessionParametersInfo,VkVideoEncodeSessionParametersFeedbackInfoKHR * pFeedbackInfo,size_t * pDataSize,void * pData)1937 radv_GetEncodedVideoSessionParametersKHR(VkDevice device,
1938 const VkVideoEncodeSessionParametersGetInfoKHR *pVideoSessionParametersInfo,
1939 VkVideoEncodeSessionParametersFeedbackInfoKHR *pFeedbackInfo,
1940 size_t *pDataSize, void *pData)
1941 {
1942 VK_FROM_HANDLE(radv_video_session_params, templ, pVideoSessionParametersInfo->videoSessionParameters);
1943 size_t total_size = 0;
1944 size_t size_limit = 0;
1945
1946 if (pData)
1947 size_limit = *pDataSize;
1948
1949 switch (templ->vk.op) {
1950 case VK_VIDEO_CODEC_OPERATION_ENCODE_H264_BIT_KHR: {
1951 const struct VkVideoEncodeH264SessionParametersGetInfoKHR *h264_get_info =
1952 vk_find_struct_const(pVideoSessionParametersInfo->pNext, VIDEO_ENCODE_H264_SESSION_PARAMETERS_GET_INFO_KHR);
1953 size_t sps_size = 0, pps_size = 0;
1954 if (h264_get_info->writeStdSPS) {
1955 const StdVideoH264SequenceParameterSet *sps =
1956 vk_video_find_h264_enc_std_sps(&templ->vk, h264_get_info->stdSPSId);
1957 assert(sps);
1958 vk_video_encode_h264_sps(sps, size_limit, &sps_size, pData);
1959 }
1960 if (h264_get_info->writeStdPPS) {
1961 const StdVideoH264PictureParameterSet *pps =
1962 vk_video_find_h264_enc_std_pps(&templ->vk, h264_get_info->stdPPSId);
1963 assert(pps);
1964 char *data_ptr = pData ? (char *)pData + sps_size : NULL;
1965 vk_video_encode_h264_pps(pps, templ->vk.h264_enc.profile_idc == STD_VIDEO_H264_PROFILE_IDC_HIGH, size_limit,
1966 &pps_size, data_ptr);
1967 }
1968 total_size = sps_size + pps_size;
1969 break;
1970 }
1971 case VK_VIDEO_CODEC_OPERATION_ENCODE_H265_BIT_KHR: {
1972 const struct VkVideoEncodeH265SessionParametersGetInfoKHR *h265_get_info =
1973 vk_find_struct_const(pVideoSessionParametersInfo->pNext, VIDEO_ENCODE_H265_SESSION_PARAMETERS_GET_INFO_KHR);
1974 size_t sps_size = 0, pps_size = 0, vps_size = 0;
1975 if (h265_get_info->writeStdVPS) {
1976 const StdVideoH265VideoParameterSet *vps = vk_video_find_h265_enc_std_vps(&templ->vk, h265_get_info->stdVPSId);
1977 assert(vps);
1978 vk_video_encode_h265_vps(vps, size_limit, &vps_size, pData);
1979 }
1980 if (h265_get_info->writeStdSPS) {
1981 const StdVideoH265SequenceParameterSet *sps =
1982 vk_video_find_h265_enc_std_sps(&templ->vk, h265_get_info->stdSPSId);
1983 assert(sps);
1984 char *data_ptr = pData ? (char *)pData + vps_size : NULL;
1985 vk_video_encode_h265_sps(sps, size_limit, &sps_size, data_ptr);
1986 }
1987 if (h265_get_info->writeStdPPS) {
1988 const StdVideoH265PictureParameterSet *pps =
1989 vk_video_find_h265_enc_std_pps(&templ->vk, h265_get_info->stdPPSId);
1990 assert(pps);
1991 char *data_ptr = pData ? (char *)pData + vps_size + sps_size : NULL;
1992 vk_video_encode_h265_pps(pps, size_limit, &pps_size, data_ptr);
1993
1994 if (pFeedbackInfo) {
1995 struct VkVideoEncodeH265SessionParametersFeedbackInfoKHR *h265_feedback_info =
1996 vk_find_struct(pFeedbackInfo->pNext, VIDEO_ENCODE_H265_SESSION_PARAMETERS_FEEDBACK_INFO_KHR);
1997 pFeedbackInfo->hasOverrides = VK_TRUE;
1998 h265_feedback_info->hasStdPPSOverrides = VK_TRUE;
1999 }
2000 }
2001 total_size = sps_size + pps_size + vps_size;
2002 break;
2003 }
2004 default:
2005 break;
2006 }
2007
2008 *pDataSize = total_size;
2009 return VK_SUCCESS;
2010 }
2011
2012 void
radv_video_enc_begin_coding(struct radv_cmd_buffer * cmd_buffer)2013 radv_video_enc_begin_coding(struct radv_cmd_buffer *cmd_buffer)
2014 {
2015 struct radv_device *device = radv_cmd_buffer_device(cmd_buffer);
2016 const struct radv_physical_device *pdev = radv_device_physical(device);
2017 radeon_check_space(device->ws, cmd_buffer->cs, 1024);
2018
2019 if (pdev->enc_hw_ver >= RADV_VIDEO_ENC_HW_4)
2020 radv_vcn_sq_header(cmd_buffer->cs, &cmd_buffer->video.sq, RADEON_VCN_ENGINE_TYPE_ENCODE);
2021 }
2022
2023 void
radv_video_enc_end_coding(struct radv_cmd_buffer * cmd_buffer)2024 radv_video_enc_end_coding(struct radv_cmd_buffer *cmd_buffer)
2025 {
2026 struct radv_device *device = radv_cmd_buffer_device(cmd_buffer);
2027 const struct radv_physical_device *pdev = radv_device_physical(device);
2028 if (pdev->enc_hw_ver >= RADV_VIDEO_ENC_HW_4)
2029 radv_vcn_sq_tail(cmd_buffer->cs, &cmd_buffer->video.sq);
2030 }
2031
2032 #define VCN_ENC_SESSION_SIZE 128 * 1024
2033
2034 VkResult
radv_video_get_encode_session_memory_requirements(struct radv_device * device,struct radv_video_session * vid,uint32_t * pMemoryRequirementsCount,VkVideoSessionMemoryRequirementsKHR * pMemoryRequirements)2035 radv_video_get_encode_session_memory_requirements(struct radv_device *device, struct radv_video_session *vid,
2036 uint32_t *pMemoryRequirementsCount,
2037 VkVideoSessionMemoryRequirementsKHR *pMemoryRequirements)
2038 {
2039 struct radv_physical_device *pdev = radv_device_physical(device);
2040 uint32_t memory_type_bits = (1u << pdev->memory_properties.memoryTypeCount) - 1;
2041
2042 VK_OUTARRAY_MAKE_TYPED(VkVideoSessionMemoryRequirementsKHR, out, pMemoryRequirements, pMemoryRequirementsCount);
2043
2044 vk_outarray_append_typed(VkVideoSessionMemoryRequirementsKHR, &out, m)
2045 {
2046 m->memoryBindIndex = 0;
2047 m->memoryRequirements.size = VCN_ENC_SESSION_SIZE;
2048 m->memoryRequirements.alignment = 0;
2049 m->memoryRequirements.memoryTypeBits = memory_type_bits;
2050 }
2051
2052 return vk_outarray_status(&out);
2053 }
2054