1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * SPDX-License-Identifier: MIT
9 */
10
11 #include <stdio.h>
12 #include <stdlib.h>
13 #ifndef _WIN32
14 #include <sys/utsname.h>
15 #endif
16 #include <sys/stat.h>
17
18 #include "util/mesa-sha1.h"
19 #include "util/os_time.h"
20 #include "ac_debug.h"
21 #include "ac_descriptors.h"
22 #include "radv_buffer.h"
23 #include "radv_debug.h"
24 #include "radv_descriptor_set.h"
25 #include "radv_entrypoints.h"
26 #include "radv_pipeline_graphics.h"
27 #include "radv_pipeline_rt.h"
28 #include "radv_shader.h"
29 #include "sid.h"
30 #include "spirv/nir_spirv.h"
31
32 #define TMA_BO_SIZE 4096
33
34 #define COLOR_RESET "\033[0m"
35 #define COLOR_RED "\033[31m"
36 #define COLOR_GREEN "\033[1;32m"
37 #define COLOR_YELLOW "\033[1;33m"
38 #define COLOR_CYAN "\033[1;36m"
39
40 #define RADV_DUMP_DIR "radv_dumps"
41
42 bool
radv_init_trace(struct radv_device * device)43 radv_init_trace(struct radv_device *device)
44 {
45 struct radeon_winsys *ws = device->ws;
46 VkResult result;
47
48 result = radv_bo_create(
49 device, NULL, sizeof(struct radv_trace_data), 8, RADEON_DOMAIN_VRAM,
50 RADEON_FLAG_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING | RADEON_FLAG_ZERO_VRAM | RADEON_FLAG_VA_UNCACHED,
51 RADV_BO_PRIORITY_UPLOAD_BUFFER, 0, true, &device->trace_bo);
52 if (result != VK_SUCCESS)
53 return false;
54
55 result = ws->buffer_make_resident(ws, device->trace_bo, true);
56 if (result != VK_SUCCESS)
57 return false;
58
59 device->trace_data = radv_buffer_map(ws, device->trace_bo);
60 if (!device->trace_data)
61 return false;
62
63 return true;
64 }
65
66 void
radv_finish_trace(struct radv_device * device)67 radv_finish_trace(struct radv_device *device)
68 {
69 struct radeon_winsys *ws = device->ws;
70
71 if (unlikely(device->trace_bo)) {
72 ws->buffer_make_resident(ws, device->trace_bo, false);
73 radv_bo_destroy(device, NULL, device->trace_bo);
74 }
75 }
76
77 static void
radv_dump_trace(const struct radv_device * device,struct radeon_cmdbuf * cs,FILE * f)78 radv_dump_trace(const struct radv_device *device, struct radeon_cmdbuf *cs, FILE *f)
79 {
80 fprintf(f, "Trace ID: %x\n", device->trace_data->primary_id);
81 device->ws->cs_dump(cs, f, (const int *)&device->trace_data->primary_id, 2, RADV_CS_DUMP_TYPE_IBS);
82 }
83
84 static void
radv_dump_mmapped_reg(const struct radv_device * device,FILE * f,unsigned offset)85 radv_dump_mmapped_reg(const struct radv_device *device, FILE *f, unsigned offset)
86 {
87 const struct radv_physical_device *pdev = radv_device_physical(device);
88 struct radeon_winsys *ws = device->ws;
89 uint32_t value;
90
91 if (ws->read_registers(ws, offset, 1, &value))
92 ac_dump_reg(f, pdev->info.gfx_level, pdev->info.family, offset, value, ~0);
93 }
94
95 static void
radv_dump_debug_registers(const struct radv_device * device,FILE * f)96 radv_dump_debug_registers(const struct radv_device *device, FILE *f)
97 {
98 const struct radv_physical_device *pdev = radv_device_physical(device);
99 const struct radeon_info *gpu_info = &pdev->info;
100
101 fprintf(f, "Memory-mapped registers:\n");
102 radv_dump_mmapped_reg(device, f, R_008010_GRBM_STATUS);
103
104 radv_dump_mmapped_reg(device, f, R_008008_GRBM_STATUS2);
105 radv_dump_mmapped_reg(device, f, R_008014_GRBM_STATUS_SE0);
106 radv_dump_mmapped_reg(device, f, R_008018_GRBM_STATUS_SE1);
107 radv_dump_mmapped_reg(device, f, R_008038_GRBM_STATUS_SE2);
108 radv_dump_mmapped_reg(device, f, R_00803C_GRBM_STATUS_SE3);
109 radv_dump_mmapped_reg(device, f, R_00D034_SDMA0_STATUS_REG);
110 radv_dump_mmapped_reg(device, f, R_00D834_SDMA1_STATUS_REG);
111 if (gpu_info->gfx_level <= GFX8) {
112 radv_dump_mmapped_reg(device, f, R_000E50_SRBM_STATUS);
113 radv_dump_mmapped_reg(device, f, R_000E4C_SRBM_STATUS2);
114 radv_dump_mmapped_reg(device, f, R_000E54_SRBM_STATUS3);
115 }
116 radv_dump_mmapped_reg(device, f, R_008680_CP_STAT);
117 radv_dump_mmapped_reg(device, f, R_008674_CP_STALLED_STAT1);
118 radv_dump_mmapped_reg(device, f, R_008678_CP_STALLED_STAT2);
119 radv_dump_mmapped_reg(device, f, R_008670_CP_STALLED_STAT3);
120 radv_dump_mmapped_reg(device, f, R_008210_CP_CPC_STATUS);
121 radv_dump_mmapped_reg(device, f, R_008214_CP_CPC_BUSY_STAT);
122 radv_dump_mmapped_reg(device, f, R_008218_CP_CPC_STALLED_STAT1);
123 radv_dump_mmapped_reg(device, f, R_00821C_CP_CPF_STATUS);
124 radv_dump_mmapped_reg(device, f, R_008220_CP_CPF_BUSY_STAT);
125 radv_dump_mmapped_reg(device, f, R_008224_CP_CPF_STALLED_STAT1);
126 fprintf(f, "\n");
127 }
128
129 static void
radv_dump_buffer_descriptor(enum amd_gfx_level gfx_level,enum radeon_family family,const uint32_t * desc,FILE * f)130 radv_dump_buffer_descriptor(enum amd_gfx_level gfx_level, enum radeon_family family, const uint32_t *desc, FILE *f)
131 {
132 fprintf(f, COLOR_CYAN "Buffer:" COLOR_RESET "\n");
133 for (unsigned j = 0; j < 4; j++)
134 ac_dump_reg(f, gfx_level, family, R_008F00_SQ_BUF_RSRC_WORD0 + j * 4, desc[j], 0xffffffff);
135 }
136
137 static void
radv_dump_image_descriptor(enum amd_gfx_level gfx_level,enum radeon_family family,const uint32_t * desc,FILE * f)138 radv_dump_image_descriptor(enum amd_gfx_level gfx_level, enum radeon_family family, const uint32_t *desc, FILE *f)
139 {
140 unsigned sq_img_rsrc_word0 = gfx_level >= GFX10 ? R_00A000_SQ_IMG_RSRC_WORD0 : R_008F10_SQ_IMG_RSRC_WORD0;
141
142 fprintf(f, COLOR_CYAN "Image:" COLOR_RESET "\n");
143 for (unsigned j = 0; j < 8; j++)
144 ac_dump_reg(f, gfx_level, family, sq_img_rsrc_word0 + j * 4, desc[j], 0xffffffff);
145
146 fprintf(f, COLOR_CYAN " FMASK:" COLOR_RESET "\n");
147 for (unsigned j = 0; j < 8; j++)
148 ac_dump_reg(f, gfx_level, family, sq_img_rsrc_word0 + j * 4, desc[8 + j], 0xffffffff);
149 }
150
151 static void
radv_dump_sampler_descriptor(enum amd_gfx_level gfx_level,enum radeon_family family,const uint32_t * desc,FILE * f)152 radv_dump_sampler_descriptor(enum amd_gfx_level gfx_level, enum radeon_family family, const uint32_t *desc, FILE *f)
153 {
154 fprintf(f, COLOR_CYAN "Sampler state:" COLOR_RESET "\n");
155 for (unsigned j = 0; j < 4; j++) {
156 ac_dump_reg(f, gfx_level, family, R_008F30_SQ_IMG_SAMP_WORD0 + j * 4, desc[j], 0xffffffff);
157 }
158 }
159
160 static void
radv_dump_combined_image_sampler_descriptor(enum amd_gfx_level gfx_level,enum radeon_family family,const uint32_t * desc,FILE * f)161 radv_dump_combined_image_sampler_descriptor(enum amd_gfx_level gfx_level, enum radeon_family family,
162 const uint32_t *desc, FILE *f)
163 {
164 radv_dump_image_descriptor(gfx_level, family, desc, f);
165 radv_dump_sampler_descriptor(gfx_level, family, desc + 16, f);
166 }
167
168 static void
radv_dump_descriptor_set(const struct radv_device * device,const struct radv_descriptor_set * set,unsigned id,FILE * f)169 radv_dump_descriptor_set(const struct radv_device *device, const struct radv_descriptor_set *set, unsigned id, FILE *f)
170 {
171 const struct radv_physical_device *pdev = radv_device_physical(device);
172 enum amd_gfx_level gfx_level = pdev->info.gfx_level;
173 enum radeon_family family = pdev->info.family;
174 const struct radv_descriptor_set_layout *layout;
175 int i;
176
177 if (!set)
178 return;
179 layout = set->header.layout;
180
181 for (i = 0; i < set->header.layout->binding_count; i++) {
182 uint32_t *desc = set->header.mapped_ptr + layout->binding[i].offset / 4;
183
184 fprintf(f, "(set=%u binding=%u offset=0x%x) ", id, i, layout->binding[i].offset);
185
186 switch (layout->binding[i].type) {
187 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER:
188 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER:
189 case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER:
190 case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER:
191 radv_dump_buffer_descriptor(gfx_level, family, desc, f);
192 break;
193 case VK_DESCRIPTOR_TYPE_STORAGE_IMAGE:
194 case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE:
195 case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT:
196 radv_dump_image_descriptor(gfx_level, family, desc, f);
197 break;
198 case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER:
199 radv_dump_combined_image_sampler_descriptor(gfx_level, family, desc, f);
200 break;
201 case VK_DESCRIPTOR_TYPE_SAMPLER:
202 radv_dump_sampler_descriptor(gfx_level, family, desc, f);
203 break;
204 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC:
205 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC:
206 case VK_DESCRIPTOR_TYPE_MUTABLE_EXT:
207 case VK_DESCRIPTOR_TYPE_ACCELERATION_STRUCTURE_KHR:
208 /* todo */
209 break;
210 default:
211 assert(!"unknown descriptor type");
212 break;
213 }
214 fprintf(f, "\n");
215 }
216 fprintf(f, "\n\n");
217 }
218
219 static void
radv_dump_descriptors(struct radv_device * device,FILE * f)220 radv_dump_descriptors(struct radv_device *device, FILE *f)
221 {
222 int i;
223
224 fprintf(f, "Descriptors:\n");
225 for (i = 0; i < MAX_SETS; i++) {
226 struct radv_descriptor_set *set = (struct radv_descriptor_set *)(uintptr_t)device->trace_data->descriptor_sets[i];
227
228 radv_dump_descriptor_set(device, set, i, f);
229 }
230 }
231
232 struct radv_shader_inst {
233 char text[160]; /* one disasm line */
234 unsigned offset; /* instruction offset */
235 unsigned size; /* instruction size >= 4 */
236 };
237
238 /* Split a disassembly string into lines and add them to the array pointed
239 * to by "instructions". */
240 static void
radv_add_split_disasm(const char * disasm,uint64_t start_addr,unsigned * num,struct radv_shader_inst * instructions)241 radv_add_split_disasm(const char *disasm, uint64_t start_addr, unsigned *num, struct radv_shader_inst *instructions)
242 {
243 struct radv_shader_inst *last_inst = *num ? &instructions[*num - 1] : NULL;
244 char *next;
245 char *repeat = strstr(disasm, "then repeated");
246
247 while ((next = strchr(disasm, '\n'))) {
248 struct radv_shader_inst *inst = &instructions[*num];
249 unsigned len = next - disasm;
250
251 if (repeat >= disasm && repeat < next) {
252 uint32_t repeat_count;
253 sscanf(repeat, "then repeated %u times", &repeat_count);
254
255 for (uint32_t i = 0; i < repeat_count; i++) {
256 inst = &instructions[*num];
257 memcpy(inst, last_inst, sizeof(struct radv_shader_inst));
258 inst->offset = last_inst->offset + last_inst->size * (i + 1);
259 (*num)++;
260 }
261
262 last_inst = inst;
263
264 disasm = next + 1;
265 repeat = strstr(disasm, "then repeated");
266 continue;
267 }
268
269 if (!memchr(disasm, ';', len)) {
270 /* Ignore everything that is not an instruction. */
271 disasm = next + 1;
272 continue;
273 }
274
275 assert(len < ARRAY_SIZE(inst->text));
276 memcpy(inst->text, disasm, len);
277 inst->text[len] = 0;
278 inst->offset = last_inst ? last_inst->offset + last_inst->size : 0;
279
280 const char *semicolon = strchr(disasm, ';');
281 assert(semicolon);
282 /* 9 = 8 hex digits + a leading space */
283 inst->size = (next - semicolon) / 9 * 4;
284
285 snprintf(inst->text + len, ARRAY_SIZE(inst->text) - len, " [PC=0x%" PRIx64 ", off=%u, size=%u]",
286 start_addr + inst->offset, inst->offset, inst->size);
287
288 last_inst = inst;
289 (*num)++;
290 disasm = next + 1;
291 }
292 }
293
294 static void
radv_dump_annotated_shader(const struct radv_shader * shader,gl_shader_stage stage,struct ac_wave_info * waves,unsigned num_waves,FILE * f)295 radv_dump_annotated_shader(const struct radv_shader *shader, gl_shader_stage stage, struct ac_wave_info *waves,
296 unsigned num_waves, FILE *f)
297 {
298 uint64_t start_addr, end_addr;
299 unsigned i;
300
301 if (!shader)
302 return;
303
304 start_addr = radv_shader_get_va(shader) & ((1ull << 48) - 1);
305 end_addr = start_addr + shader->code_size;
306
307 /* See if any wave executes the shader. */
308 for (i = 0; i < num_waves; i++) {
309 if (start_addr <= waves[i].pc && waves[i].pc <= end_addr)
310 break;
311 }
312
313 if (i == num_waves)
314 return; /* the shader is not being executed */
315
316 /* Remember the first found wave. The waves are sorted according to PC. */
317 waves = &waves[i];
318 num_waves -= i;
319
320 /* Get the list of instructions.
321 * Buffer size / 4 is the upper bound of the instruction count.
322 */
323 unsigned num_inst = 0;
324 struct radv_shader_inst *instructions = calloc(shader->code_size / 4, sizeof(struct radv_shader_inst));
325
326 radv_add_split_disasm(shader->disasm_string, start_addr, &num_inst, instructions);
327
328 fprintf(f, COLOR_YELLOW "%s - annotated disassembly:" COLOR_RESET "\n", radv_get_shader_name(&shader->info, stage));
329
330 /* Print instructions with annotations. */
331 for (i = 0; i < num_inst; i++) {
332 struct radv_shader_inst *inst = &instructions[i];
333
334 fprintf(f, "%s\n", inst->text);
335
336 /* Print which waves execute the instruction right now. */
337 while (num_waves && start_addr + inst->offset == waves->pc) {
338 fprintf(f,
339 " " COLOR_GREEN "^ SE%u SH%u CU%u "
340 "SIMD%u WAVE%u EXEC=%016" PRIx64 " ",
341 waves->se, waves->sh, waves->cu, waves->simd, waves->wave, waves->exec);
342
343 if (inst->size == 4) {
344 fprintf(f, "INST32=%08X" COLOR_RESET "\n", waves->inst_dw0);
345 } else {
346 fprintf(f, "INST64=%08X %08X" COLOR_RESET "\n", waves->inst_dw0, waves->inst_dw1);
347 }
348
349 waves->matched = true;
350 waves = &waves[1];
351 num_waves--;
352 }
353 }
354
355 fprintf(f, "\n\n");
356 free(instructions);
357 }
358
359 static void
radv_dump_spirv(const struct radv_shader * shader,const char * sha1,const char * dump_dir)360 radv_dump_spirv(const struct radv_shader *shader, const char *sha1, const char *dump_dir)
361 {
362 char dump_path[512];
363 FILE *f;
364
365 snprintf(dump_path, sizeof(dump_path), "%s/%s.spv", dump_dir, sha1);
366
367 f = fopen(dump_path, "w+");
368 if (f) {
369 fwrite(shader->spirv, shader->spirv_size, 1, f);
370 fclose(f);
371 }
372 }
373
374 static void
radv_dump_shader(struct radv_device * device,struct radv_pipeline * pipeline,struct radv_shader * shader,gl_shader_stage stage,const char * dump_dir,FILE * f)375 radv_dump_shader(struct radv_device *device, struct radv_pipeline *pipeline, struct radv_shader *shader,
376 gl_shader_stage stage, const char *dump_dir, FILE *f)
377 {
378 const struct radv_physical_device *pdev = radv_device_physical(device);
379
380 if (!shader)
381 return;
382
383 fprintf(f, "%s:\n\n", radv_get_shader_name(&shader->info, stage));
384
385 if (shader->spirv) {
386 unsigned char sha1[21];
387 char sha1buf[41];
388
389 _mesa_sha1_compute(shader->spirv, shader->spirv_size, sha1);
390 _mesa_sha1_format(sha1buf, sha1);
391
392 if (device->vk.enabled_features.deviceFaultVendorBinary) {
393 spirv_print_asm(f, (const uint32_t *)shader->spirv, shader->spirv_size / 4);
394 } else {
395 fprintf(f, "SPIRV (see %s.spv)\n\n", sha1buf);
396 radv_dump_spirv(shader, sha1buf, dump_dir);
397 }
398 }
399
400 if (shader->nir_string) {
401 fprintf(f, "NIR:\n%s\n", shader->nir_string);
402 }
403
404 fprintf(f, "%s IR:\n%s\n", pdev->use_llvm ? "LLVM" : "ACO", shader->ir_string);
405 fprintf(f, "DISASM:\n%s\n", shader->disasm_string);
406
407 radv_dump_shader_stats(device, pipeline, shader, stage, f);
408 }
409
410 static void
radv_dump_vertex_descriptors(const struct radv_device * device,const struct radv_graphics_pipeline * pipeline,FILE * f)411 radv_dump_vertex_descriptors(const struct radv_device *device, const struct radv_graphics_pipeline *pipeline, FILE *f)
412 {
413 struct radv_shader *vs = radv_get_shader(pipeline->base.shaders, MESA_SHADER_VERTEX);
414 uint32_t count = util_bitcount(vs->info.vs.vb_desc_usage_mask);
415 uint32_t *vb_ptr = (uint32_t *)(uintptr_t)device->trace_data->vertex_descriptors;
416
417 if (!count)
418 return;
419
420 fprintf(f, "Num vertex %s: %d\n", vs->info.vs.use_per_attribute_vb_descs ? "attributes" : "bindings", count);
421 for (uint32_t i = 0; i < count; i++) {
422 uint32_t *desc = &((uint32_t *)vb_ptr)[i * 4];
423 uint64_t va = 0;
424
425 va |= desc[0];
426 va |= (uint64_t)G_008F04_BASE_ADDRESS_HI(desc[1]) << 32;
427
428 fprintf(f, "VBO#%d:\n", i);
429 fprintf(f, "\tVA: 0x%" PRIx64 "\n", va);
430 fprintf(f, "\tStride: %d\n", G_008F04_STRIDE(desc[1]));
431 fprintf(f, "\tNum records: %d (0x%x)\n", desc[2], desc[2]);
432 }
433 }
434
435 static void
radv_dump_vs_prolog(const struct radv_device * device,const struct radv_graphics_pipeline * pipeline,FILE * f)436 radv_dump_vs_prolog(const struct radv_device *device, const struct radv_graphics_pipeline *pipeline, FILE *f)
437 {
438 struct radv_shader_part *vs_prolog = (struct radv_shader_part *)(uintptr_t)device->trace_data->vertex_prolog;
439 struct radv_shader *vs_shader = radv_get_shader(pipeline->base.shaders, MESA_SHADER_VERTEX);
440
441 if (!vs_prolog || !vs_shader || !vs_shader->info.vs.has_prolog)
442 return;
443
444 fprintf(f, "Vertex prolog:\n\n");
445 fprintf(f, "DISASM:\n%s\n", vs_prolog->disasm_string);
446 }
447
448 static struct radv_pipeline *
radv_get_saved_pipeline(struct radv_device * device,enum amd_ip_type ring)449 radv_get_saved_pipeline(struct radv_device *device, enum amd_ip_type ring)
450 {
451 if (ring == AMD_IP_GFX)
452 return (struct radv_pipeline *)(uintptr_t)device->trace_data->gfx_ring_pipeline;
453 else
454 return (struct radv_pipeline *)(uintptr_t)device->trace_data->comp_ring_pipeline;
455 }
456
457 static void
radv_dump_queue_state(struct radv_queue * queue,const char * dump_dir,const char * wave_dump,FILE * f)458 radv_dump_queue_state(struct radv_queue *queue, const char *dump_dir, const char *wave_dump, FILE *f)
459 {
460 struct radv_device *device = radv_queue_device(queue);
461 const struct radv_physical_device *pdev = radv_device_physical(device);
462 enum amd_ip_type ring = radv_queue_ring(queue);
463 struct radv_pipeline *pipeline;
464
465 fprintf(f, "AMD_IP_%s:\n", ac_get_ip_type_string(&pdev->info, ring));
466
467 pipeline = radv_get_saved_pipeline(device, ring);
468 if (pipeline) {
469 fprintf(f, "Pipeline hash: %" PRIx64 "\n", pipeline->pipeline_hash);
470
471 if (pipeline->type == RADV_PIPELINE_GRAPHICS) {
472 struct radv_graphics_pipeline *graphics_pipeline = radv_pipeline_to_graphics(pipeline);
473
474 radv_dump_vs_prolog(device, graphics_pipeline, f);
475
476 /* Dump active graphics shaders. */
477 unsigned stages = graphics_pipeline->active_stages;
478 while (stages) {
479 int stage = u_bit_scan(&stages);
480
481 radv_dump_shader(device, &graphics_pipeline->base, graphics_pipeline->base.shaders[stage], stage, dump_dir,
482 f);
483 }
484 } else if (pipeline->type == RADV_PIPELINE_RAY_TRACING) {
485 struct radv_ray_tracing_pipeline *rt_pipeline = radv_pipeline_to_ray_tracing(pipeline);
486 for (unsigned i = 0; i < rt_pipeline->stage_count; i++) {
487 struct radv_shader *shader = rt_pipeline->stages[i].shader;
488 if (shader)
489 radv_dump_shader(device, pipeline, shader, shader->info.stage, dump_dir, f);
490 }
491 radv_dump_shader(device, pipeline, pipeline->shaders[MESA_SHADER_INTERSECTION], MESA_SHADER_INTERSECTION,
492 dump_dir, f);
493 } else {
494 struct radv_compute_pipeline *compute_pipeline = radv_pipeline_to_compute(pipeline);
495
496 radv_dump_shader(device, &compute_pipeline->base, compute_pipeline->base.shaders[MESA_SHADER_COMPUTE],
497 MESA_SHADER_COMPUTE, dump_dir, f);
498 }
499
500 if (wave_dump) {
501 struct ac_wave_info waves[AC_MAX_WAVES_PER_CHIP];
502 enum amd_gfx_level gfx_level = pdev->info.gfx_level;
503 unsigned num_waves = ac_get_wave_info(gfx_level, &pdev->info, wave_dump, waves);
504
505 fprintf(f, COLOR_CYAN "The number of active waves = %u" COLOR_RESET "\n\n", num_waves);
506
507 if (pipeline->type == RADV_PIPELINE_GRAPHICS) {
508 struct radv_graphics_pipeline *graphics_pipeline = radv_pipeline_to_graphics(pipeline);
509
510 /* Dump annotated active graphics shaders. */
511 unsigned stages = graphics_pipeline->active_stages;
512 while (stages) {
513 int stage = u_bit_scan(&stages);
514
515 radv_dump_annotated_shader(graphics_pipeline->base.shaders[stage], stage, waves, num_waves, f);
516 }
517 } else if (pipeline->type == RADV_PIPELINE_RAY_TRACING) {
518 struct radv_ray_tracing_pipeline *rt_pipeline = radv_pipeline_to_ray_tracing(pipeline);
519 for (unsigned i = 0; i < rt_pipeline->stage_count; i++) {
520 struct radv_shader *shader = rt_pipeline->stages[i].shader;
521 if (shader)
522 radv_dump_annotated_shader(shader, shader->info.stage, waves, num_waves, f);
523 }
524 radv_dump_annotated_shader(pipeline->shaders[MESA_SHADER_INTERSECTION], MESA_SHADER_INTERSECTION, waves,
525 num_waves, f);
526 } else {
527 struct radv_compute_pipeline *compute_pipeline = radv_pipeline_to_compute(pipeline);
528
529 radv_dump_annotated_shader(compute_pipeline->base.shaders[MESA_SHADER_COMPUTE], MESA_SHADER_COMPUTE, waves,
530 num_waves, f);
531 }
532
533 /* Print waves executing shaders that are not currently bound. */
534 unsigned i;
535 bool found = false;
536 for (i = 0; i < num_waves; i++) {
537 if (waves[i].matched)
538 continue;
539
540 if (!found) {
541 fprintf(f, COLOR_CYAN "Waves not executing currently-bound shaders:" COLOR_RESET "\n");
542 found = true;
543 }
544
545 struct radv_shader *shader = radv_find_shader(device, waves[0].pc);
546 if (shader) {
547 radv_dump_annotated_shader(shader, shader->info.stage, waves, num_waves, f);
548 if (waves[i].matched)
549 continue;
550 }
551
552 fprintf(f, " SE%u SH%u CU%u SIMD%u WAVE%u EXEC=%016" PRIx64 " INST=%08X %08X PC=%" PRIx64 "\n",
553 waves[i].se, waves[i].sh, waves[i].cu, waves[i].simd, waves[i].wave, waves[i].exec,
554 waves[i].inst_dw0, waves[i].inst_dw1, waves[i].pc);
555 }
556 if (found)
557 fprintf(f, "\n\n");
558 }
559
560 VkDispatchIndirectCommand dispatch_indirect = device->trace_data->indirect_dispatch;
561 if (dispatch_indirect.x || dispatch_indirect.y || dispatch_indirect.z)
562 fprintf(f, "VkDispatchIndirectCommand: x=%u y=%u z=%u\n\n\n", dispatch_indirect.x, dispatch_indirect.y,
563 dispatch_indirect.z);
564
565 if (pipeline->type == RADV_PIPELINE_GRAPHICS) {
566 struct radv_graphics_pipeline *graphics_pipeline = radv_pipeline_to_graphics(pipeline);
567 radv_dump_vertex_descriptors(device, graphics_pipeline, f);
568 }
569 radv_dump_descriptors(device, f);
570 }
571 }
572
573 static void
radv_dump_cmd(const char * cmd,FILE * f)574 radv_dump_cmd(const char *cmd, FILE *f)
575 {
576 #ifndef _WIN32
577 char line[2048];
578 FILE *p;
579
580 p = popen(cmd, "r");
581 if (p) {
582 while (fgets(line, sizeof(line), p))
583 fputs(line, f);
584 fprintf(f, "\n");
585 pclose(p);
586 }
587 #endif
588 }
589
590 static void
radv_dump_dmesg(FILE * f)591 radv_dump_dmesg(FILE *f)
592 {
593 fprintf(f, "\nLast 60 lines of dmesg:\n\n");
594 radv_dump_cmd("dmesg | tail -n60", f);
595 }
596
597 void
radv_dump_enabled_options(const struct radv_device * device,FILE * f)598 radv_dump_enabled_options(const struct radv_device *device, FILE *f)
599 {
600 const struct radv_physical_device *pdev = radv_device_physical(device);
601 const struct radv_instance *instance = radv_physical_device_instance(pdev);
602 uint64_t mask;
603
604 if (instance->debug_flags) {
605 fprintf(f, "Enabled debug options: ");
606
607 mask = instance->debug_flags;
608 while (mask) {
609 int i = u_bit_scan64(&mask);
610 fprintf(f, "%s, ", radv_get_debug_option_name(i));
611 }
612 fprintf(f, "\n");
613 }
614
615 if (instance->perftest_flags) {
616 fprintf(f, "Enabled perftest options: ");
617
618 mask = instance->perftest_flags;
619 while (mask) {
620 int i = u_bit_scan64(&mask);
621 fprintf(f, "%s, ", radv_get_perftest_option_name(i));
622 }
623 fprintf(f, "\n");
624 }
625 }
626
627 static void
radv_dump_app_info(const struct radv_device * device,FILE * f)628 radv_dump_app_info(const struct radv_device *device, FILE *f)
629 {
630 const struct radv_physical_device *pdev = radv_device_physical(device);
631 const struct radv_instance *instance = radv_physical_device_instance(pdev);
632
633 fprintf(f, "Application name: %s\n", instance->vk.app_info.app_name);
634 fprintf(f, "Application version: %d\n", instance->vk.app_info.app_version);
635 fprintf(f, "Engine name: %s\n", instance->vk.app_info.engine_name);
636 fprintf(f, "Engine version: %d\n", instance->vk.app_info.engine_version);
637 fprintf(f, "API version: %d.%d.%d\n", VK_VERSION_MAJOR(instance->vk.app_info.api_version),
638 VK_VERSION_MINOR(instance->vk.app_info.api_version), VK_VERSION_PATCH(instance->vk.app_info.api_version));
639
640 radv_dump_enabled_options(device, f);
641 }
642
643 static void
radv_dump_device_name(const struct radv_device * device,FILE * f)644 radv_dump_device_name(const struct radv_device *device, FILE *f)
645 {
646 const struct radv_physical_device *pdev = radv_device_physical(device);
647 const struct radeon_info *gpu_info = &pdev->info;
648 #ifndef _WIN32
649 char kernel_version[128] = {0};
650 struct utsname uname_data;
651 #endif
652
653 #ifdef _WIN32
654 fprintf(f, "Device name: %s (DRM %i.%i.%i)\n\n", pdev->marketing_name, gpu_info->drm_major, gpu_info->drm_minor,
655 gpu_info->drm_patchlevel);
656 #else
657 if (uname(&uname_data) == 0)
658 snprintf(kernel_version, sizeof(kernel_version), " / %s", uname_data.release);
659
660 fprintf(f, "Device name: %s (DRM %i.%i.%i%s)\n\n", pdev->marketing_name, gpu_info->drm_major, gpu_info->drm_minor,
661 gpu_info->drm_patchlevel, kernel_version);
662 #endif
663 }
664
665 static void
radv_dump_umr_ring(const struct radv_queue * queue,FILE * f)666 radv_dump_umr_ring(const struct radv_queue *queue, FILE *f)
667 {
668 #ifndef _WIN32
669 const struct radv_device *device = radv_queue_device(queue);
670 const struct radv_physical_device *pdev = radv_device_physical(device);
671 const enum amd_ip_type ring = radv_queue_ring(queue);
672 char cmd[256];
673
674 /* TODO: Dump compute ring. */
675 if (ring != AMD_IP_GFX)
676 return;
677
678 sprintf(cmd, "umr --by-pci %04x:%02x:%02x.%01x -RS %s 2>&1", pdev->bus_info.domain, pdev->bus_info.bus,
679 pdev->bus_info.dev, pdev->bus_info.func, pdev->info.gfx_level >= GFX10 ? "gfx_0.0.0" : "gfx");
680 fprintf(f, "\nUMR GFX ring:\n\n");
681 radv_dump_cmd(cmd, f);
682 #endif
683 }
684
685 static void
radv_dump_umr_waves(struct radv_queue * queue,const char * wave_dump,FILE * f)686 radv_dump_umr_waves(struct radv_queue *queue, const char *wave_dump, FILE *f)
687 {
688 fprintf(f, "\nUMR GFX waves:\n\n%s", wave_dump ? wave_dump : "");
689 }
690
691 static bool
radv_gpu_hang_occurred(struct radv_queue * queue,enum amd_ip_type ring)692 radv_gpu_hang_occurred(struct radv_queue *queue, enum amd_ip_type ring)
693 {
694 const struct radv_device *device = radv_queue_device(queue);
695 struct radeon_winsys *ws = device->ws;
696
697 if (!ws->ctx_wait_idle(queue->hw_ctx, ring, queue->vk.index_in_family))
698 return true;
699
700 return false;
701 }
702
703 bool
radv_vm_fault_occurred(struct radv_device * device,struct radv_winsys_gpuvm_fault_info * fault_info)704 radv_vm_fault_occurred(struct radv_device *device, struct radv_winsys_gpuvm_fault_info *fault_info)
705 {
706 const struct radv_physical_device *pdev = radv_device_physical(device);
707
708 if (!pdev->info.has_gpuvm_fault_query)
709 return false;
710
711 return device->ws->query_gpuvm_fault(device->ws, fault_info);
712 }
713
714 enum radv_device_fault_chunk {
715 RADV_DEVICE_FAULT_CHUNK_TRACE,
716 RADV_DEVICE_FAULT_CHUNK_QUEUE_STATE,
717 RADV_DEVICE_FAULT_CHUNK_UMR_WAVES,
718 RADV_DEVICE_FAULT_CHUNK_UMR_RING,
719 RADV_DEVICE_FAULT_CHUNK_REGISTERS,
720 RADV_DEVICE_FAULT_CHUNK_BO_RANGES,
721 RADV_DEVICE_FAULT_CHUNK_BO_HISTORY,
722 RADV_DEVICE_FAULT_CHUNK_VM_FAULT,
723 RADV_DEVICE_FAULT_CHUNK_APP_INFO,
724 RADV_DEVICE_FAULT_CHUNK_GPU_INFO,
725 RADV_DEVICE_FAULT_CHUNK_DMESG,
726 RADV_DEVICE_FAULT_CHUNK_COUNT,
727 };
728
729 VkResult
radv_check_gpu_hangs(struct radv_queue * queue,const struct radv_winsys_submit_info * submit_info)730 radv_check_gpu_hangs(struct radv_queue *queue, const struct radv_winsys_submit_info *submit_info)
731 {
732 enum amd_ip_type ring;
733
734 ring = radv_queue_ring(queue);
735
736 bool hang_occurred = radv_gpu_hang_occurred(queue, ring);
737 if (!hang_occurred)
738 return VK_SUCCESS;
739
740 fprintf(stderr, "radv: GPU hang detected...\n");
741
742 #ifndef _WIN32
743 struct radv_device *device = radv_queue_device(queue);
744 const struct radv_physical_device *pdev = radv_device_physical(device);
745 const struct radv_instance *instance = radv_physical_device_instance(pdev);
746 const bool save_hang_report = !device->vk.enabled_features.deviceFaultVendorBinary;
747 struct radv_winsys_gpuvm_fault_info fault_info = {0};
748
749 /* Query if a VM fault happened for this GPU hang. */
750 bool vm_fault_occurred = radv_vm_fault_occurred(device, &fault_info);
751
752 /* Create a directory into $HOME/radv_dumps_<pid>_<time> to save
753 * various debugging info about that GPU hang.
754 */
755 struct tm *timep, result;
756 time_t raw_time;
757 FILE *f;
758 char dump_dir[256], dump_path[512], buf_time[128];
759
760 if (save_hang_report) {
761 time(&raw_time);
762 timep = os_localtime(&raw_time, &result);
763 strftime(buf_time, sizeof(buf_time), "%Y.%m.%d_%H.%M.%S", timep);
764
765 snprintf(dump_dir, sizeof(dump_dir), "%s/" RADV_DUMP_DIR "_%d_%s", debug_get_option("HOME", "."), getpid(),
766 buf_time);
767 if (mkdir(dump_dir, 0774) && errno != EEXIST) {
768 fprintf(stderr, "radv: can't create directory '%s' (%i).\n", dump_dir, errno);
769 abort();
770 }
771
772 fprintf(stderr, "radv: GPU hang report will be saved to '%s'!\n", dump_dir);
773 }
774
775 struct {
776 const char *name;
777 char *ptr;
778 size_t size;
779 } chunks[RADV_DEVICE_FAULT_CHUNK_COUNT] = {
780 {"trace"}, {"pipeline"}, {"umr_waves"}, {"umr_ring"}, {"registers"}, {"bo_ranges"},
781 {"bo_history"}, {"vm_fault"}, {"app_info"}, {"gpu_info"}, {"dmesg"},
782 };
783
784 char *wave_dump = NULL;
785 if (!(instance->debug_flags & RADV_DEBUG_NO_UMR))
786 wave_dump = ac_get_umr_waves(&pdev->info, radv_queue_ring(queue));
787
788 for (uint32_t i = 0; i < RADV_DEVICE_FAULT_CHUNK_COUNT; i++) {
789
790 if (save_hang_report) {
791 snprintf(dump_path, sizeof(dump_path), "%s/%s.log", dump_dir, chunks[i].name);
792
793 f = fopen(dump_path, "w+");
794 } else {
795 f = open_memstream(&chunks[i].ptr, &chunks[i].size);
796 }
797
798 if (!f)
799 continue;
800
801 switch (i) {
802 case RADV_DEVICE_FAULT_CHUNK_TRACE:
803 radv_dump_trace(device, submit_info->cs_array[0], f);
804 break;
805 case RADV_DEVICE_FAULT_CHUNK_QUEUE_STATE:
806 radv_dump_queue_state(queue, dump_dir, wave_dump, f);
807 break;
808 case RADV_DEVICE_FAULT_CHUNK_UMR_WAVES:
809 if (!(instance->debug_flags & RADV_DEBUG_NO_UMR))
810 radv_dump_umr_waves(queue, wave_dump, f);
811 break;
812 case RADV_DEVICE_FAULT_CHUNK_UMR_RING:
813 if (!(instance->debug_flags & RADV_DEBUG_NO_UMR))
814 radv_dump_umr_ring(queue, f);
815 break;
816 case RADV_DEVICE_FAULT_CHUNK_REGISTERS:
817 radv_dump_debug_registers(device, f);
818 break;
819 case RADV_DEVICE_FAULT_CHUNK_BO_RANGES:
820 device->ws->dump_bo_ranges(device->ws, f);
821 break;
822 case RADV_DEVICE_FAULT_CHUNK_BO_HISTORY:
823 device->ws->dump_bo_log(device->ws, f);
824 break;
825 case RADV_DEVICE_FAULT_CHUNK_VM_FAULT:
826 if (vm_fault_occurred) {
827 fprintf(f, "VM fault report.\n\n");
828 fprintf(f, "Failing VM page: 0x%08" PRIx64 "\n", fault_info.addr);
829 ac_print_gpuvm_fault_status(f, pdev->info.gfx_level, fault_info.status);
830 }
831 break;
832 case RADV_DEVICE_FAULT_CHUNK_APP_INFO:
833 radv_dump_app_info(device, f);
834 break;
835 case RADV_DEVICE_FAULT_CHUNK_GPU_INFO:
836 radv_dump_device_name(device, f);
837 ac_print_gpu_info(&pdev->info, f);
838 break;
839 case RADV_DEVICE_FAULT_CHUNK_DMESG:
840 radv_dump_dmesg(f);
841 break;
842 default:
843 break;
844 }
845
846 fclose(f);
847 }
848
849 free(wave_dump);
850
851 if (save_hang_report) {
852 fprintf(stderr, "radv: GPU hang report saved successfully!\n");
853 abort();
854 } else {
855 char *report;
856
857 report = ralloc_strdup(NULL, "========== RADV GPU hang report ==========\n");
858 for (uint32_t i = 0; i < RADV_DEVICE_FAULT_CHUNK_COUNT; i++) {
859 if (!chunks[i].size)
860 continue;
861
862 ralloc_asprintf_append(&report, "\n========== %s ==========\n", chunks[i].name);
863 ralloc_asprintf_append(&report, "%s", chunks[i].ptr);
864
865 free(chunks[i].ptr);
866 }
867
868 device->gpu_hang_report = report;
869 }
870
871 #endif
872 return VK_ERROR_DEVICE_LOST;
873 }
874
875 bool
radv_trap_handler_init(struct radv_device * device)876 radv_trap_handler_init(struct radv_device *device)
877 {
878 const struct radv_physical_device *pdev = radv_device_physical(device);
879 struct radeon_winsys *ws = device->ws;
880 VkResult result;
881
882 /* Create the trap handler shader and upload it like other shaders. */
883 device->trap_handler_shader = radv_create_trap_handler_shader(device);
884 if (!device->trap_handler_shader) {
885 fprintf(stderr, "radv: failed to create the trap handler shader.\n");
886 return false;
887 }
888
889 result = ws->buffer_make_resident(ws, device->trap_handler_shader->bo, true);
890 if (result != VK_SUCCESS)
891 return false;
892
893 result = radv_bo_create(
894 device, NULL, TMA_BO_SIZE, 256, RADEON_DOMAIN_VRAM,
895 RADEON_FLAG_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING | RADEON_FLAG_ZERO_VRAM | RADEON_FLAG_32BIT,
896 RADV_BO_PRIORITY_SCRATCH, 0, true, &device->tma_bo);
897 if (result != VK_SUCCESS)
898 return false;
899
900 result = ws->buffer_make_resident(ws, device->tma_bo, true);
901 if (result != VK_SUCCESS)
902 return false;
903
904 device->tma_ptr = radv_buffer_map(ws, device->tma_bo);
905 if (!device->tma_ptr)
906 return false;
907
908 /* Upload a buffer descriptor to store various info from the trap. */
909 uint64_t tma_va = radv_buffer_get_va(device->tma_bo) + 16;
910 uint32_t desc[4];
911
912 ac_build_raw_buffer_descriptor(pdev->info.gfx_level, tma_va, TMA_BO_SIZE, desc);
913
914 memcpy(device->tma_ptr, desc, sizeof(desc));
915
916 return true;
917 }
918
919 void
radv_trap_handler_finish(struct radv_device * device)920 radv_trap_handler_finish(struct radv_device *device)
921 {
922 struct radeon_winsys *ws = device->ws;
923
924 if (unlikely(device->trap_handler_shader)) {
925 ws->buffer_make_resident(ws, device->trap_handler_shader->bo, false);
926 radv_shader_unref(device, device->trap_handler_shader);
927 }
928
929 if (unlikely(device->tma_bo)) {
930 ws->buffer_make_resident(ws, device->tma_bo, false);
931 radv_bo_destroy(device, NULL, device->tma_bo);
932 }
933 }
934
935 static void
radv_dump_faulty_shader(struct radv_device * device,uint64_t faulty_pc)936 radv_dump_faulty_shader(struct radv_device *device, uint64_t faulty_pc)
937 {
938 struct radv_shader *shader;
939 uint64_t start_addr, end_addr;
940 uint32_t instr_offset;
941
942 shader = radv_find_shader(device, faulty_pc);
943 if (!shader)
944 return;
945
946 start_addr = radv_shader_get_va(shader);
947 end_addr = start_addr + shader->code_size;
948 instr_offset = faulty_pc - start_addr;
949
950 fprintf(stderr,
951 "Faulty shader found "
952 "VA=[0x%" PRIx64 "-0x%" PRIx64 "], instr_offset=%d\n",
953 start_addr, end_addr, instr_offset);
954
955 /* Get the list of instructions.
956 * Buffer size / 4 is the upper bound of the instruction count.
957 */
958 unsigned num_inst = 0;
959 struct radv_shader_inst *instructions = calloc(shader->code_size / 4, sizeof(struct radv_shader_inst));
960
961 /* Split the disassembly string into instructions. */
962 radv_add_split_disasm(shader->disasm_string, start_addr, &num_inst, instructions);
963
964 /* Print instructions with annotations. */
965 for (unsigned i = 0; i < num_inst; i++) {
966 struct radv_shader_inst *inst = &instructions[i];
967
968 if (start_addr + inst->offset == faulty_pc) {
969 fprintf(stderr, "\n!!! Faulty instruction below !!!\n");
970 fprintf(stderr, "%s\n", inst->text);
971 fprintf(stderr, "\n");
972 } else {
973 fprintf(stderr, "%s\n", inst->text);
974 }
975 }
976
977 free(instructions);
978 }
979
980 struct radv_sq_hw_reg {
981 uint32_t status;
982 uint32_t trap_sts;
983 uint32_t hw_id;
984 uint32_t ib_sts;
985 };
986
987 static void
radv_dump_sq_hw_regs(struct radv_device * device)988 radv_dump_sq_hw_regs(struct radv_device *device)
989 {
990 const struct radv_physical_device *pdev = radv_device_physical(device);
991 enum amd_gfx_level gfx_level = pdev->info.gfx_level;
992 enum radeon_family family = pdev->info.family;
993 struct radv_sq_hw_reg *regs = (struct radv_sq_hw_reg *)&device->tma_ptr[6];
994
995 fprintf(stderr, "\nHardware registers:\n");
996 if (pdev->info.gfx_level >= GFX10) {
997 ac_dump_reg(stderr, gfx_level, family, R_000408_SQ_WAVE_STATUS, regs->status, ~0);
998 ac_dump_reg(stderr, gfx_level, family, R_00040C_SQ_WAVE_TRAPSTS, regs->trap_sts, ~0);
999 ac_dump_reg(stderr, gfx_level, family, R_00045C_SQ_WAVE_HW_ID1, regs->hw_id, ~0);
1000 ac_dump_reg(stderr, gfx_level, family, R_00041C_SQ_WAVE_IB_STS, regs->ib_sts, ~0);
1001 } else {
1002 ac_dump_reg(stderr, gfx_level, family, R_000048_SQ_WAVE_STATUS, regs->status, ~0);
1003 ac_dump_reg(stderr, gfx_level, family, R_00004C_SQ_WAVE_TRAPSTS, regs->trap_sts, ~0);
1004 ac_dump_reg(stderr, gfx_level, family, R_000050_SQ_WAVE_HW_ID, regs->hw_id, ~0);
1005 ac_dump_reg(stderr, gfx_level, family, R_00005C_SQ_WAVE_IB_STS, regs->ib_sts, ~0);
1006 }
1007 fprintf(stderr, "\n\n");
1008 }
1009
1010 void
radv_check_trap_handler(struct radv_queue * queue)1011 radv_check_trap_handler(struct radv_queue *queue)
1012 {
1013 enum amd_ip_type ring = radv_queue_ring(queue);
1014 struct radv_device *device = radv_queue_device(queue);
1015 struct radeon_winsys *ws = device->ws;
1016
1017 /* Wait for the context to be idle in a finite time. */
1018 ws->ctx_wait_idle(queue->hw_ctx, ring, queue->vk.index_in_family);
1019
1020 /* Try to detect if the trap handler has been reached by the hw by
1021 * looking at ttmp0 which should be non-zero if a shader exception
1022 * happened.
1023 */
1024 if (!device->tma_ptr[4])
1025 return;
1026
1027 #if 0
1028 fprintf(stderr, "tma_ptr:\n");
1029 for (unsigned i = 0; i < 10; i++)
1030 fprintf(stderr, "tma_ptr[%d]=0x%x\n", i, device->tma_ptr[i]);
1031 #endif
1032
1033 radv_dump_sq_hw_regs(device);
1034
1035 uint32_t ttmp0 = device->tma_ptr[4];
1036 uint32_t ttmp1 = device->tma_ptr[5];
1037
1038 /* According to the ISA docs, 3.10 Trap and Exception Registers:
1039 *
1040 * "{ttmp1, ttmp0} = {3'h0, pc_rewind[3:0], HT[0], trapID[7:0], PC[47:0]}"
1041 *
1042 * "When the trap handler is entered, the PC of the faulting
1043 * instruction is: (PC - PC_rewind * 4)."
1044 * */
1045 uint8_t trap_id = (ttmp1 >> 16) & 0xff;
1046 uint8_t ht = (ttmp1 >> 24) & 0x1;
1047 uint8_t pc_rewind = (ttmp1 >> 25) & 0xf;
1048 uint64_t pc = (ttmp0 | ((ttmp1 & 0x0000ffffull) << 32)) - (pc_rewind * 4);
1049
1050 fprintf(stderr, "PC=0x%" PRIx64 ", trapID=%d, HT=%d, PC_rewind=%d\n", pc, trap_id, ht, pc_rewind);
1051
1052 radv_dump_faulty_shader(device, pc);
1053
1054 abort();
1055 }
1056
1057 /* VK_EXT_device_fault */
1058 VKAPI_ATTR VkResult VKAPI_CALL
radv_GetDeviceFaultInfoEXT(VkDevice _device,VkDeviceFaultCountsEXT * pFaultCounts,VkDeviceFaultInfoEXT * pFaultInfo)1059 radv_GetDeviceFaultInfoEXT(VkDevice _device, VkDeviceFaultCountsEXT *pFaultCounts, VkDeviceFaultInfoEXT *pFaultInfo)
1060 {
1061 VK_OUTARRAY_MAKE_TYPED(VkDeviceFaultAddressInfoEXT, out, pFaultInfo ? pFaultInfo->pAddressInfos : NULL,
1062 &pFaultCounts->addressInfoCount);
1063 struct radv_winsys_gpuvm_fault_info fault_info = {0};
1064 VK_FROM_HANDLE(radv_device, device, _device);
1065 const struct radv_physical_device *pdev = radv_device_physical(device);
1066 const struct radv_instance *instance = radv_physical_device_instance(pdev);
1067 bool vm_fault_occurred = false;
1068
1069 /* Query if a GPUVM fault happened. */
1070 vm_fault_occurred = radv_vm_fault_occurred(device, &fault_info);
1071
1072 /* No vendor-specific crash dumps yet. */
1073 pFaultCounts->vendorInfoCount = 0;
1074 pFaultCounts->vendorBinarySize = 0;
1075
1076 if (device->gpu_hang_report) {
1077 VkDeviceFaultVendorBinaryHeaderVersionOneEXT hdr;
1078
1079 hdr.headerSize = sizeof(VkDeviceFaultVendorBinaryHeaderVersionOneEXT);
1080 hdr.headerVersion = VK_DEVICE_FAULT_VENDOR_BINARY_HEADER_VERSION_ONE_EXT;
1081 hdr.vendorID = pdev->vk.properties.vendorID;
1082 hdr.deviceID = pdev->vk.properties.deviceID;
1083 hdr.driverVersion = pdev->vk.properties.driverVersion;
1084 memcpy(hdr.pipelineCacheUUID, pdev->cache_uuid, VK_UUID_SIZE);
1085 hdr.applicationNameOffset = 0;
1086 hdr.applicationVersion = instance->vk.app_info.app_version;
1087 hdr.engineNameOffset = 0;
1088 hdr.engineVersion = instance->vk.app_info.engine_version;
1089 hdr.apiVersion = instance->vk.app_info.api_version;
1090
1091 pFaultCounts->vendorBinarySize = sizeof(hdr) + strlen(device->gpu_hang_report);
1092 if (pFaultInfo) {
1093 memcpy(pFaultInfo->pVendorBinaryData, &hdr, sizeof(hdr));
1094 memcpy((char *)pFaultInfo->pVendorBinaryData + sizeof(hdr), device->gpu_hang_report,
1095 strlen(device->gpu_hang_report));
1096 }
1097 }
1098
1099 if (vm_fault_occurred) {
1100 VkDeviceFaultAddressInfoEXT addr_fault_info = {
1101 .reportedAddress = ((int64_t)fault_info.addr << 16) >> 16,
1102 .addressPrecision = 4096, /* 4K page granularity */
1103 };
1104
1105 if (pFaultInfo)
1106 strncpy(pFaultInfo->description, "A GPUVM fault has been detected", sizeof(pFaultInfo->description));
1107
1108 if (pdev->info.gfx_level >= GFX10) {
1109 addr_fault_info.addressType = G_00A130_RW(fault_info.status) ? VK_DEVICE_FAULT_ADDRESS_TYPE_WRITE_INVALID_EXT
1110 : VK_DEVICE_FAULT_ADDRESS_TYPE_READ_INVALID_EXT;
1111 } else {
1112 /* Not sure how to get the access status on GFX6-9. */
1113 addr_fault_info.addressType = VK_DEVICE_FAULT_ADDRESS_TYPE_NONE_EXT;
1114 }
1115 vk_outarray_append_typed(VkDeviceFaultAddressInfoEXT, &out, elem) *elem = addr_fault_info;
1116 }
1117
1118 return vk_outarray_status(&out);
1119 }
1120