1 /************************************************************************** 2 * 3 * Copyright 2011 Advanced Micro Devices, Inc. 4 * 5 * SPDX-License-Identifier: MIT 6 * 7 **************************************************************************/ 8 9 #ifndef AC_UVD_DEC_H 10 #define AC_UVD_DEC_H 11 12 13 /* UVD uses PM4 packet type 0 and 2 */ 14 #define RUVD_PKT_TYPE_S(x) (((unsigned)(x)&0x3) << 30) 15 #define RUVD_PKT_TYPE_G(x) (((x) >> 30) & 0x3) 16 #define RUVD_PKT_TYPE_C 0x3FFFFFFF 17 #define RUVD_PKT_COUNT_S(x) (((unsigned)(x)&0x3FFF) << 16) 18 #define RUVD_PKT_COUNT_G(x) (((x) >> 16) & 0x3FFF) 19 #define RUVD_PKT_COUNT_C 0xC000FFFF 20 #define RUVD_PKT0_BASE_INDEX_S(x) (((unsigned)(x)&0xFFFF) << 0) 21 #define RUVD_PKT0_BASE_INDEX_G(x) (((x) >> 0) & 0xFFFF) 22 #define RUVD_PKT0_BASE_INDEX_C 0xFFFF0000 23 #define RUVD_PKT0(index, count) \ 24 (RUVD_PKT_TYPE_S(0) | RUVD_PKT0_BASE_INDEX_S(index) | RUVD_PKT_COUNT_S(count)) 25 #define RUVD_PKT2() (RUVD_PKT_TYPE_S(2)) 26 27 /* registers involved with UVD */ 28 #define RUVD_GPCOM_VCPU_CMD 0xEF0C 29 #define RUVD_GPCOM_VCPU_DATA0 0xEF10 30 #define RUVD_GPCOM_VCPU_DATA1 0xEF14 31 #define RUVD_ENGINE_CNTL 0xEF18 32 33 #define RUVD_GPCOM_VCPU_CMD_SOC15 0x2070c 34 #define RUVD_GPCOM_VCPU_DATA0_SOC15 0x20710 35 #define RUVD_GPCOM_VCPU_DATA1_SOC15 0x20714 36 #define RUVD_ENGINE_CNTL_SOC15 0x20718 37 38 /* UVD commands to VCPU */ 39 #define RUVD_CMD_MSG_BUFFER 0x00000000 40 #define RUVD_CMD_DPB_BUFFER 0x00000001 41 #define RUVD_CMD_DECODING_TARGET_BUFFER 0x00000002 42 #define RUVD_CMD_FEEDBACK_BUFFER 0x00000003 43 #define RUVD_CMD_SESSION_CONTEXT_BUFFER 0x00000005 44 #define RUVD_CMD_BITSTREAM_BUFFER 0x00000100 45 #define RUVD_CMD_ITSCALING_TABLE_BUFFER 0x00000204 46 #define RUVD_CMD_CONTEXT_BUFFER 0x00000206 47 48 /* UVD message types */ 49 #define RUVD_MSG_CREATE 0 50 #define RUVD_MSG_DECODE 1 51 #define RUVD_MSG_DESTROY 2 52 53 /* UVD stream types */ 54 #define RUVD_CODEC_H264 0x00000000 55 #define RUVD_CODEC_VC1 0x00000001 56 #define RUVD_CODEC_MPEG2 0x00000003 57 #define RUVD_CODEC_MPEG4 0x00000004 58 #define RUVD_CODEC_H264_PERF 0x00000007 59 #define RUVD_CODEC_MJPEG 0x00000008 60 #define RUVD_CODEC_H265 0x00000010 61 62 /* UVD decode target buffer tiling mode */ 63 #define RUVD_TILE_LINEAR 0x00000000 64 #define RUVD_TILE_8X4 0x00000001 65 #define RUVD_TILE_8X8 0x00000002 66 #define RUVD_TILE_32AS8 0x00000003 67 68 /* UVD decode target buffer array mode */ 69 #define RUVD_ARRAY_MODE_LINEAR 0x00000000 70 #define RUVD_ARRAY_MODE_MACRO_LINEAR_MICRO_TILED 0x00000001 71 #define RUVD_ARRAY_MODE_1D_THIN 0x00000002 72 #define RUVD_ARRAY_MODE_2D_THIN 0x00000004 73 #define RUVD_ARRAY_MODE_MACRO_TILED_MICRO_LINEAR 0x00000004 74 #define RUVD_ARRAY_MODE_MACRO_TILED_MICRO_TILED 0x00000005 75 76 /* UVD tile config */ 77 #define RUVD_BANK_WIDTH(x) ((x) << 0) 78 #define RUVD_BANK_HEIGHT(x) ((x) << 3) 79 #define RUVD_MACRO_TILE_ASPECT_RATIO(x) ((x) << 6) 80 #define RUVD_NUM_BANKS(x) ((x) << 9) 81 82 /* H.264 profile definitions */ 83 #define RUVD_H264_PROFILE_BASELINE 0x00000000 84 #define RUVD_H264_PROFILE_MAIN 0x00000001 85 #define RUVD_H264_PROFILE_HIGH 0x00000002 86 #define RUVD_H264_PROFILE_STEREO_HIGH 0x00000003 87 #define RUVD_H264_PROFILE_MVC 0x00000004 88 89 /* VC-1 profile definitions */ 90 #define RUVD_VC1_PROFILE_SIMPLE 0x00000000 91 #define RUVD_VC1_PROFILE_MAIN 0x00000001 92 #define RUVD_VC1_PROFILE_ADVANCED 0x00000002 93 94 enum ruvd_surface_type 95 { 96 RUVD_SURFACE_TYPE_LEGACY = 0, 97 RUVD_SURFACE_TYPE_GFX9 98 }; 99 100 struct ruvd_mvc_element { 101 uint16_t viewOrderIndex; 102 uint16_t viewId; 103 uint16_t numOfAnchorRefsInL0; 104 uint16_t viewIdOfAnchorRefsInL0[15]; 105 uint16_t numOfAnchorRefsInL1; 106 uint16_t viewIdOfAnchorRefsInL1[15]; 107 uint16_t numOfNonAnchorRefsInL0; 108 uint16_t viewIdOfNonAnchorRefsInL0[15]; 109 uint16_t numOfNonAnchorRefsInL1; 110 uint16_t viewIdOfNonAnchorRefsInL1[15]; 111 }; 112 113 struct ruvd_h264 { 114 uint32_t profile; 115 uint32_t level; 116 117 uint32_t sps_info_flags; 118 uint32_t pps_info_flags; 119 uint8_t chroma_format; 120 uint8_t bit_depth_luma_minus8; 121 uint8_t bit_depth_chroma_minus8; 122 uint8_t log2_max_frame_num_minus4; 123 124 uint8_t pic_order_cnt_type; 125 uint8_t log2_max_pic_order_cnt_lsb_minus4; 126 uint8_t num_ref_frames; 127 uint8_t reserved_8bit; 128 129 int8_t pic_init_qp_minus26; 130 int8_t pic_init_qs_minus26; 131 int8_t chroma_qp_index_offset; 132 int8_t second_chroma_qp_index_offset; 133 134 uint8_t num_slice_groups_minus1; 135 uint8_t slice_group_map_type; 136 uint8_t num_ref_idx_l0_active_minus1; 137 uint8_t num_ref_idx_l1_active_minus1; 138 139 uint16_t slice_group_change_rate_minus1; 140 uint16_t reserved_16bit_1; 141 142 uint8_t scaling_list_4x4[6][16]; 143 uint8_t scaling_list_8x8[2][64]; 144 145 uint32_t frame_num; 146 uint32_t frame_num_list[16]; 147 int32_t curr_field_order_cnt_list[2]; 148 int32_t field_order_cnt_list[16][2]; 149 150 uint32_t decoded_pic_idx; 151 152 uint32_t curr_pic_ref_frame_num; 153 154 uint8_t ref_frame_list[16]; 155 156 uint32_t reserved[122]; 157 158 struct { 159 uint32_t numViews; 160 uint32_t viewId0; 161 struct ruvd_mvc_element mvcElements[1]; 162 } mvc; 163 }; 164 165 struct ruvd_h265 { 166 uint32_t sps_info_flags; 167 uint32_t pps_info_flags; 168 169 uint8_t chroma_format; 170 uint8_t bit_depth_luma_minus8; 171 uint8_t bit_depth_chroma_minus8; 172 uint8_t log2_max_pic_order_cnt_lsb_minus4; 173 174 uint8_t sps_max_dec_pic_buffering_minus1; 175 uint8_t log2_min_luma_coding_block_size_minus3; 176 uint8_t log2_diff_max_min_luma_coding_block_size; 177 uint8_t log2_min_transform_block_size_minus2; 178 179 uint8_t log2_diff_max_min_transform_block_size; 180 uint8_t max_transform_hierarchy_depth_inter; 181 uint8_t max_transform_hierarchy_depth_intra; 182 uint8_t pcm_sample_bit_depth_luma_minus1; 183 184 uint8_t pcm_sample_bit_depth_chroma_minus1; 185 uint8_t log2_min_pcm_luma_coding_block_size_minus3; 186 uint8_t log2_diff_max_min_pcm_luma_coding_block_size; 187 uint8_t num_extra_slice_header_bits; 188 189 uint8_t num_short_term_ref_pic_sets; 190 uint8_t num_long_term_ref_pic_sps; 191 uint8_t num_ref_idx_l0_default_active_minus1; 192 uint8_t num_ref_idx_l1_default_active_minus1; 193 194 int8_t pps_cb_qp_offset; 195 int8_t pps_cr_qp_offset; 196 int8_t pps_beta_offset_div2; 197 int8_t pps_tc_offset_div2; 198 199 uint8_t diff_cu_qp_delta_depth; 200 uint8_t num_tile_columns_minus1; 201 uint8_t num_tile_rows_minus1; 202 uint8_t log2_parallel_merge_level_minus2; 203 204 uint16_t column_width_minus1[19]; 205 uint16_t row_height_minus1[21]; 206 207 int8_t init_qp_minus26; 208 uint8_t num_delta_pocs_ref_rps_idx; 209 uint8_t curr_idx; 210 uint8_t reserved1; 211 int32_t curr_poc; 212 uint8_t ref_pic_list[16]; 213 int32_t poc_list[16]; 214 uint8_t ref_pic_set_st_curr_before[8]; 215 uint8_t ref_pic_set_st_curr_after[8]; 216 uint8_t ref_pic_set_lt_curr[8]; 217 218 uint8_t ucScalingListDCCoefSizeID2[6]; 219 uint8_t ucScalingListDCCoefSizeID3[2]; 220 221 uint8_t highestTid; 222 uint8_t isNonRef; 223 224 uint8_t p010_mode; 225 uint8_t msb_mode; 226 uint8_t luma_10to8; 227 uint8_t chroma_10to8; 228 uint8_t sclr_luma10to8; 229 uint8_t sclr_chroma10to8; 230 231 uint8_t direct_reflist[2][15]; 232 }; 233 234 struct ruvd_vc1 { 235 uint32_t profile; 236 uint32_t level; 237 uint32_t sps_info_flags; 238 uint32_t pps_info_flags; 239 uint32_t pic_structure; 240 uint32_t chroma_format; 241 }; 242 243 struct ruvd_mpeg2 { 244 uint32_t decoded_pic_idx; 245 uint32_t ref_pic_idx[2]; 246 247 uint8_t load_intra_quantiser_matrix; 248 uint8_t load_nonintra_quantiser_matrix; 249 uint8_t reserved_quantiser_alignement[2]; 250 uint8_t intra_quantiser_matrix[64]; 251 uint8_t nonintra_quantiser_matrix[64]; 252 253 uint8_t profile_and_level_indication; 254 uint8_t chroma_format; 255 256 uint8_t picture_coding_type; 257 258 uint8_t reserved_1; 259 260 uint8_t f_code[2][2]; 261 uint8_t intra_dc_precision; 262 uint8_t pic_structure; 263 uint8_t top_field_first; 264 uint8_t frame_pred_frame_dct; 265 uint8_t concealment_motion_vectors; 266 uint8_t q_scale_type; 267 uint8_t intra_vlc_format; 268 uint8_t alternate_scan; 269 }; 270 271 struct ruvd_mpeg4 { 272 uint32_t decoded_pic_idx; 273 uint32_t ref_pic_idx[2]; 274 275 uint32_t variant_type; 276 uint8_t profile_and_level_indication; 277 278 uint8_t video_object_layer_verid; 279 uint8_t video_object_layer_shape; 280 281 uint8_t reserved_1; 282 283 uint16_t video_object_layer_width; 284 uint16_t video_object_layer_height; 285 286 uint16_t vop_time_increment_resolution; 287 288 uint16_t reserved_2; 289 290 uint32_t flags; 291 292 uint8_t quant_type; 293 294 uint8_t reserved_3[3]; 295 296 uint8_t intra_quant_mat[64]; 297 uint8_t nonintra_quant_mat[64]; 298 299 struct { 300 uint8_t sprite_enable; 301 302 uint8_t reserved_4[3]; 303 304 uint16_t sprite_width; 305 uint16_t sprite_height; 306 int16_t sprite_left_coordinate; 307 int16_t sprite_top_coordinate; 308 309 uint8_t no_of_sprite_warping_points; 310 uint8_t sprite_warping_accuracy; 311 uint8_t sprite_brightness_change; 312 uint8_t low_latency_sprite_enable; 313 } sprite_config; 314 315 struct { 316 uint32_t flags; 317 uint8_t vol_mode; 318 uint8_t reserved_5[3]; 319 } divx_311_config; 320 }; 321 322 /* message between driver and hardware */ 323 struct ruvd_msg { 324 325 uint32_t size; 326 uint32_t msg_type; 327 uint32_t stream_handle; 328 uint32_t status_report_feedback_number; 329 330 union { 331 struct { 332 uint32_t stream_type; 333 uint32_t session_flags; 334 uint32_t asic_id; 335 uint32_t width_in_samples; 336 uint32_t height_in_samples; 337 uint32_t dpb_buffer; 338 uint32_t dpb_size; 339 uint32_t dpb_model; 340 uint32_t version_info; 341 } create; 342 343 struct { 344 uint32_t stream_type; 345 uint32_t decode_flags; 346 uint32_t width_in_samples; 347 uint32_t height_in_samples; 348 349 uint32_t dpb_buffer; 350 uint32_t dpb_size; 351 uint32_t dpb_model; 352 uint32_t dpb_reserved; 353 354 uint32_t db_offset_alignment; 355 uint32_t db_pitch; 356 uint32_t db_tiling_mode; 357 uint32_t db_array_mode; 358 uint32_t db_field_mode; 359 uint32_t db_surf_tile_config; 360 uint32_t db_aligned_height; 361 uint32_t db_reserved; 362 363 uint32_t use_addr_macro; 364 365 uint32_t bsd_buffer; 366 uint32_t bsd_size; 367 368 uint32_t pic_param_buffer; 369 uint32_t pic_param_size; 370 uint32_t mb_cntl_buffer; 371 uint32_t mb_cntl_size; 372 373 uint32_t dt_buffer; 374 uint32_t dt_pitch; 375 uint32_t dt_tiling_mode; 376 uint32_t dt_array_mode; 377 uint32_t dt_field_mode; 378 uint32_t dt_luma_top_offset; 379 uint32_t dt_luma_bottom_offset; 380 uint32_t dt_chroma_top_offset; 381 uint32_t dt_chroma_bottom_offset; 382 uint32_t dt_surf_tile_config; 383 uint32_t dt_uv_surf_tile_config; 384 // re-use dt_wa_chroma_top_offset as dt_ext_info for UV pitch in stoney 385 uint32_t dt_wa_chroma_top_offset; 386 uint32_t dt_wa_chroma_bottom_offset; 387 388 uint32_t reserved[16]; 389 390 union { 391 struct ruvd_h264 h264; 392 struct ruvd_h265 h265; 393 struct ruvd_vc1 vc1; 394 struct ruvd_mpeg2 mpeg2; 395 struct ruvd_mpeg4 mpeg4; 396 397 uint32_t info[768]; 398 } codec; 399 400 uint8_t extension_support; 401 uint8_t reserved_8bit_1; 402 uint8_t reserved_8bit_2; 403 uint8_t reserved_8bit_3; 404 uint32_t extension_reserved[64]; 405 } decode; 406 } body; 407 }; 408 409 #endif 410