1 /* 2 * Copyright © 2020 Advanced Micro Devices, Inc. 3 * 4 * SPDX-License-Identifier: MIT 5 */ 6 7 #ifndef AC_SHADOWED_REGS 8 #define AC_SHADOWED_REGS 9 10 #include "ac_gpu_info.h" 11 12 struct radeon_cmdbuf; 13 14 struct ac_reg_range { 15 unsigned offset; 16 unsigned size; 17 }; 18 19 enum ac_reg_range_type 20 { 21 SI_REG_RANGE_UCONFIG, 22 SI_REG_RANGE_CONTEXT, 23 SI_REG_RANGE_SH, 24 SI_REG_RANGE_CS_SH, 25 SI_NUM_REG_RANGES, 26 }; 27 28 #ifdef __cplusplus 29 extern "C" { 30 #endif 31 32 typedef void (*pm4_cmd_add_fn)(void *pm4_cmdbuf, uint32_t value); 33 34 typedef void (*set_context_reg_seq_array_fn)(struct radeon_cmdbuf *cs, unsigned reg, unsigned num, 35 const uint32_t *values); 36 37 void ac_get_reg_ranges(enum amd_gfx_level gfx_level, enum radeon_family family, 38 enum ac_reg_range_type type, unsigned *num_ranges, 39 const struct ac_reg_range **ranges); 40 void ac_emulate_clear_state(const struct radeon_info *info, struct radeon_cmdbuf *cs, 41 set_context_reg_seq_array_fn set_context_reg_seq_array); 42 void ac_print_nonshadowed_regs(enum amd_gfx_level gfx_level, enum radeon_family family); 43 44 void ac_create_shadowing_ib_preamble(const struct radeon_info *info, 45 pm4_cmd_add_fn pm4_cmd_add, void *pm4_cmdbuf, 46 uint64_t gpu_address, 47 bool dpbb_allowed); 48 #ifdef __cplusplus 49 } 50 #endif 51 52 53 #endif 54