xref: /aosp_15_r20/external/llvm/test/CodeGen/X86/vec_set-B.ll (revision 9880d6810fe72a1726cb53787c6711e909410d58)
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=i386-unknown -mattr=+sse2 | FileCheck %s
3
4; These should both generate something like this:
5;_test3:
6;	movl	$1234567, %eax
7;	andl	4(%esp), %eax
8;	movd	%eax, %xmm0
9;	ret
10
11define <2 x i64> @test3(i64 %arg) nounwind {
12; CHECK-LABEL: test3:
13; CHECK:       # BB#0:
14; CHECK-NEXT:    movl $1234567, %eax # imm = 0x12D687
15; CHECK-NEXT:    andl {{[0-9]+}}(%esp), %eax
16; CHECK-NEXT:    movd %eax, %xmm0
17; CHECK-NEXT:    retl
18  %A = and i64 %arg, 1234567
19  %B = insertelement <2 x i64> zeroinitializer, i64 %A, i32 0
20  ret <2 x i64> %B
21}
22
23define <2 x i64> @test2(i64 %arg) nounwind {
24; CHECK-LABEL: test2:
25; CHECK:       # BB#0:
26; CHECK-NEXT:    movl $1234567, %eax # imm = 0x12D687
27; CHECK-NEXT:    andl {{[0-9]+}}(%esp), %eax
28; CHECK-NEXT:    movd %eax, %xmm0
29; CHECK-NEXT:    retl
30  %A = and i64 %arg, 1234567
31  %B = insertelement <2 x i64> undef, i64 %A, i32 0
32  ret <2 x i64> %B
33}
34
35