xref: /aosp_15_r20/external/llvm/test/CodeGen/X86/vec_set-2.ll (revision 9880d6810fe72a1726cb53787c6711e909410d58)
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=i386-unknown -mattr=+sse2,-sse4.1 | FileCheck %s
3
4define <4 x float> @test1(float %a) nounwind {
5; CHECK-LABEL: test1:
6; CHECK:       # BB#0:
7; CHECK-NEXT:    movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
8; CHECK-NEXT:    retl
9  %tmp = insertelement <4 x float> zeroinitializer, float %a, i32 0
10  %tmp5 = insertelement <4 x float> %tmp, float 0.000000e+00, i32 1
11  %tmp6 = insertelement <4 x float> %tmp5, float 0.000000e+00, i32 2
12  %tmp7 = insertelement <4 x float> %tmp6, float 0.000000e+00, i32 3
13  ret <4 x float> %tmp7
14}
15
16define <2 x i64> @test(i32 %a) nounwind {
17; CHECK-LABEL: test:
18; CHECK:       # BB#0:
19; CHECK-NEXT:    movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
20; CHECK-NEXT:    retl
21  %tmp = insertelement <4 x i32> zeroinitializer, i32 %a, i32 0
22  %tmp6 = insertelement <4 x i32> %tmp, i32 0, i32 1
23  %tmp8 = insertelement <4 x i32> %tmp6, i32 0, i32 2
24  %tmp10 = insertelement <4 x i32> %tmp8, i32 0, i32 3
25  %tmp19 = bitcast <4 x i32> %tmp10 to <2 x i64>
26  ret <2 x i64> %tmp19
27}
28